JPH09307102A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable relieving electric field concentration causing hot carrier deterioration, without obstructing the fining of an MIS(metal insulator semiconductor) structure. SOLUTION: In an MOS(metal oxide semiconductor) structure, a conductivity type is inverted between a source 6 and a drain 5 in a P-type silicon substrate 11 below a gate electrode 1. For example, B(boron) ions having almost the same conductivity type as the conductivity type of the P-type silicon substrate 11 are implanted in a position which is isolated from both end parts of the source 6 and the drain 5 in the channel region, and an electric field relieving region 4 is arranged. When a voltage is applied to a gate electrode 1, inversion of the electric field relieving region 4 is decreased, and resistance becomes high. By the effect of voltage drop of the high resistance region, electric fields concentration in the end part of the drain is relieved.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a MIS (Metal In
(sulator semiconductor) structure, a semiconductor device having a structure in which an electric field relaxation region for relaxing electric field concentration at a drain end is formed when a voltage forming a channel is applied.

[0002]

2. Description of the Related Art A semiconductor device having a MIS structure includes a fine MOS (Metal Oxide Semiconductor) transistor. In this fine MOS transistor, when a voltage is applied to the gate electrode, an inversion layer called a channel is formed under the gate electrode and the current flowing between the drain and the source is controlled.

However, in the fine MOS transistor described above, when the drain potential increases and approaches the gate potential, the inversion of the channel near the drain electrode becomes weaker than in other portions. In such a case, the electric field applied between the drain and the source is not uniform under the gate electrode,
The electric field distribution in the vicinity of the drain becomes higher than that in other portions.
When the high electric field near the drain becomes extremely large, hot carriers are generated in a part of the current flowing through the channel, and the gate oxide film is deteriorated. This deterioration of the gate oxide film causes deterioration of transistor characteristics.

As described above, in recent years, with the miniaturization of the MIS structure, the hot carrier deterioration caused by the electric field concentration at the drain end has become a problem. This hot carrier deterioration is caused by the generation of a high electric field portion at the gate end, and becomes remarkable as the electric field between the drain and the source increases as miniaturization progresses. Therefore, conventionally, an LDD (Lightly Doped Drain Structure) structure has been proposed in which a low-resistance electric field relaxation layer is provided at the drain end to prevent electric field concentration at the drain end, thereby preventing hot carrier deterioration.

This LDD structure will be described with reference to FIG. In the N-type channel MOS transistor shown in FIG. 20, a gate oxide film 2 and a gate electrode 1 are laminated on a P-type silicon substrate 11 and covered with an insulating film 3, and a source 6 and a drain are formed on the P-type silicon surface. And 5 are formed by an N-type diffusion layer to form an N-type conductive layer, and have low resistance between the gate oxide film 2 and the end of the source 6 and between the gate oxide film 2 and the end of the drain 5. The electric field relaxation layers 7 and 7 are provided.

N-type channel M having the above LDD structure
In the OS transistor, the electric field relaxation layer 7 formed at the end of the drain 5 weakens the electric field in the depletion layer at the end of the drain 5, thereby reducing the hot electron effect. As a result, the hot carrier deterioration life can be extended.

[0007]

However, in the semiconductor device according to the above-mentioned conventional example, when the electric field relaxation layers 7 and 7 are extended in accordance with the increase of the electric field between the drain 5 and the source 6 in the LDD structure, the fine MIS structure is formed. Since the area occupied by the electric field relaxation layers 7 and 7 per element increases with the increase in size, there is a problem that the miniaturization of the MIS structure is hindered.

An object of the present invention is to provide a semiconductor device capable of mitigating the electric field concentration that causes hot carrier deterioration without hindering the miniaturization of the MIS structure.

[0009]

According to another aspect of the present invention, there is provided in a semiconductor device, a voltage for forming a channel in a gate is applied to at least a part of a channel forming region which is separated from both a source and a drain. When the gate electrode is applied, the electric field relaxation region has a high resistance, and the electric field relaxation region has a high resistance when the voltage is applied. Becomes larger, and the electric field is concentrated compared to other regions. As a result, the electric field concentration at the source or drain end can be relaxed in the electric field relaxation region. So the source,
Since hot carrier deterioration can be suppressed without providing an electric field relaxation layer having, for example, an LDD structure at each end of the drain, M does not depend on the area of the electric field relaxation layer.
It becomes possible to realize miniaturization of the IS structure.

A semiconductor device according to a second aspect of the invention is
Since the electric field relaxation layer is formed so that its impurity concentration is higher than that of the other channel forming regions, the inversion is weakened in this region, and the electric field concentration at the source or drain end can be relaxed as described above. In the semiconductor device according to the third aspect of the present invention, since the notch portion is provided in at least a part of the gate electrode on a region separated from both the source and the drain of the channel formation region,
When the gate electrode is applied, no electric field is generated from the cutout portion, and the channel region located below the cutout portion weakens the inversion. This can alleviate the electric field concentration at the source or drain end as described above.

A semiconductor device according to a fourth aspect of the invention is
At least part of the gate oxide film is provided with a protrusion having a thickness greater than that of the other on the region separated from both the source and the drain of the channel formation region. The electric field is weaker than others,
The channel region located under the protrusion weakens the inversion. This can alleviate the electric field concentration at the source or drain end as described above.

[0012]

Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. First, the first embodiment will be described. FIG. 1 is a side sectional view showing a first embodiment of a semiconductor device according to the present invention,
The semiconductor device shown in the figure has an N-type channel M as an example.
It is a side sectional structure of an OS transistor.

In the N-type channel MOS transistor shown in FIG. 1, for example, a gate oxide film 2 and a gate electrode 1 made of polycrystalline silicon are laminated on a P-type silicon substrate 11 having a P-type conductivity. The surface of the laminate is covered with a side wall oxide film 3 to be insulated from the outside, and a source 6 and a drain 5 are arranged at both ends of the gate oxide film 2, respectively. ), A channel region formed between the drain 5 and the source 6 is formed with an electric field relaxation region 4 that weakens inversion weaker than that of the P-type silicon substrate 11. This electric field relaxation region 4
Has the same conductivity type as that of the silicon substrate 11 and has an impurity concentration higher than that of the substrate 11. When a voltage for forming a channel is applied to the gate electrode 1, Also, the inverted state becomes weaker.

Next, a method of manufacturing the above N-type channel MOS transistor will be described in detail. 2 to 6 are the first
FIG. 9 is a cross sectional view illustrating a manufacturing process of the N-type channel MOS transistor according to the embodiment of FIG. First, according to a general manufacturing process of an N-type channel MOS transistor, after the P-type silicon substrate 11 is formed, the P-type silicon substrate 11 is thermally oxidized to form the gate oxide film 2 on its surface, while P The local oxidation of LOCOS (Local Oxidation of
Silicon) oxide films 8 and 8 are formed (see FIG. 2). On the gate oxide film 2, polycrystalline silicon (Doped PolySi) 10 for forming the gate electrode 1 later is deposited (see FIG. 3).

Next, the deposited polycrystalline silicon 10
A mask 9 made of a resist is formed on the top by a photolithography process, and an opening 9a is provided in a part of the mask 9. Part of the polycrystalline silicon 10 is exposed from the opening 9a. In this state, B (boron) ions are implanted from above the mask 9. In this case, B ions pass through the opening 9a provided in the mask 9 and the P-type silicon substrate 11 through the polycrystalline silicon 10 and the gate oxide film 2.
Is injected into. In the P-type silicon substrate 11, the impurity concentration of this portion becomes high due to the implantation of B ions, and the channel region formed with the application of the gate electrode 1 has a high resistance, that is, electric field relaxation for weakening inversion. Region 4 is formed (see FIG. 4).

After that, when the mask 9 is peeled off, a photolithography process, an etching process, and a thermal oxidation process are performed on the portion (polycrystalline silicon 10) to be the gate electrode 1 according to a conventional transistor manufacturing method. As a result, the sidewall oxide film 3 made of a thermal oxide film is formed so as to cover the stacked body made of the gate oxide film 2 and the gate electrode 1 (see FIG. 5). In this state, ion implantation with N-type ions (for example, phosphorus and arsenic ions) is performed again on the sidewall oxide film 3 and the gate oxide film 2 (FIG. 6), and the transistor structure is completed as shown in FIG. Note that in the transistor structure shown in FIG. 1, the electric field relaxation region 4, the drain 5, the source 6, and the LOCOS oxide film 8 have a positional relationship as shown in FIG. 7 when viewed from above.

Normally, when a voltage is applied to the gate electrode 1 to form an inversion layer called a channel under the gate electrode 1, the potential of the drain 5 increases, and when the gate potential is approached, the inversion of the channel near the drain 5 occurs. Is weaker than other portions, so that the electric field distribution near the drain 5 is high.
Therefore, as shown in FIGS. 1 and 4 to 7, the drain 5
In the channel region between the sources 6, the electric field relaxation region 4 is set so as not to contact the drain 5 but to be separated from the drain 5 so that the electric field concentration near the drain 5 can be mitigated.

As described above, by implanting, for example, B (boron) ions as an impurity of the same conductivity type as the silicon substrate 11 which prevents the channel formation, into a part of the channel region below the gate electrode 1 (eg, near the drain 5). It is possible to obtain the electric field relaxation region 4 in a part of the channel region in which the inversion becomes weak when the voltage is applied to the gate electrode 1, that is, the resistance becomes relatively high. Since the electric field relaxation region 4 is a weak inversion layer in which the inversion is further weakened as the potential of the drain 5 rises, the electric field relaxation region 4 becomes a high resistance region and the drain 5 is utilized by utilizing the voltage drop due to the high resistance.
The electric field concentration between the source 6 and the vicinity of the drain 5 can be relaxed. Further, when the potential of the drain 5 is low, a sufficient channel is formed in the weak inversion portion, while as the potential of the drain 5 increases, the channel region changes so as not to have a high resistance. A resistance can be formed according to the potential of the.

Further, in the present embodiment, the channel separated from the drain 5 and the source 6 is provided without providing the electric field relaxation regions 7 and 7 adjacent to the drain 5 and the source 6 as in the LDD structure shown in FIG. Since the electric field relaxation region 4 is provided at an arbitrary position of the region, the electric field relaxation region 4 does not interfere with the setting of the gate length to be short, so that the area per element is reduced and miniaturization is performed. Can be improved.

Differences in electric field concentration between the conventional N-type channel MOS transistor structure and the N-type channel MOS transistor structure according to the present embodiment will now be described with reference to FIGS.
This will be described with reference to the lateral electric field (calculated value) in FIG. FIG. 8 shows a distance (μ) indicating the electric field strength (v / cm) and the gate length in a general structure of an N-type channel MOS transistor.
m) and FIG. 9 is a graph showing the relationship between the electric field strength (v / cm) and the distance (μm) indicating the gate length in the LDD structure of the N-type channel MOS transistor. FIG. 10 shows the electric field strength (v) in the N-type channel MOS transistor structure according to this embodiment.
/ Cm) and a distance (μm) indicating a gate length. And FIG. 11 is FIG. 8, FIG. 9, FIG.
It is a graph figure which combined each graph shown in FIG. In addition, in the examples of FIGS. 8 to 11, the value of the electric field on the vertical axis represents a value of 1/10 5th. In addition, the potential of the drain 5 is, for example, 5 V,
The gate potential is set to 2.5 v, for example, and the gate length (for example, 1.0 μm) and the threshold are set to be substantially the same. However, in the graph of the LDD structure shown in FIG. 9, since the distance between the electric field relaxation regions 7 and 7 (see FIG. 20) is set with respect to the gate length, this is also set to 1.0 μm as an example for comparison. .

In a general N-type channel MOS transistor, as shown in FIG.
The slope is gentle up to about 0.0 to 0.6 μm, but is steep at the peak portion causing electric field concentration between 0.6 to 0.9 μm. Further, in the N-type channel MOS transistor having the LDD structure, as shown in FIG.
In the electric field intensity curve 90, the slope of the peak portion causing electric field concentration is gentler than that in the graph shown in FIG. 8, and the peak value is also lowered (see FIG. 11).

In the N-type channel MOS transistor according to the present embodiment, the electric field intensity curve 100 as shown in FIG. 10 is compared with the graph shown in FIG.
It has a first peak portion P1 near 0.6 μm and a second peak portion P2 lower than the peak portion of the graph shown in FIG. 8 near 0.8 μm that follows (see FIG. 11). The peak portion P1 of 1 corresponds to the electric field relaxation region 4. The electric field relaxation region 4 is set in the vicinity of the drain 5 also from the generation position of the first peak portion P1.

Therefore, the LDD structure (see FIG. 20) and the structure according to the present embodiment (see FIG. 1) are different from those of the general N-type channel MOS transistor structure (not shown) in FIG.
As shown in FIG. 1, the peak value of the electric field strength is decreased in all cases, which means that the electric field is relaxed. Particularly, in the structure according to the present embodiment shown in FIG. 10, the area of the peak portion (around 0.6 μm) of the electric field intensity corresponding to the electric field relaxation region 4 increases, so that the electric field of other portions is increased by the increased area. Since it decreases, the peak electric field can be lowered even at the end of the drain 5.

Next, a second embodiment will be described. FIG. 12 is a side sectional view showing a second embodiment of the semiconductor device according to the present invention. The semiconductor device shown in FIG.
Similar to the first embodiment, it is a side sectional structure of an N-type channel MOS transistor. In the N-type channel MOS transistor shown in FIG. 12, for example, a gate oxide film 2 and a gate electrode 1 are laminated on a P-type silicon substrate 11 and a partial cutout 1a is provided for the gate electrode 1, and The surface of the resulting laminate is covered with a sidewall oxide film 3 to insulate it from the outside, and a source 6 and a drain 5 are arranged at both ends of the gate oxide film 2, respectively. 11 inside) drain 5 source 6
The electric field relaxation region 4 is formed under the cutout portion 1a of the channel region between them.
It has a structure to obtain an electric field relaxation region 41 having a function similar to.

Next, a method of manufacturing the above-mentioned N-type channel MOS transistor will be described in detail. 13 and 14
FIG. 6A is a cross-sectional view illustrating the manufacturing process of the N-type channel MOS transistor according to the second embodiment. Also in the second embodiment, similarly to the first embodiment described above, first, the steps up to the step of depositing the polycrystalline silicon 10 for forming the gate electrode 1 shown in FIG. 3 are performed.

Next, the deposited polycrystalline silicon 10
In the photolithography / etching step and the thermal oxidation step, the gate electrode 1 having the cutout portion 1a is formed at the same position as the position where the electric field relaxation region 4 is provided in the channel region in this case as well. Sidewall oxide film 3 serving as an insulating film is formed (see FIG. 13). In this state, ion implantation with N-type ions is performed again from the side wall oxide film 3 and the gate oxide film 2 (FIG. 14) to complete the transistor structure as shown in FIG.

As described above, when the cutout portion 1a that does not generate an electric field is provided in at least a part of the gate electrode 1, the electric field below the cutout portion 1a becomes weaker when applied to the gate electrode 1, that is, Since the electric field relaxation region 41 where the inversion becomes weak is formed at the same position as the electric field relaxation region 4 described above, the same effect as that of the first embodiment described above can be obtained. next,
A third embodiment will be described.

FIG. 15 is a side sectional view showing a third embodiment of the semiconductor device according to the present invention. The semiconductor device shown in FIG. 15 has the same N as the first and second embodiments. 2 is a side sectional structure of a channel MOS transistor. This FIG.
The N-type channel MOS transistor shown in FIG.
The gate oxide film 2 and the gate electrode 1 are laminated on the P-type silicon substrate 11 upward, and the gate oxide film 2 is partially provided with a protruding portion 2a on the gate electrode 1 side (upper side) and has a film thickness larger than the others. And the surface of the resulting laminate is covered with a side wall oxide film 3 to insulate it from the outside, and a source 6 and a drain 5 are arranged at both ends of the gate oxide film 2 respectively. It has a structure for obtaining an electric field relaxation region 42 having the same function as that of the electric field relaxation region 4 below the protruding portion 2a of the channel region between the drain 5 and the source 6 in the P-type silicon substrate 11).

Next, a method of manufacturing the above-mentioned N-type channel MOS transistor will be described in detail. 16 to 19 are cross-sectional views for explaining the manufacturing process of the N-type channel MOS transistor according to the third embodiment. In the third embodiment, like the first embodiment described above, first,
LOCOS oxide films 8 and 8 are formed on the P-type silicon substrate 11 by selective oxidation, and then a thin oxide film is formed by thermal oxidation (see FIG. 16). After that, at the same position as the position (distance in the lateral direction of the channel region) where the notch 1a for obtaining the electric field relaxation region 4 in the first embodiment or the electric field relaxation region in the second embodiment is arranged, A part of the gate oxide film 2 is formed in the etching process (see FIG. 17).

Next, the gate oxide film 2 is formed again by the second thermal oxidation of the P-type silicon substrate 11. At that time, a part of the gate oxide film 2 is already formed in the step shown in FIG. Since it is formed with a thickness, the gate oxide film 2 provided by the second thermal oxidation is added. As a result, as shown in FIG. 18, a protruding portion 2a having a thickness higher than that of the other portions is formed in the portion of the gate oxide film 2 formed by the first thermal oxidation.

After that, similarly to the first embodiment described above, a step of depositing the polycrystalline silicon 10 to form the gate electrode 1 and then forming the sidewall oxide film 3 to be an insulating film is performed. In this state, ion implantation with N-type ions is performed again from the side wall oxide film 3 and the gate oxide film 2 (see FIG. 1).
9), the transistor structure is completed as shown in FIG. In this way, if the protrusion 2a having a film thickness larger than that of the other is provided at least in part on the gate oxide film 2, the gate electrode 1
When the voltage is applied to the electric field, the electric field below the projecting portion 2a becomes weak, that is, the inversion is weakened. The electric field relaxation region 42 is formed at the same position as the electric field relaxation region 4 described above. The same effect as that of each of the second embodiments can be obtained.

By adopting this step, the electric field relaxation region 42 in which a part of the gate oxide film is thickened can be easily formed. In the first, second and third embodiments described above, the N-type channel MOS transistor has been described as an example, but the present invention is a P-type channel M transistor.
It can also be applied to an OS transistor. In this P-type channel transistor, for example, a fine M of the order of submicron
Since hot carrier deterioration becomes a problem from the OS transistor, the hot carrier deterioration can be prevented by providing an electric field relaxation region corresponding to the weak inversion layer in the channel region as in the case of the N-type channel MOS transistor.

[Brief description of drawings]

FIG. 1 is a side sectional view showing a first embodiment of a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view illustrating the manufacturing process of the MOS transistor of the first embodiment.

FIG. 3 is a cross-sectional view explaining the manufacturing process of the MOS transistor of the first embodiment.

FIG. 4 is a cross-sectional view illustrating the manufacturing process of the MOS transistor of the first embodiment.

FIG. 5 is a cross-sectional view illustrating the manufacturing process of the MOS transistor of the first embodiment.

FIG. 6 is a cross-sectional view illustrating the manufacturing process of the MOS transistor of the first embodiment.

FIG. 7 is a top view showing a first embodiment of a semiconductor device according to the present invention.

FIG. 8 is a graph showing the electric field strength in the channel region of a MOS transistor.

FIG. 9 is a graph showing the electric field intensity in the channel region of a MOS transistor having an LDD structure.

FIG. 10 is a graph showing the electric field strength in the channel region of the MOS transistor of the first embodiment.

FIG. 11 is a graph obtained by combining the graphs shown in FIGS. 8, 9 and 10.

FIG. 12 is a sectional view showing a second embodiment of a semiconductor device according to the present invention.

FIG. 13 is a cross-sectional view illustrating the manufacturing process of the MOS transistor of the second embodiment.

FIG. 14 is a cross-sectional view illustrating the manufacturing process of the MOS transistor of the second embodiment.

FIG. 15 is a sectional view showing a third embodiment of a semiconductor device according to the present invention.

FIG. 16 is a cross-sectional view illustrating the manufacturing process of the MOS transistor of the third embodiment.

FIG. 17 is a cross-sectional view illustrating the manufacturing process of the MOS transistor of the third embodiment.

FIG. 18 is a cross-sectional view illustrating the manufacturing process of the MOS transistor of the third embodiment.

FIG. 19 is a cross-sectional view illustrating the manufacturing process of the MOS transistor of the third embodiment.

FIG. 20 is a cross-sectional view of a MOS transistor having an LDD structure.

[Description of Reference Signs] 1 gate electrode 1a cutout 2 gate oxide film 2a protrusion 3 sidewall oxide film 4 electric field relaxation region 5 drain 6 source 8 LOCOS oxide film 11 P-type silicon substrate 41, 42 electric field relaxation region

Claims (4)

[Claims] 1. A semiconductor device in which a channel is formed by inverting the conductivity type of the semiconductor substrate between a source and a drain in a semiconductor substrate below a gate electrode. A semiconductor, characterized in that an electric field relaxation region is provided in a region distant from any of the regions, when the voltage for forming the channel is applied to the gate electrode, the inversion state is weaker and the resistance becomes higher than that in other regions. apparatus. 2. The electric field relaxation region is a region for forming the channel, and has a higher impurity concentration in the source and drain than in other regions for forming the channel. The semiconductor device according to claim 1. 3. A semiconductor device in which a channel is formed by inverting the conductivity type of the semiconductor substrate between a source and a drain in a semiconductor substrate below a gate electrode, the semiconductor forming the channel in the source-drain direction. A semiconductor device, wherein a notch is provided in at least a part of the gate electrode on a region of the substrate which is separated from both the source and the drain. 4. A semiconductor device in which a channel is formed by reversing the conductivity type of the semiconductor substrate between a source and a drain in the semiconductor substrate below the gate electrode laminated on the gate oxide film, in the source-drain direction. A protruding portion is provided on at least a part of the gate oxide film on a region of the region of the semiconductor substrate forming the channel, which is separated from both the source and the drain, so as to have a film thickness larger than other portions. A semiconductor device characterized by the above.