JP3029676B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a fine structure MOS type semiconductor device used for a high density integrated circuit.

[0002]

2. Description of the Related Art High integration is achieved by miniaturization of devices, but this largely depends on the development of processing technology and material technology. However, device miniaturization cannot be achieved simply by reducing the device size. This is because when a device is made smaller, a phenomenon that is not noticed when the device size is large is closed up, which is a serious drawback in a highly integrated circuit.

[0003] The short channel effect is an effect caused by a reduction in the size of an element. As the element size decreases, the influence of the source and drain on the electric field and potential in the channel region becomes significant. Therefore, one-dimensional approximation of the electric field and the electric potential cannot be performed, and it is necessary to consider the original two-dimensional or three-dimensional electric field distribution and electric potential distribution. The short channel effect arises from the spread of the two-dimensional distribution of the electric field and the electric potential.

A typical short channel effect is a decrease in the threshold voltage Vth. As the channel length L decreases for both the n-channel and the p-channel, | Vth | decreases. This is because, as the channel length becomes shorter, the charge in the channel region is greatly affected by not only the gate but also the depletion layer charge in the source and drain regions, the electric field and the potential distribution. In addition to lowering the threshold voltage,
Reduction of the breakdown voltage between the drain and the drain is also a major problem associated with the shortened channel. When the channel length becomes short, the drain depletion layer approaches the source, and the drain depletion layer and the source depletion layer are connected. In this state, the drain electric field affects the source side and lowers the diffusion potential near the source, so that a current flows between the source and the drain even when no channel is formed. This is a punch through
This is a phenomenon called (punch-through). When punch through begins to occur, the drain current does not saturate even in the saturation region, and increases sharply with an increase in drain voltage.

In addition, as the MOS transistor becomes finer, a high electric field is applied to the source-drain junction, which causes a problem that hot carriers are generated, which deteriorates the device. A transistor having an LDD structure is well known as a transistor for relaxing a high electric field at a source / drain junction.

However, when the MOS transistor is further miniaturized without changing the power supply voltage, the electric field concentration in the channel direction further increases, and an n ⁻ layer which is a low concentration impurity layer like a transistor having an LDD structure is provided. Therefore, the effect of only reducing the electric field concentration in the channel direction cannot be followed.

[0007] Therefore, in 1987 IEDM LDD
Among the structured transistors, a transistor (overlap LDD transistor) having a structure in which an n ⁺ region enters under the gate (that is, all n ⁻ regions are located under the gate) is used.
It has been reported that the transistor is more reliable because the electric field in the channel reduces the electric field in the channel direction at the junction of the diffusion layer.

The gate overlap L announced at this time
FIG. 31 shows a manufacturing process of the DD transistor. First, p
A gate oxide film 21 is grown on the surface of a mold silicon substrate 20, and a first polycrystalline silicon 22 of about 500 angstroms is deposited thereon. A native oxide film 23 of about 5-10 Å is grown on the first polycrystalline silicon 22 and a second oxide film of about 1000 Å is formed thereon.
Polycrystalline silicon 24 is deposited. (FIG. 31 (a)).

Further, a silicon oxide film 25 is deposited thereon by a CVD method, patterned by using a pattern of a gate electrode, and the silicon oxide film 25 is used as a mask to perform a second selective dry etching. The polycrystalline silicon 24 is etched. This etching is stopped at the natural oxide film 23. Thereafter, n-type impurities are ion-implanted using silicon oxide film 25 as a mask to form n ⁻ diffusion layer 27. At this time, the n-type impurity is
Ions are implanted at an acceleration voltage large enough to pass through the polycrystalline silicon film 22 (FIG. 31B).

Further, as shown in FIG. 31C, a silicon oxide film 26 serving as a side wall is deposited on the entire surface by a CVD method.
This is etched back using high selective ion etching. After the first polycrystalline silicon is patterned and thinly post-oxidized to prevent channeling, an n ⁺ impurity is ion-implanted from outside the silicon oxide film side wall 26 and a thermal process is performed to obtain a gate overwrap. The structure is completed.

However, in this method, firstly, as described above, the electric field in the channel direction can be alleviated by making the transistor have the overlapping LDD structure. Since the directional electric field is concentrated, it is necessary to reduce the channel direction electric field by changing the structure of the transistor.

Second, the conventional gate overlap transistor has a drawback that the parasitic capacitance due to the overlap portion between the diffusion layer and the gate is large, which is not suitable for high speed operation.

Third, it is questionable whether the etching can be stopped by the natural oxide film when the second polycrystalline silicon is etched in this manufacturing process. If the first polycrystalline silicon deposited first is etched without stopping the etching with the natural oxide film, the profile of the n ^- impurity is not as desired, and the desired transistor characteristics cannot be obtained. Also, the etching of the second polycrystalline silicon does not proceed sufficiently,
If the native oxide film is left as it is, there is also a problem of insulation in the gate.

Fourth, in order to leave a CVD silicon oxide film serving as a mask in this manufacturing process, the gate has a high aspect ratio and a large step.

Fifth, in the manufacturing process, post-oxidation is performed before n ⁺ ion implantation, so that a gate bird's-peak is generated, and a mechanical stress in that portion is increased, which is a cause of a decrease in reliability. Become.

Sixth, if the first polycrystalline silicon is oxidized by the last heat step in the manufacturing process, a complete overlap structure may not be realized.

Seventh, there is a problem that the manufacturing process is complicated as a whole.

[0018]

As described above, the conventional MOS transistor has a problem that a short channel effect such as a decrease in the threshold value as the channel length L decreases becomes apparent. This is because the charge in the channel region is greatly affected by not only the gate voltage but also the depletion layer charge in the source and drain regions, the electric field and the potential distribution, and the controllability of the gate deteriorates. It is considered.

In addition, the conventional LDD transistor has a limit in relaxing the electric field in the channel direction, and the conventional gate-overlap LDD transistor proposed to compensate for the limitation has an unstable manufacturing process. MO easily
There is a problem that an S transistor cannot be obtained. Further, as the miniaturization of elements further progresses, it is necessary to further increase the reliability, and it is necessary to form a transistor having high driving capability, high speed, and strong short channel effect.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a transistor having a high driving capability, a high speed, and a strong short-channel effect even when the element is miniaturized.

[0021]

Therefore, according to the present invention, a conductive film is formed on a side wall of a gate electrode, and a dielectric constant between the conductive film and the substrate is higher than that of a gate insulating film below the gate electrode. The insulating film is in contact with the side wall film on one flat surface, and the insulating film protrudes below the gate electrode. For example, a sidewall used for forming a conventional LDD structure is formed of a conductive material, and an insulating film having a higher dielectric constant than a gate insulating film below a gate electrode is interposed between the conductive material and the substrate. Like that.

The conductive material on the side wall is selected so that the work function difference between the conductive material and the Si substrate is smaller than the work function difference between the gate electrode and the Si substrate.

According to the method of the present invention, a high-dielectric-constant insulating film (hereinafter referred to as a high-dielectric film) is formed on the surface of a silicon substrate, and a silicon oxide film is deposited thereon. A resist pattern is formed so as to cover the region other than the region, and using this resist pattern as a mask, the silicon oxide film, the high dielectric constant insulating film, and the gate insulating film in the gate electrode forming region are patterned and further exposed. A gate insulating film is formed on the resulting substrate, a gate electrode material is deposited on the entire surface, a resist having a low viscosity coefficient is applied on the entire surface, and the surface is flattened. After etching by anisotropic etching to completely bury the electrode material in the recesses of the silicon oxide film, the silicon oxide film is removed, and the gate electrode is further masked. A low-concentration impurity ion implantation is performed as a step to form a low-concentration region, a conductive material is further deposited on the entire surface, anisotropic etching is performed on the entire surface, and a sidewall conductor film is formed while leaving sidewalls on both sides of the electrode material. Using the sidewall conductor film and the gate electrode as a mask, high-concentration impurity ions are implanted to form a source / drain region composed of a high-concentration region.

That is, for example, a step of forming an element isolation region on the surface of a Si silicon substrate, further forming a gate insulating film and a high dielectric constant insulating film, and further forming a silicon oxide film thereon by a CVD method and performing a heat treatment. And pattern with resist
Using a resist as a mask, the CVD silicon oxide film, the high dielectric film, and the gate insulating film in the gate electrode formation region are removed by highly selective anisotropic etching. A gate insulating film on the exposed substrate, deposit an electrode material on the entire surface, paint a resist with a low viscosity coefficient on the entire surface, flatten the entire surface, and make the resist anisotropic. The electrode material is removed by anisotropic etching, and the electrode material is further removed by anisotropic etching to completely bury the material in the hole of the CVD silicon oxide film. (The above three steps are not necessarily required when forming a plurality of transistors of the same size. ), A low-resistance material is selectively grown on the electrode material, and CV is etched by NH ₄ F isotropic etching.
The D silicon oxide film is removed, low-concentration impurity ion implantation is performed, and a conductive material is further deposited on the upper layer, high-concentration impurity ion implantation is performed by performing anisotropic etching over the entire surface and leaving sidewalls on both sides of the electrode material. Deposit an insulating film and
A contact hole is formed in the drain region to form an electrode.

Preferably, the side wall used for manufacturing the LDD structure is formed of a conductive material so as to have conductivity with the gate, and the gate has a silicide structure. I have.

[0026]

According to the present invention, a high dielectric material having a higher relative dielectric constant than the gate insulating film below the gate electrode is interposed between the side wall conductive material and the substrate. The vertical electric field is further strengthened at the side wall portion, and the channel electric field is further reduced. Further, since the side wall film for forming the LDD structure is formed of the conductor film electrically connected to the gate electrode, the low concentration impurity diffusion layer completely covers the gate electrode (including the side wall). As a result, the controllability of the gate electrode with respect to the potential under the gate is improved.

In this way, high reliability, high driving capability,
It is possible to form a MOS transistor which is high-speed and resistant to a short channel effect.

Also, since this conductive material is selected so that the work function difference between the Si substrate and the gate electrode is smaller than the work function difference between the gate electrode and the Si substrate, the gate electrode with respect to the potential on the gate is reduced. , The controllability of the transistor is improved, and a transistor resistant to the short-channel effect can be realized.

The speed is high because the gate has a silicide structure.

According to the method of the present invention, in the MOS transistor, an electrode material is buried by making a hole in the CVD silicon oxide deposited on the entire surface and using a resist etch back method.
After the CVD silicon oxide is removed by isotropic etching, a conductive material is deposited on the entire surface, and the entire surface is etched back so as to leave the side walls. Therefore, as seen in the conventional gate-overlap LDD transistor. It can be formed without using an unstable process such as stopping etching with a natural oxide film, and a gate-overlap LDD transistor can be obtained with good reproducibility.

[0031]

Embodiments of the present invention will be described below.

Embodiment 1 FIGS. 1 and 2 are a plan view showing a MOS transistor according to a first embodiment of the present invention and a sectional view taken along the line AA 'of FIG.

In this LDDMOS type transistor, n
A p-channel MOS transistor is formed in an element region 10 isolated by an element isolation region 2 formed in a silicon substrate 1, and a polycide comprising n ⁺ polycrystalline silicon 6 a and tungsten 6 b is formed on the surface of the substrate 1. A sidewall conductor film 7 made of tungsten is formed on the sidewall of the gate electrode 6 having the structure, and ion implantation is performed using the tungsten as a mask to form an LDD structure. A gate electrode 6 is provided between the sidewall conductor film 7 and the silicon substrate 1. This is characterized in that an insulating film having a higher dielectric constant than the lower gate insulating film 17 is interposed. Here, a silicon oxide film having a thickness of 100 angstroms is used as the gate insulating film 17, and a silicon oxide film 4 having a thickness of 50 angstroms and a silicon nitride film 5 having a thickness of 100 angstroms are formed as insulating films under the side wall conductive film. A laminated film is used.

Then, a low concentration of p
A p-type impurity region 8 is formed, and a p ⁺ -type impurity region 9 having a high concentration is formed outside thereof to form a source / drain. Here, 11 is an interlayer insulating film, and 12 is a source / drain contact. Further, an impurity is introduced in advance for controlling the threshold value on the surface of the silicon substrate in a region corresponding to a region under the gate electrode, and an n-type impurity region 3 is formed. This impurity is introduced for controlling the threshold value, and may not be formed.

According to this structure, since the side wall film for forming the LDD structure is constituted by the side wall conductor film electrically connected to the gate electrode, the low concentration impurity diffusion layer 8 is formed by the gate electrode (side wall). ), And the controllability to the potential under the gate of the gate electrode is improved.

A gate is provided between the side wall conductive material and the substrate.
Since the high dielectric material, which has a higher dielectric constant than the gate insulating film below the gate electrode, is interposed, the vertical electric field is further strengthened at the side wall and the channel electric field is further reduced. The reliability can be maintained even in the case of miniaturization.

In this way, high reliability, high driving capability,
It is possible to form a MOS transistor which is high-speed and resistant to a short channel effect.

The side wall conductor film is made of tungsten, and the work function difference with respect to the Si substrate is smaller than the work function difference with respect to the gate electrode made of the n ⁺ polycrystalline silicon film with respect to the Si substrate. The controllability of the gate with respect to the potential on the gate is improved, and a transistor which is resistant to the short channel effect can be realized. In addition, since the gate has a polycide structure, the speed is high. The conductivity type of the substrate can be applied to both p and n, and the substrate structure can be variously modified.
For example, an n-type Si substrate may be used to form a p-channel MOS transistor, or a high-concentration n-type well formed in an n-type or p-type Si substrate may be used. Similarly, a p-type Si substrate may be used to form an n-channel MOS transistor, or a high-concentration p-type well formed in an n or p-type Si substrate may be used.

In the above embodiment, the isolation insulating film 2 is formed by the selective oxidation method (LOCOS method). However, these isolation techniques are not limited to the embodiment, and the oxide film embedding method (BOX method) may be used. Alternatively, a BOX method (so-called trench isolation method) for deeply digging a groove can be applied.

A gate electrode 6 is formed on each of the regions of the substrate thus separated from each other via a gate insulating film 17. The gate electrode has a polycide structure, and the metal formed on the polycrystalline silicon 6a is not limited to tungsten, but may be another high melting point low resistance material such as molybdenum or titanium.

On both sides of the gate electrode 6, side wall conductor films 7 serving as side walls are formed. In this case, it is desirable to use a material having a smaller work function with respect to vacuum than the lower gate electrode material 6a (n ⁺ polycrystalline silicon), and gold, tungsten, molybdenum, titanium, p ⁺ polysilicon, or the like can be used. Between the sidewall conductor film 7 and the silicon substrate 1, a two-layer structure of a silicon oxide film 4 and a second insulating film 5 such as a silicon nitride film having a higher dielectric constant than the gate insulating film 17 is formed. I have. For example, when silicon oxide is selected as the insulating film below the side wall of the gate insulating film 17 and the gate insulating film 4,
As a material of the high dielectric constant insulating film 5, silicon nitride, tantalum pentoxide, or the like can be considered. The gate insulating film 17 may have a two-layer structure or a three-layer structure by combining silicon oxide and silicon nitride, or may have a single layer of silicon nitride. At this time, a combination of silicon oxide, silicon nitride, tantalum pentoxide, etc.
It may have a layer or four-layer structure. The important thing here is that
This means that the relative dielectric constant of the insulating film between the side wall conductor film 7 and the substrate is higher than the relative dielectric constant of the gate insulating film 17, and it may be one layer of a high dielectric material. Not even. The source / drain region is formed by an n ⁻ -type layer or p ⁻ -type layer 8 as a first low-concentration impurity ion-implanted layer and an n ⁺ -type or p ⁺ -type layer 9 as high-concentration impurity ion-implantation. It is configured. The low concentration impurity layer n is an ion implantation layer ^- -type layer or p ^- type layer 8, gate - a gate electrode 6 as a mask, n ^- arsenic or phosphorus in the case of type layer, p ^- For a type layer It is formed by ion implantation of boron or boron fluoride. The high concentration impurity ion implantation n ⁺ -type layer or p ⁺ -type layer 9 is gate - if the sidewall conductive film 7 is selectively formed on the side wall of the gate electrode of the n ⁺ -type as a mask, phosphorus or arsenic, In the case of a p ⁺ -type layer, it is formed by ion implantation of boron or boron fluoride. The n ⁻ -type layer or the p ⁻ -type layer is configured to be inside the n ⁺ -type layer or the p ⁺ -type layer, respectively, and a so-called LD
Form a D structure. The side wall conductor film 7 is left on the side wall of the gate electrode 6 by anisotropic etching by the technique of the side wall remaining. In the above embodiment, the LDD structure has been described.
The present invention is also applicable to a transistor in which the impurity profile of a diffusion layer such as a structure is changed. If you give specific numbers,
Assuming that the gate length is 0.5 μm, the side wall width is 0.11 μm, and the effective channel length is 0.4 μm, the gate length including the side wall is 0.1 μm.
7 μm.

The substrate on which the elements are formed is covered with an interlayer insulating film 11 made of a silicon oxide film formed by a CVD method, a contact hole is formed in the interlayer insulating film 11, and a metal wiring 12 such as an aluminum film is formed.

Next, an integrated structure of such a transistor will be described.

FIGS. 3 and 4 show the M of the first embodiment.
Plan view when two or more OS transistors (transistor T1 and transistor T2) are formed and their BB ′
It is sectional drawing.

In this embodiment, two or more MOS transistors (transistor T1) of the embodiment shown in FIG.
And a transistor T2), connecting them with a gate polysilicon 6a and a low resistance metal 6b, opening a contact hole on the gate in a region located on the element isolation region 2, and forming a metal wiring 13 such as an aluminum film. Has formed.

The contact on the gate may be made on the element region (on the SDG) as shown in FIG. At this time, this contact is
It is better to take it on the gate of the longer transistor. For example, in the transistor T1 and the transistor T2,
Taking the gate of the transistor T2 having the longer gate length on the gate makes it easier to form a contact from the viewpoint of lithography technology.

However, if it is permissible from the point of view of the lithography technique, the contact may be made at the shorter gate length.

As another method of forming the contact, as shown in FIG. 6, the contact may be formed not only on the gate but also on the side wall conductor film 7. This method can be applied to a case where a contact is formed not only on the element region but also on the element isolation region. When the contact is formed not only on the gate, but also when the side wall conductor film 7 is included, the conductivity of both is improved, and the gate overwrap effect of the transistor works well, so that a highly reliable transistor is expected. Can be.

Next, the manufacturing process of this transistor will be described.

FIGS. 7 to 17 are a cross-sectional view and a plan view showing main steps of a process for manufacturing a MOS transistor according to a second embodiment of the present invention.

First, as shown in FIGS. 7A and 7B,
The impurity concentration is set to about 10 ¹⁶ cm ⁻³ near the surface of the element region 10 by forming a well in a region where a MOS transistor of the silicon substrate 1 is formed, and further by the LOCOS method.
An element isolation insulating film 2 is formed. Then, in each element region, a silicon oxide film 4 having a thickness of about 100 angstroms to be an insulating film below the side wall is formed by a thermal oxidation method, and a silicon nitride film 5 having a thickness of about 100 angstroms is formed by a CVD method. At this time, only the silicon nitride film may be formed.

Thereafter, as shown in FIGS. 8A and 8B, a silicon oxide film 15 having a thickness of about 4000 Å is formed by the CVD method, and heat treatment is performed at 900 ° C. for 60 minutes. It is applied and patterned so that the resist remains in the area other than the gate forming area.

Further, using the resist 16 as a mask, the silicon oxide film 15 exposed from the resist 16 and the silicon nitride film 5 under the resist 16 are subjected to highly selective anisotropic etching such as reactive ion etching (RIE). The silicon oxide film 4 is removed. After that, the surface of the substrate damaged by RIE is processed by NH ₄ F-based processing, and further, ion implantation is performed to prevent punch-through and control a threshold value, thereby forming a channel region 3. This ion implantation may be a normal ion implantation for preventing channeling, but the use of rotary ion implantation is more effective because there is no offset in the channel region below the gate.

Then, as shown in FIG. 9, a silicon oxide film 17 having a thickness of about 100 Å is formed on the exposed silicon substrate 1 by a CVD method, and further contains phosphorus having a thickness of about 6000 Å. Polycrystalline silicon 6a is deposited. Thereafter, the polycrystalline silicon 6 is buried in the hole formed by the silicon oxide film 15, and two transistors having different gate lengths (the transistors T1 and T2 shown in FIGS. To form it, a low-viscosity resist 17 (so-called etch-back resist) is applied on the polycrystalline silicon 6 to make the whole flat (FIG. 10).

Further, as shown in FIG. 11, first, the resist 17 is etched using a highly selective anisotropic etching.

Thereafter, as shown in FIG. 12, the polycrystalline silicon 6a is etched to
a is completely buried between the silicon oxide films 15.

Further, as shown in FIGS. 13 (a) and 13 (b), a metal gate film 6b made of W (tungsten) is formed on the polysilicon 6a by performing a heat treatment in a tungsten hexafluoride WF ₆ atmosphere. Selective growth (so-called selective growth of W). Further, the silicon oxide films 15 on both sides of the polycrystalline silicon 6a are removed by NH ₄ F treatment. At this time, the silicon oxide film 1 is formed by NH ₄ F-based treatment for eliminating substrate damage previously performed.
5 is slightly recessed from the position immediately after the RIE shown in FIG. 9 and is blocked by the silicon nitride film 5. The NH ₄ F etching for removing the silicon oxide film 15 removes the portion under the polycrystalline silicon 6 a. The silicon oxide film 17 has N
There is no fear that the H ₄ F solution enters.

Thereafter, as shown in FIG.
P (phosphorus) is used at a dose of 4 × 10 ¹³ cm ⁻³ and an acceleration voltage of 40 to form the n ⁻ impurity layer 8 using
Ion implantation with Kev.

Thereafter, as shown in FIG. 15, a tungsten film 7 serving as a side wall is deposited on the entire surface of the substrate. This tungsten film 7 may be made of polycrystalline silicon containing phosphorus similarly to gate polycrystalline silicon layer 6b, or may contain other impurities.

Then, as shown in FIGS. 16A and 16B, sidewall conductive films 7 are formed on both sides of the gate 6 by highly selective anisotropic etching. As (arsenic) de To further form an n ⁺ impurity layer 9 -'s weight 5 × 10 ¹⁵ cm ^-3, implanting ions at an acceleration voltage 40 keV, Figure 5 (d)) the side wall portion by the ion implantation Increases the conductivity of the polycrystalline silicon.

Thereafter, an interlayer insulating film 11 made of silicon oxide is entirely deposited by a CVD method, and a heat treatment is performed at 850 ° C. for 60 minutes, and the interlayer insulating film 11 is contact holed by highly selective anisotropic etching. To form an electrode wiring 12 of an aluminum film (FIG. 17).

Finally, a contact on the gate 6 is formed, and the LDDMOS transistor as shown in FIGS. 3 and 4 is completed.

According to this embodiment, it is possible to greatly improve the initial characteristics, particularly the decrease in the threshold value (so-called short channel effect) which appears when the transistor is miniaturized.

This will be described with reference to FIGS. (Here, the case of the structure of Embodiment 1 using n-type silicon for the substrate and n ⁺ polycrystalline silicon for the gate will be described.) FIGS. 18 to 20 show transistors of the embodiment of the present invention, and FIGS. FIG. 23 is an explanatory diagram of a conventional transistor.

FIGS. 19 and 20 show potential diagrams of the transistor according to the embodiment of the present invention in the AA 'direction (in the vicinity of the source) and the BB' direction (silicon surface) in FIG. For comparison, the potential diagrams of the conventional transistor in the AA 'direction (near the source) and BB' direction (silicon surface) in FIG. 21 are shown in FIGS.
Shown in

In the transistor of the present invention, as shown in FIG. 18, the side wall portion of the gate n ⁺ polycrystalline silicon 6a is made of a metal (here, tungsten) having a work function difference smaller than that of the n ⁺ polycrystalline silicon with respect to the silicon substrate. FIG. 4 is a cross-sectional view of a transistor using a side wall conductive film 6b. The potential diagrams of this transistor in the AA 'direction (near the source) and BB' direction (silicon surface) are shown in FIG.
20. In this case, as can be seen from FIG. 19, since the bending of the band in the thermal equilibrium state is smaller than that of the conventional example, the potential near the source under the gate is hardly affected by the effect of the potential due to the drain bias. Therefore, even if the gate length is shortened, a transistor having good gate controllability and having a strong short channel effect can be realized.

The cause of the short channel effect is that when the gate length becomes short, the controllability of the gate with respect to the potential under the gate becomes poor, and the drop in the potential near the drain due to the application of the drain voltage is reduced. This is to affect the potential under the gate (especially near the source) and lower the potential. (FIG. 23 (c) partial reference p) the gain in the present invention to work around the problem - work function difference with respect to the silicon substrate on the side wall portion of the bets of n ⁺ polysilicon gate - bets n ⁺ polycrystalline silicon Using a material different from
It controls the potential near the source below.

FIG. 24 shows the results of measuring the gate length dependence of the threshold voltage Vth of the transistor of the present invention and the conventional transistor. As is apparent from FIG. 24, the transistor according to the embodiment of the present invention is a transistor having a strong short channel effect.

Further, according to the above embodiment, since the gate is formed including the side wall portion by using the conductive material for the side wall portion, the LDD low impurity layer can be completely overlapped under the gate.

Next, the reason why the gate-overlap structure transistor becomes a highly reliable transistor will be described.
FIG. 25 shows the drain voltage Vd = 6 and the gate voltage Vg = 30.
Simulation of electric field strength distribution in the channel direction when
Shows the results of the (a) is an example of a conventional LDD structure transistor (b). By completely overlapping the impurity diffusion layer under the gate, the vertical electric field is strengthened, and it is understood that the channel electric field which causes impact ionization and hot carrier generation is weakened.

Further, in this embodiment, a high dielectric film is provided between the side wall of the conductive material and the substrate.
It is different from the balapped LDD transistor. The effect will be described with reference to FIG. FIG. 26 is a simulation of the electric field intensity distribution in the channel direction near the drain when the relative dielectric constant (εr) of the insulating film between the side wall and the substrate is changed. That is, silicon oxide (εr =
When using 3.9), the conventional gate-overlap LDD
Silicon nitride (εr = 7.
This embodiment is the case where tantalum pentoxide or tantalum pentoxide (εr = 30) is used. According to the simulation results, the use of a high dielectric (silicon nitride, tantalum pentoxide) strengthens the vertical electric field in that part, reduces the channel electric field that causes hot carrier generation, and improves reliability. .

As described above, the conventional LDD transistor reduces the lateral electric field by providing a low concentration impurity layer, and the conventional gate-overlap LDD transistor further enhances the vertical electric field, Relieve the electric field,
In this embodiment, the lateral electric field is further reduced by providing a high dielectric material under the side wall. FIG. 27 shows the difference in reliability between the three transistors. The vertical axis indicates the amount of deterioration of gm, and the horizontal axis indicates the stress time. It can be seen that the transistor of this embodiment is the most reliable transistor among the above three.

The effect obtained by the transistor of this embodiment is not limited to the reliability but also appears in the initial characteristics. Gay
By completely overlapping the gate with the low-concentration pure layer and further providing a high-dielectric material under the side wall, the vertical electric field is strengthened and the dominance of the potential under the gate by the gate is increased. This effect is noticeable in the short channel effect. Second
FIG. 8 shows a diagram for explaining the short channel effect. Thus, it can be seen that this embodiment is a transistor which is strong against the short channel effect.

Further, by increasing the vertical electric field, the current flowing through the channel and the impurity diffusion layer flows from the bulk of the high resistance region to the substrate surface of the low resistance region. As a result, the driving ability becomes larger than before. This state is shown in FIG. In addition, since the present transistor has a silicide structure, it is faster than a conventional LDD transistor and a conventional overlap LDD transistor. In addition, since channel ion implantation is performed only in the channel portion, the junction capacitance of the diffusion layer is reduced, which indicates that the operation speed is high. FIG. 30 shows the power supply voltage dependency of the gate delay of the 71-stage ring oscillator. From this figure, it can be seen that the transistor of the embodiment of the present invention has a very high speed.

[0075]

As described above, by using a conductive material for the gate electrode side wall and using a high dielectric material between the side wall and the substrate, the gate overwrap effect can be enhanced.
A high-speed MOS transistor with high reliability, high driving capability, strong short-channel effect and high speed can be realized.

Further, according to the method of the present invention, it is possible to manufacture the semiconductor device without using an unstable process such as a conventional manufacturing process of a gate overlap LDD transistor, and to obtain extremely stable characteristics. it can.

[Brief description of the drawings]

FIG. 1 is a plan view showing a MOS transistor according to a first embodiment of the present invention.

FIG. 2 is a sectional view of the transistor taken along the line AA ′.

FIG. 3 is a plan view showing a MOS transistor according to a second embodiment of the present invention;

FIG. 4 is a sectional view of the transistor taken along the line AA ′.

FIG. 5 is a plan view showing a MOS transistor according to another embodiment of the present invention.

FIG. 6 is a plan view showing a MOS transistor according to another embodiment of the present invention.

FIG. 7 is a view showing a manufacturing process of a MOS transistor according to a second embodiment of the present invention;

FIG. 8 is a view showing a manufacturing process of the MOS transistor according to the second embodiment of the present invention;

FIG. 9 is a view showing a manufacturing process of the MOS transistor according to the second embodiment of the present invention;

FIG. 10 is a view showing a manufacturing process of the MOS transistor according to the second embodiment of the present invention;

FIG. 11 is a view showing a manufacturing process of the MOS transistor according to the second embodiment of the present invention;

FIG. 12 is a view showing a manufacturing process of the MOS transistor according to the second embodiment of the present invention;

FIG. 13 is a view showing a manufacturing process of the MOS transistor according to the second embodiment of the present invention;

FIG. 14 is a view showing a manufacturing process of the MOS transistor according to the second embodiment of the present invention;

FIG. 15 is a diagram showing a manufacturing process of the MOS transistor according to the second embodiment of the present invention;

FIG. 16 is a view showing a manufacturing process of the MOS transistor according to the second embodiment of the present invention;

FIG. 17 is a view showing a manufacturing process of the MOS transistor according to the second embodiment of the present invention;

FIG. 18 is a cross-sectional view illustrating the operation of a transistor of an example of the present invention.

FIG. 19 is a potential diagram of the transistor in the AA ′ direction (near the source).

FIG. 20 is a potential diagram of the transistor in the BB ′ direction (silicon surface).

FIG. 21 is a cross-sectional view illustrating the operation of a conventional transistor.

FIG. 22 is a potential diagram of the transistor in the AA ′ direction (near the source).

FIG. 23 is a potential diagram of the transistor in the BB ′ direction (silicon surface).

FIG. 24 is a graph showing the results of measuring the gate length dependence of the threshold voltage Vth of the transistor of the present invention and a conventional transistor.

FIG. 25 is a simulation result showing a channel direction electric field distribution near the drain of the conventional LDD transistor and the transistor of the embodiment of the present invention.

FIG. 26 is a simulation result showing the electric field intensity distribution in the channel direction near the drain of the conventional gate overlap LDD transistor and the transistor of the embodiment of the present invention.

FIG. 27 is a graph showing the stress time dependence of the amount of degradation of gm for comparing the reliability of the transistor of the conventional example and the transistor of the example of the present invention.

FIG. 28 is a diagram for comparing the short-channel effect of the transistor of the conventional example and the transistor of the example of the present invention;

FIG. 29 is a diagram for comparing the driving capabilities of a conventional transistor and a transistor of the present invention.

FIG. 30 is a diagram showing high-speed characteristics of a transistor according to an example of the present invention.

FIG. 31 is a view showing a manufacturing process of a conventional gate overlap transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Si board | substrate 2 ... Isolation insulating film 3 ... Transistor channel region 4 ... Gate insulating film 5 ... High dielectric constant film 6 ... Gate electrode 6a ... Polycrystalline silicon 6b ... High melting point low resistance metal 7 ... Side wall Conductive film 8 Low-concentration impurity diffusion layer 9 High-concentration impurity diffusion layer 10 Element region 11 Insulating film 12 Electrode wiring 13 Electrode wiring 15 Silicon oxide film 16 Resist 17 Gate insulating film 18 Resist Reference Signs List 20 P-type semiconductor substrate 21 Gate oxide film 22, 24 Polycrystalline silicon 23 Natural oxide film 27 High-concentration n-type impurity diffusion layer 28 Low-concentration n-type impurity diffusion layer 29 Silicon oxide

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-126679 (JP, A) JP-A-58-141575 (JP, A) JP-A-3-6830 (JP, A) JP-A-4- 181738 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/78 H01L 21/336

Claims (4)

(57) [Claims] A gate electrode formed on a surface of a substrate of one conductivity type via a gate insulating film; a first impurity diffusion layer; and a second impurity diffusion layer having a lower concentration than the first impurity diffusion layer. A MOS transistor comprising: a source / drain region of a second conductivity type formed on the surface of the substrate; and a side wall film made of a conductor directly in contact with a side wall of the gate electrode. The second impurity diffusion layer is formed to extend at least below the side wall film, and has a higher dielectric constant between the side wall film and the substrate than a gate insulating film below a gate electrode, and has one A semiconductor device having an insulating film in contact with a flat surface. 2. A gate electrode formed on a surface of a substrate of one conductivity type via a gate insulating film; a first impurity diffusion layer; and a second impurity diffusion layer having a lower concentration than the first impurity diffusion layer. A MOS transistor comprising: a source / drain region of a second conductivity type formed on the surface of the substrate; and a side wall film made of a conductor on a side wall of the gate electrode; An impurity diffusion layer is formed to extend at least below the sidewall film, and an insulating film between the sidewall film and the substrate having a higher dielectric constant than a gate insulating film below a gate electrode and protruding below the gate electrode. A semiconductor device characterized in that a semiconductor device is provided. 3. The side wall film is made of a material having a work function difference between the side wall film and the substrate smaller than a work function difference between the gate electrode and the substrate. 3. The semiconductor device according to claim 1. A step of forming a gate insulating film on the surface of the silicon substrate; a step of forming an insulating film having a higher relative dielectric constant than the gate insulating film on the gate insulating film; Depositing a silicon film; forming a resist pattern on the upper layer so as to cover a region other than the gate electrode formation region; using the resist pattern as a mask, the silicon oxide film in the gate electrode formation region, the insulating film, and Patterning the gate insulating film; depositing a gate electrode material on the entire surface; applying a resist having a low viscosity coefficient over the entire surface to planarize the surface; and oxidizing the resist and the electrode material. Embedding in a concave portion of the silicon film, growing a metal film on the silicon oxide film, and removing the silicon oxide film Forming a region having a first impurity concentration by performing ion implantation using the gate electrode as a mask, further depositing a conductive material on the entire surface, and then performing anisotropic etching on both sides of the electrode material. Forming a side wall conductive film while leaving the side wall; and performing ion implantation using the side wall conductive film and the gate electrode as a mask to form a source / source having a second impurity concentration higher than the first impurity concentration. Forming a drain region.