JPH05183153A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a high reliability semiconductor device which is unlikely to be varied in its characteristics by adjusting the energy state of electric charges located below a gate insulating film and having an opposite polarity to that of a chief conductive carrier such that the energy state of the electric charges located far away from the gate insulating film is lower than that of the electric charges located near the gate insulating film. CONSTITUTION:A semiconductor region excepting a source region 12 and a drain region 13 of a device portion on a substrate 11 is constructed into a double-layered structure, and an upper layer portion therebetween located below a gate oxide film 14 is formed slightly deeper than a channel depth. Further, a lower layer portion therebetween located just below a single crystal silicon channel formation layer 16 is formed as a constant energy layer 17 which is lower than the channel formation layer 16 with respect to positive hole energy. Electrons travel from the n type source region 12 through an n type channel located in the p type channel formation layer 16, and cause collision ionization in the vicinity of the n type drain region 13. Hereby, positive holes are moved to the constant energy layer 17 with lower energy than the p type channel formation layer 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which constitutes an insulated gate transistor.

[0002]

2. Description of the Related Art Conventionally, an insulated gate transistor has been widely used as an element constituting a large scale integrated circuit (hereinafter referred to as an LSI). Insulated gate type means metallic (polycrystalline silicon (Si) made of metal or close to metal.
Is a general term for a type in which a semiconductor surface is controlled via an insulator by applying a voltage to an electrode of (Metal).
nsulator Semiconductor). Among them, the one using an oxide film as an insulator is a metal oxide semiconductor (MOS).
MNS (Metal Ni)
tride Semiconductor), M using an alumina coating
It corresponds to AS (Metal Alumina Semiconductor).

FIG. 15 shows, by way of example, an electron conduction type (hereinafter, n
It is called a channel. ) This shows the structure of a MOSFET.

In this figure, reference numeral 601 denotes a p-type silicon substrate, and n ⁺ source regions 602 and n ⁺ are formed on the surface of the substrate 601 with a space for forming channel formation regions from each other.
^{A +} drain region 603 is formed, a gate oxide film 604 as the insulator is formed on the channel formation region, and a gate electrode 605 as the metallic electrode is formed on the gate oxide film 604. ..

In such a structure, the gate electrode 60
When a + voltage is applied to 5, an electron is attracted to the surface side in the region under the gate oxide film 604 in the substrate 601, an n-type channel that serves as a carrier is formed, and a current passes through this channel. It becomes possible to flow from the source region 602 toward the drain region 603.

Further, such MISFET such as MOS
In recent years, SOI (Semiconductor on Insul)
ator) structure is often used. This SOI MOSFET
Is a technology in which a new element is formed on the insulating film, which is an indispensable technology for realizing high-density and high-performance elements such as three-dimensional integrated circuits. This is one of the important technologies that enables complete isolation of individual devices even in an integrated circuit having the same configuration as that of.

FIG. 16 shows the structure of an n-channel MOSFET having an SOI structure as an example.

In this figure, reference numeral 701 designates a p-type silicon substrate, and an interlayer isolation oxide film layer 702 for electrically insulating and isolating the upper and lower layers thereof to provide the SOI structure is formed on the substrate 701. The oxide film layer 70 is
It is formed on 2. Reference numeral 703 is its n + type source region, 704 is an n + type drain region, 705 is a gate oxide film, and 706 is a gate electrode. A semiconductor region other than the source region 703 and the drain region 704 on the oxide film 702 is a channel formation layer 707 that forms a channel between the both regions 703 and 704.

The basic operation is the same as that shown in FIG. 15, but since there is an oxide film 702, this oxide film 702 is present.
Even if the impurity concentration of the upper silicon layer (that is, the channel formation layer 707) is reduced, a depletion layer extends from the source region 703 and the drain region 704 and the source and the drain are electrically connected ( Punch-through phenomenon)
Is suppressed. Therefore, the impurity concentration of the channel formation layer 707 can be reduced, so that the impurity scattering in the channel formation layer 707 is reduced and the vertical electric field peculiar to the MIS transistor is also reduced, so that the current value flowing from the source region 703 to the drain region 704 is reduced. Will increase. Also,
Since there is the oxide film 702, the upper layer element portion and the base substrate 701 are
There is little parasitic capacitance with. Furthermore, since it is insulated from the base substrate 701 by the oxide film 702, the base substrate 7
The electric charge generated by the radiation in 01 does not affect the operation as the nMIS transistor.

[0010]

However, in the MIS transistor and the SOI type MIS transistor described above, the main conduction carriers are high in energy because of the high electric field generated at the junction between the drain region and the channel region. There is a problem that the charge having the opposite polarity to the main conduction carrier, which is generated due to the acceleration and collisional ionization, has a bad influence on the characteristics of the transistor.

For example, in the case of the n-channel transistor, holes are generated in the vicinity of the drain region by impact ionization, but these holes are easily injected into the gate insulating film and the quality of the gate insulating film is improved. This causes the transistor characteristics to deteriorate and the transistor characteristics to fluctuate. Further, in the hole conduction type pMIS transistor and the SOI type pMIS transistor, the electrons generated by the impact ionization have the same adverse effect on the characteristics.

Even when the gate voltage is applied until the inversion layer is formed in the channel forming layer, an electrically neutral region exists in the channel forming layer.

FIG. 17 shows the situation in the SOI type nMIS transistor.

In this figure, reference numeral 801 designates an upper and lower interlayer insulating isolation oxide film formed on a p-type base substrate (not shown).
2 is an n + type source region, 803 is an n + type drain region,
Reference numeral 804 is a gate oxide film, 805 is a gate electrode, and 806 is a channel forming layer. The solid line in the cross section of the element is an equipotential line formed by connecting equipotential portions, and the numbers therein represent the potential. ing.

As shown in the figure, even if it is an SOI type, if the channel forming layer 806 is thick, the depletion layer is the channel forming layer 806 even if the gate voltage is applied up to the inversion layer forming level.
The lower oxide film 801 is not reached, and the channel formation layer 806
An electrically neutral region (hatched portion) remains inside. Therefore, holes generated by the impact ionization flow below the channel having a low potential, whereby holes are accumulated in the neutral region generated in the channel formation layer 806 and the potential of the channel formation layer 806 is increased.

For example, the thickness TSOI of the channel forming layer = 2
500 Å, same impurity concentration CSOI = 10 ¹⁷
At cm ^-3 and VD = VG = 1.5V, the hole concentration in the shaded area shown in FIG. 17 is as high as 10 ¹⁴ cm ^-3 by a few orders of magnitude higher than the surrounding area. As a result, an effect similar to that of applying a positive voltage to the base substrate is produced, and the current − shown in FIG.
As in the voltage characteristic, a kink occurs at the drain voltage at which holes start to accumulate, and a flat saturation region cannot be formed when the drain voltage is further increased, so that stable circuit operation cannot be guaranteed.

The present invention has been made in view of the above problems of the prior art, and an object of the present invention is to generate electric charges (holes (n-channel) or electrons) having a polarity opposite to that of carriers generated by impact ionization. It is an object of the present invention to provide a semiconductor device forming a MIS transistor, which prevents (p channel)) from penetrating into the gate oxide film and accumulates in the channel forming layer, and thus the characteristics are less likely to change and the reliability is high.

[0018]

According to another aspect of the present invention, there is provided a semiconductor device, which constitutes an insulated gate type transistor, is disposed under a gate insulating film, and has a gate insulating property with respect to charges having a polarity opposite to that of a main conduction carrier. It is characterized in that it is provided with an energy state adjusting layer whose energy state is adjusted so that the side farther from the film is lower than the side closer to the side.

In particular, the energy state adjusting layer in the semiconductor device according to the second aspect is provided with a constant energy layer having a constant energy over the entire region.

Further, the energy state adjusting layer in the semiconductor device according to claim 3 is characterized in that it has a transition layer in which the energy decreases from the gate insulating film side toward the semiconductor substrate side.

Further, the energy state adjusting layer in the semiconductor device according to the fourth aspect is characterized by including a transition layer in which the energy decreases from the drain region side toward the source region side.

In addition to the structure according to any one of claims 1 to 4, the semiconductor device according to claim 5 has an interlayer separation for electrically insulating and separating the semiconductor substrate and the energy state adjusting layer between them. It is characterized by having an insulating layer.

[0023]

In the MIS transistor according to the present invention, the energy on the substrate side of the channel forming layer is lower than that on the surface portion of the charge, which is the opposite polarity to the main conduction carriers. Therefore, in the vicinity of the drain region, the charges generated by the impact ionization move to the substrate side faster than in the MIS transistor according to the related art.

As a result, it is difficult to inject high-energy charges into the gate insulating film, and deterioration of the quality of the gate insulating film is suppressed.

Further, since the charges are less likely to be accumulated under the channel formation region, stable current-voltage characteristics can be obtained up to a high drain voltage.

Furthermore, if a transition layer whose energy decreases from the gate insulating film side toward the semiconductor substrate side is provided, the charges generated by impact ionization can be promptly flown to the lower part.

Furthermore, if the energy decreases from the drain region side toward the source region side, the charges generated by the impact ionization will be promptly discharged through the source electrode.

Particularly in the SOI type MIS transistor, since the impurity concentration of the channel forming layer on the isolation oxide film can be made lower than that of the MIS transistor of the normal structure having no SOI structure, the carrier concentration is originally low and it is generated by collision ionization. Electrons or holes easily diffuse in the direction away from the gate insulating film. Therefore, higher reliability can be realized as compared with the MIS transistor having the normal structure.

[0029]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the structure of an n-channel MOSFET according to the first embodiment of the semiconductor device of the present invention, which has a constant energy layer.

In this figure, 11 is a p-type silicon substrate, and an n-channel element portion is formed in a region on the front surface side of this substrate 11. That is, n is provided in the region near the surface of the substrate 11 with a space corresponding to the channel length.
^{The +} type source region 12 and the n ⁺ type drain region 13 are formed and are on the one main surface of the substrate 11 and the source region 1.
A gate oxide film 14 is formed between the gate oxide film 14 and the drain region 13, and a gate electrode 15 is formed on the gate oxide film 14.

The source region 1 of the element portion on the substrate 11
The semiconductor region except 2 and the drain region 13 has a two-layer structure, and the upper layer portion thereof located directly below the gate oxide film 14 is formed slightly deeper than the formed channel depth and is formed of single crystal silicon. The lower layer portion immediately below the channel forming layer 16 is made of a SiGe alloy synthesized with the same composition ratio of 75% Si and 25% Si in the lower layer portion immediately below the channel forming layer 16. The energy of holes is lower than that of the channel formation layer 16 and is formed as a constant energy layer 17 in a constant energy state over the entire region.

Next, the behavior of the electron, which is the main conduction carrier, will be specifically described. The electrons from the n-type source region 12 to n
Toward the drain region 13, the p-type channel forming layer 1
It travels in the n-type channel in 6 and causes collision ionization in the vicinity of the n-type drain region 13. The holes generated by this move to the constant energy layer 17 having lower energy than the p-type channel formation layer 16.

As a result, holes are less likely to enter the gate oxide film 14 and variations in transistor characteristics are suppressed.
Therefore, higher reliability can be obtained than in the conventional technique.

Further, since the holes can be separated from the channel in the channel forming layer 16, it is possible to prevent the holes from accumulating in the vicinity of the channel, and from this point also, the fluctuation of the transistor characteristics is suppressed, It is possible to realize higher reliability than the conventional technology.

Further, in the present embodiment, the channel forming layer 16 containing no germanium is formed in the uppermost layer of the element layer, but this has the effect of reducing the occurrence of interface states at the interface with the gate oxide film 14 as much as possible. The effect of keeping the forbidden band width of this portion where the channel current flows large is to prevent the collision ionization rate from increasing.

FIG. 2 shows the structure of an n-channel MOS transistor according to the second embodiment of the present invention. In addition to the constant energy layer, a semiconductor is formed between the channel forming layer and the constant energy layer from the gate oxide film side. The structure is provided with a transition layer whose energy decreases toward the substrate side, that is, in the depth direction of the substrate.

In this figure, reference numeral 21 is a p-type silicon substrate, and the element portion is formed on this substrate 21,
22 is an n ⁺ type source region, 23 is an n ⁺ type drain region,
Reference numeral 24 is a gate oxide film, and 25 is a gate electrode.

The source region 2 of the element portion on the substrate 21
The semiconductor region other than 2 and the drain region 23 has a three-layer structure, of which the upper layer portion located directly under the gate oxide film 24 is formed slightly deeper than the formed channel depth and is formed of single crystal silicon. The channel forming layer 26 is formed. The intermediate layer located immediately below the channel forming layer 26 is made of a SiGe alloy, and the composition ratio (Si: Ge) of silicon and germanium is 100.
%: 0% to 75%: 25% linearly changes in the depth direction of the substrate 21, thereby forming the transition layer 27 in which the energy for holes gradually and continuously decreases in the depth direction of the substrate 21. ing. In the lowermost layer portion immediately below the transition layer 27, silicon and germanium are spread over the entire area and S
Si synthesized with the same composition ratio of i = 75% and Ge = 25%
It is formed as a constant energy layer 28 made of a Ge alloy.

The FET of this embodiment having such a structure
According to the description, in the transition layer 27, the channel forming layer 2
The energy for holes is continuously reduced from 6 toward the constant energy layer 28, which causes a pseudo electric field for accelerating holes to a deeper portion of the substrate 21. Holes are separated from the gate oxide film 24 at a higher speed than in the above embodiment. Therefore, higher reliability can be realized than in the first embodiment.

FIG. 3 shows the structure of an n-channel MOSFET according to the third embodiment of the present invention, which corresponds to the structure shown in FIG. 2 from which the channel forming layer is removed, and it corresponds to the constant energy layer and the depth direction. A transition layer is provided, and this transition layer also serves as a channel formation layer.

In this figure, 31 is a p-type silicon substrate, and the element portion is such that 32 is an n ⁺ type source region of the element portion formed on this substrate 31, 33 is an n ⁺ type drain region, and 34 is A gate oxide film, 35 is a gate electrode.

Source region 3 in the element portion on the substrate 31
The semiconductor region other than 2 and the drain region 33 has a two-layer structure, of which the upper layer portion located immediately below the gate oxide film 34 is formed sufficiently deeper than the formed channel depth and is made of a SiGe alloy. The composition ratio (Si: Ge) of silicon and germanium is 100%: 0.
% To 75%: 25%, which linearly changes in the depth direction of the substrate 31, whereby the energy for holes is formed as a transition layer 36 in which the energy gradually decreases continuously in the depth direction of the substrate 31. In the lowermost layer portion immediately below the transition layer 36, silicon and germanium are spread over the entire area, and Si is 75
%, Ge is formed as the constant energy layer 37 made of a SiGe alloy synthesized with the same composition ratio of 25%.

The FET of this embodiment having such a structure
According to this, since a similar electric field as described above is generated just below the gate oxide film 34, holes are separated from the gate oxide film 34 and the channel formation region at a higher speed than in the second embodiment shown in FIG. , And is discharged from the source region 32.

FIG. 4 shows the structure of an SOI n-channel MOSFET according to the fourth embodiment of the present invention, which is a combination of the SOI structure and the structure of the first embodiment shown in FIG. Equivalent to.

In this figure, reference numeral 41 is a p-type silicon substrate, and an interlayer isolation oxide film 42 which electrically insulates and separates the substrate 41 and an element layer above it from the substrate 41 and provides an SOI structure. Has been formed. 43 is this substrate 4
1 is an n ⁺ type source region of the element portion formed above 1, 44 is also an n ⁺ type drain region, 45 is a gate oxide film, and 46 is a gate electrode.

Source region 4 in the element portion on the substrate 41
3 and the semiconductor region except the drain region 44 have a two-layer structure, of which the upper layer portion located directly below the gate oxide film 45 is formed to be slightly deeper than the formed channel depth and is made of single-crystal silicon. Formation layer 47
And silicon and germanium are present in the lower layer portion located immediately below the channel forming layer 47,
S synthesized with the same composition ratio of 75% Si and 25% Ge
It is formed as a constant energy layer 48 made of an iGe alloy.

According to the present embodiment, the impurity concentration of the channel forming layer 47 on the isolation oxide film 42 can be made lower than that of the MIS transistor of the normal structure having no SOI structure.
The holes generated by the impact ionization are likely to diffuse in the direction away from the channel formation region side, and higher reliability than that of the MIS transistor having the normal structure can be realized.

FIG. 5 shows the structure of an SOI n-channel MOSFET according to the fifth embodiment of the present invention, which is a combination of the SOI structure and the structure of the second embodiment shown in FIG. Equivalent to.

In this figure, 51 is a p-type silicon substrate, an interlayer isolation oxide film 52 is formed on this substrate 51, and 53 is n ^{+ of} the element portion formed on this oxide film 52. A type source region, 54 is an n ⁺ type drain region, 55 is a gate oxide film, and 56 is a gate electrode.

The semiconductor region except the source region 53 and the drain region 54 in the element portion on the oxide film 52 has a three-layer structure, of which the uppermost layer portion immediately below the gate oxide film 55 is the channel to be formed. The channel forming layer 57 is formed to be slightly deeper than the depth and is made of single crystal silicon. The intermediate layer located immediately below the channel forming layer 57 is made of SiGe alloy, and the composition ratio of silicon and germanium (Si: Ge) is 100%: 0
% To 75%: 25%, which linearly changes in the depth direction of the substrate 51, whereby the energy for holes is formed as a transition layer 57 in which the energy gradually decreases continuously in the depth direction of the substrate 51. In the lower layer portion immediately below the transition layer 57, silicon and germanium are spread over the entire area, and Si is 75
%, Ge is formed as the constant energy layer 58 made of a SiGe alloy synthesized with the same composition ratio of 25%.

According to the present embodiment, due to the presence of the transition layer 57, the holes generated by impact ionization are more likely to leave the channel formation region than in the fourth embodiment shown in FIG.

FIG. 6 shows the structure of an SOI n-channel MOSFET according to the sixth embodiment of the present invention, which has an SOI structure and the structure of the third embodiment shown in FIG. Equivalent to.

In this figure, 61 is a p-type silicon substrate, 62 is an interlayer isolation oxide film on this substrate 61, 63 is an n ⁺ type source region of the element portion formed on this oxide film 62, and 64 is the same. An n ⁺ type drain region, 65 is a gate oxide film, and 66 is a gate electrode.

The semiconductor region except the source region 63 and the drain region 64 in the element portion on the oxide film 62 has a two-layer structure, of which the upper layer portion immediately below the gate oxide film 65 has a channel depth to be formed. And is made of SiGe alloy and has a composition ratio of silicon and germanium (Si: Ge) of 100.
%: 0% to 75%: 25% linearly changes in the depth direction of the substrate 61, whereby the energy for holes is formed as a transition layer 67 in which the energy gradually decreases continuously in the depth direction of the substrate 61. ing. The lower layer immediately below the transition layer 67 is
SiGe synthesized with the same composition ratio of 75% Si and 25% Ge over the entire area of silicon and germanium.
It is formed as a constant energy layer 68 made of an alloy.

Therefore, according to the present embodiment, the holes generated by the impact ionization are more likely to leave the channel formation region than in the fifth embodiment shown in FIG.

FIG. 7 shows the structure of an n-channel MOSFET according to the seventh embodiment of the present invention, which is obtained by removing the constant energy layer from the FET of the second embodiment shown in FIG. The structure has only a transition layer in the depth direction.

In this figure, 71 is a p-type silicon substrate, 72 is an n ⁺ type source region of an element portion formed on the substrate 71, 73 is also an n ⁺ type drain region, 74 is a gate oxide film, and 75 is It is a gate electrode.

The source region 7 in the element portion on the substrate 71
The semiconductor region except 2 and the drain region 73 has a three-layer structure including the base layer used as the substrate 71, of which the upper layer portion located immediately below the gate oxide film 74 is slightly smaller than the formed channel depth. The channel forming layer 76 is formed deeply and is made of single crystal silicon, and the lower layer portion thereof is made of SiGe alloy, and the composition ratio (Si: Ge) of silicon and germanium is 100%: 0%.
To 75%: 25%, it is formed as a transition layer 77 that linearly changes in the depth direction of the substrate 71 and the energy for holes gradually and continuously decreases in the depth direction of the substrate 61.

Also in this embodiment, due to the presence of the transition layer 77 immediately below the channel, the holes can be easily separated from the channel forming region, and the holes are less likely to be accumulated in the SiGe layer, so that the parasitic bipolar effect is suppressed. can do.

FIG. 8 shows the structure of an n-channel MOSFET according to the eighth embodiment of the present invention. Here, the constant energy layer is removed from the FET of the third embodiment shown in FIG. The structure is shown as having.

In this figure, 81 is a p-type silicon substrate, 82 is an n ⁺ type source region of the element portion formed on the substrate 81, 83 is also an n ⁺ type drain region, 84 is a gate oxide film, and 85 is It is a gate electrode.

The source region 8 in the element portion on the substrate 81
The semiconductor region except 2 and the drain region 83 has a two-layer structure including the base layer made of the substrate 81, and the upper layer portion located immediately below the gate oxide film 84 is formed deeper than the formed channel depth. In addition, it is made of SiGe alloy, and its composition ratio of silicon and germanium (Si:
Ge) from 100%: 0% to 75%: 25% substrate 8
Transition layer 8 that linearly changes in the depth direction of 1 to gradually reduce the energy for holes gradually and continuously in the depth direction of the substrate 81.
It is formed as 6.

Therefore, according to the present embodiment, further effects can be expected as compared with the seventh embodiment shown in FIG.

FIG. 9 shows the structure of an SOI n-channel MOSFET according to the ninth embodiment of the present invention. The structure shown in this figure corresponds to a combination of the SOI structure and the structure shown in FIG. To do.

In this figure, 91 is a p-type silicon substrate, 92 is an interlayer isolation oxide film formed on this substrate 91, and 93 is an n ^{+ of} the element portion formed on this oxide film 92.
Type source region, 94 is also an n ⁺ type drain region, 95
Is a gate oxide film, and 96 is a gate electrode.

The semiconductor region in the element portion on the oxide film 92 except the source region 93 and the drain region 94 has a two-layer structure, of which the upper layer portion immediately below the gate oxide film 95 has a channel depth to be formed. The channel forming layer 97 is formed to be deeper than that and is made of single crystal silicon, and the lower layer of the channel forming layer 97 is made of a SiGe alloy, and the composition ratio of the silicon and germanium (Si : Ge) is 100%: 0%
To 75%: 25%, it is formed as a transition layer 98 that linearly changes in the depth direction of the substrate 91.

Therefore, according to the present embodiment, since it has the SOI structure, a further effect can be expected as compared with the seventh embodiment shown in FIG. 7, and the SOI floating effect can be suppressed.

FIG. 10 shows an SO according to the tenth embodiment of the present invention.
This shows the structure of an I-type n-channel MOSFET, and here, a structure having a combination of the SOI structure and the structure shown in FIG. 8 is shown.

In this figure, 101 is a p-type silicon substrate, 102 is an interlayer isolation oxide film formed on this substrate 101, 103 is an n ⁺ type source region of an element portion formed on this oxide film 102, and 104. Is an n ⁺ type drain region, 105 is a gate oxide film, and 106 is a gate electrode.

The semiconductor region except the source region 103 and the drain region 104 in the element portion on the oxide film 102 is entirely formed as a transition layer 107 which also serves as a channel forming layer. This transition layer 107 is also made of SiG, as described above.
It is composed of an e-alloy, and its composition ratio of silicon and germanium (Si: Ge) is 100%: 0% to 75%: 25%.
The substrate 101 is formed so as to change linearly in the depth direction.

Therefore, according to the present embodiment, it is possible to expect more effects than the ninth embodiment shown in FIG.

FIG. 11 shows an SO according to the eleventh embodiment of the present invention.
1 shows the structure of an I-type n-channel MOSFET, which is characterized in that in addition to the depth direction of the substrate, the direction from the drain region to the source region (hereinafter , For convenience, is abbreviated as a horizontal direction.).

In this figure, 201 is a p-type silicon substrate, on which an interlayer isolation oxide film 202 for providing an SOI structure is formed, and an element isolation oxide film 203 is provided so as to surround an element formation region. Are formed.

Reference numeral 204 denotes an n ⁺ type source region of the element portion, 20
5 is an n ⁺ type drain region, 206 is a gate oxide film, 20
Reference numeral 7 is a gate electrode, 208 is an interlayer isolation oxide film for electrically insulating and separating the element layer and the wiring layer, 209 is a source electrode, 2
Reference numeral 10 is a drain electrode.

The semiconductor region except the source region 204 and the drain region 205 of the element portion on the oxide film 202 is 3
It has a layered structure, of which an upper layer portion located immediately below the gate oxide film 206 is formed of a single crystal silicon and is formed as a channel formation layer 211 having a depth enough to cover a channel. This channel forming layer 21
The lower layer of No. 1 is made of SiGe alloy, and the composition ratio of silicon and germanium (Si: Ge) is 100%:
It is formed as a transition layer 212 that linearly increases in the depth direction and the lateral direction from 0% to 75%: 25%. For example, the composition ratio (Si: Ge) of the portion along the line AA ′ in FIG. 11 corresponding to the depth direction changes from 100%: 0% to 80%: 20%, and corresponds to the lateral direction. The composition ratio (Si: Ge) of the portion along the line BB ′ in 11 is 9
It varies from 5%: 5% to 85%: 15%. Therefore,
In this transition layer 212, the closer to the oxide film 202 and the closer to the source region 204, the lower the energy state for holes becomes. The lower layer of the transition layer 212 is a base layer 213 and is made of the same single crystal silicon as the substrate 201.

According to this embodiment, in the transition layer 212, the closer to the oxide film 202 is, the more the source region 20 is formed.
4, the energy state for holes becomes lower, so that excess holes generated by collision ionization of electrons, which is the main current component of the SOI n-channel MOSFET, near the drain rapidly increase the proportion of germanium. On the other hand, that is, since it plays a role of guiding to the source region 204 side in the deep direction on the side opposite to the gate oxide film 206 side in the element region, excess holes can be more rapidly generated than only the transition in the depth direction. Then, it can be extracted from the source electrode.

Further, in this embodiment, the channel forming layer 211 containing no germanium is formed in the uppermost layer of the SOI device layer, but this has the effect of reducing the occurrence of interface states at the interface with the gate oxide film 206 as much as possible. Then, the forbidden band width of this portion where the channel current flows is kept large, and there is an effect that the collision ionization rate is prevented from increasing.

Here, the MOS described so far is used.
The manufacturing method of the embodiment shown in each of FIGS. 1, 4, and 11 among the FETs will be described below with reference to the drawings.

FIG. 12 illustrates the manufacturing process for obtaining the FET structure of the first embodiment shown in FIG.

First, SiG is formed on the p-type silicon substrate 301.
The e-alloy film 302 and the single crystal silicon film 303 are formed in this order by UHV / CVD (Ultra High Vacuum / Chemical V).
apor Deposition) or MBE (Molecular Beam Epitax)
y) is used (FIG. 12A). Here, in forming the SiGe alloy film 302, by controlling the supply of those material gases, the composition ratio of silicon and germanium (Si: Ge = 75%: 25%) is maintained constant over the entire area. It is possible to change the depth direction or the lateral direction.

Next, the single crystal silicon film 303 is thermally oxidized to form an oxide film 304, and the polycrystalline silicon film 305 is formed on the oxide film 304 by the above UHV / CVD or MB.
It is deposited by the E method (FIG. 12B).

Then, the oxide film 3 is formed by the lithography technique.
04 and the polycrystalline silicon film 305 are patterned to form a gate oxide film 306 and a gate electrode 307 (FIG. 12C).

Then, from the single crystal silicon film 303 side, S
By implanting arsenic ions to a depth reaching the iGe alloy film 302, the n ⁺ -type source region 308 is formed.
And n ⁺ type drain region 309 are formed at the same time as SiG
The e-alloy film 310 is formed as the low energy layer 310, and the single crystal silicon film 303 is formed as the channel forming layer 311 (FIG. 12D).

According to the above manufacturing steps, the MOSFET structure of the first embodiment shown in FIG. 1 can be obtained. PECVD
Alternatively, in MBE, if the composition ratio of germanium is continuously changed, the second (FIG. 2), the third (FIG. 3), the seventh
(FIG. 7) and the structure of the eighth (FIG. 8) embodiment can be obtained by the same manufacturing process.

Next, a manufacturing process for obtaining the SOI type n-channel MOSFET structure of the fourth embodiment of FIG. 4 will be described with reference to FIG.

First, LPCVD is performed on the silicon substrate 401.
After forming the oxide film 402 by (Low Pressure Chemical Vapor Deposition), the SiGe alloy film 403 and the single crystal silicon film 404 are subjected to UHV / CVD or MBE.
Are formed (FIG. 13A).

Then, an oxide film 405 is formed by PECVD.
Then, an n ⁺ type polycrystalline silicon film 406 is formed (FIG. 13B).

Then, the oxide film 4 is formed by the lithography technique.
05 and the polycrystalline silicon film 406 are patterned to form a gate oxide film 407 and a gate electrode 408 (FIG. 13C).

Then, from the single crystal silicon film 404 side, S
By implanting arsenic ions to a depth reaching the iGe alloy film 403, the n ⁺ -type source region 409 is formed.
And the n ⁺ drain region 410 are formed at the same time, the SiGe alloy film 403 and the single crystal silicon film 404 between the regions 409 and 410 are formed as the low energy layer 411 and the channel formation layer 412, respectively (FIG. 13).
(D)).

According to the above manufacturing process, the FET structure of the fourth embodiment of FIG. 4 can be obtained. In PECVD or MBE, if the composition ratio of germanium is continuously changed, the fifth (FIG. 5), sixth (FIG. 6), ninth (FIG. 9), and tenth (FIG. 10) examples can be obtained. The structure of can be obtained by the same manufacturing process.

FIG. 14 illustrates the manufacturing process of the SOI type n-channel MOSFET shown in FIG.

First, a silicon oxide film 502 having a thickness of about 1 μm is formed on the entire surface of a semiconductor substrate 501 by a sputtering method or a CVD method, and then a polycrystalline silicon film having a thickness of, for example, 6000 angstrom is formed on the silicon oxide film 502. Form with thickness. Then, the polycrystalline silicon film is single-crystallized using an electron beam annealing method or an annealing method using a heater, and is oxidized in an oxidizing atmosphere to remove the oxide film with a solution such as ammonium fluoride.
Alternatively, a single crystal silicon film 503 having a film thickness of about 1000 angstroms is formed by an etch-back method such as RIE using dry etching (FIG. 14A).

Then, a silicon-germanium alloy film 504 having a film thickness of about 1000 angstrom is formed on the single crystal silicon film 503 by high vacuum CVD method or molecular beam epitaxial method. At this time, the supply of the raw material gas is controlled so that the proportion of germanium gradually decreases from the lower layer to the upper layer due to the composition change described above. After that, the portion on the drain side is masked with a resist or the like, and 100 K is formed by, for example, a 45 ° oblique ion implantation method.
After the Ge ions are implanted by ev to remove the resist, the Ge content can be laterally distributed by annealing at, for example, 600 ° C. for 24 hours. further,
Continuous single-crystal silicon film 50 containing no germanium
5 is formed on the SiGe alloy film 504 with a thickness of, for example, about 100 angstrom (FIG. 14B). Here, it is desirable that the single crystal silicon film 505 be doped with p-type impurities at a low concentration of 10 ¹⁶ cm ⁻³ or less.

After that, an oxide film, for example, 200 is formed on the single crystal silicon film 505 by using a thermal oxidation method or a CVD method.
Angstrom is formed and LPC is formed on this oxide film.
A polycrystalline silicon film to be a gate electrode is formed, for example, in a thickness of 4000 angstrom by the VD method or the like, and the oxide film and the polycrystalline silicon film are simultaneously patterned to form a gate oxide film 511 and a gate electrode 512. next,
Self-aligned on both sides of these gates, eg 10 ²⁰ cm
Source region 507 of the n-channel transistor by ion-implanting and diffusing an n-type impurity such as arsenic having a high concentration of about ^−3.
At the same time as forming the n-type diffusion layer to be the drain region 508, the single crystal silicon film 503 in the region other than these regions 507 and 508 is formed as the base layer 506, the SiGe alloy film 504 is formed as the transition layer 509, and the single crystal silicon film 505 is formed. Each is formed as a channel formation layer 510 (FIG. 14).
(C)).

After that, a hole for a trench is opened, and in that state, a silicon oxide film is formed on the entire surface by a CVD method or the like, and then contact holes reaching the source / drain regions 507 and 508 are opened respectively, and the element is formed. A source electrode 515 and a drain electrode 516 are formed by forming an inter-separation oxide film 514 and an inter-layer separation oxide film 513, and further burying a metal wiring in this contact hole to form a semiconductor according to an embodiment of the present invention. The device is formed (FIG. 14 (d)). In this case, the electrodes 515 and 516 may be made of any material as long as they can make ohmic contact with the n-type diffusion layer.

In this embodiment, first, in order to form the single crystal silicon film 503 which becomes the base layer 506 on the oxide film 502 for SOI, first, a polycrystalline silicon film is deposited, and this is annealed to form a single crystal. However, for example, a SIMOX method in which oxygen atoms are ion-implanted into a silicon substrate to form a buried oxide film may be used. Alternatively, epitaxial growth may be performed directly on the insulating film.

Although a polycrystalline silicon film is used for the gate electrode 512, if a desired threshold value can be obtained,
It may be another semiconductor material, a silicide compound, or a metal such as aluminum or tungsten.

Further, in the above embodiment, the SiGe alloy was used as a means for changing the forbidden band in the transition layer 509. In the SiGe alloy, when the content ratio of germanium is set to about 20%, the forbidden band is 0.1 than that of silicon.
It becomes narrower than eV. In the case of a SiGe alloy, this change in the forbidden band is mainly due to the change in the valence band, and the electrons flowing in the conduction band are hardly affected, but the holes flowing in the valence band have a germanium content ratio. The tilt of the valence band caused by the change causes the force toward the higher germanium ratio. If the forbidden band difference of 0.1 eV is 1000 angstrom, the electric field strength is 10 kV / cm, and holes can be flowed by this electric field. Therefore, n-channel SOIMO
Electrons, which are the main current component of the SFET, play a role of promptly flowing out excess holes generated by collision ionization in the vicinity of the drain in a direction having a high germanium ratio, that is, in a deep direction opposite to the gate. Other than the SiGe alloy, any substance may be used as long as the forbidden band can be smoothly reduced and the main part of the change is the change on the valence band side.

Also, since the intrinsic carrier concentration is high where the forbidden band is narrow, the recombination probability of holes that have flowed in increases. In addition, even if it remains, the distance from the gate is larger than that in the conventional structure.
It becomes possible to stabilize the drain current without changing the potential of the substrate like T.

Further, in the p-channel SOI MOSFET, if a material that can smoothly reduce the forbidden band is used and the main part of the change is the change on the conduction band side, the SOI n-channel MOSFET described above is used. A high performance SOI type p-channel MOSFET similar to the above is possible.

[0102]

As is clear from the above description, according to the present invention, the energy on the substrate side of the channel forming layer is lower than that of the main conduction carriers on the substrate side, and the energy is lower in the vicinity of the drain region. Since the newly generated charges generated by the impact ionization move to the substrate side faster than the conventional MIS transistor, it is difficult to inject high-energy charges into the gate insulating film, and deterioration of the film quality of the gate insulating film is suppressed. Will be done.

Further, since the newly-generated charges are less likely to be accumulated under the channel formation region, stable current-voltage characteristics can be obtained up to a high drain voltage.

Furthermore, by providing a transition layer whose energy decreases from the gate insulating film side toward the semiconductor substrate side, the charges generated by impact ionization can be promptly flown to the lower part.

Furthermore, if the energy is reduced from the drain region side toward the source region side, the charges generated by impact ionization will be promptly discharged through the source electrode.

Particularly, in the SOI type MIS transistor, the impurity concentration of the channel forming layer on the isolation oxide film can be made lower than that of the MIS transistor of the normal structure having no SOI structure. Therefore, the carrier concentration is originally low and it is generated by collision ionization. Electrons or holes easily diffuse in the direction away from the gate insulating film. Therefore, higher reliability can be realized as compared with the MIS transistor having the normal structure.

[Brief description of drawings]

FIG. 1 is an n-channel MOSF according to a first embodiment of the present invention.
The element sectional view showing the structure of ET.

FIG. 2 is an n-channel MOSF according to a second embodiment of the present invention.
The element sectional view showing the structure of ET.

FIG. 3 is an n-channel MOSF according to a third embodiment of the present invention.
The element sectional view showing the structure of ET.

FIG. 4 is an element sectional view showing the structure of an SOI n-channel MOSFET according to a fourth embodiment of the present invention.

FIG. 5 is an element sectional view showing the structure of an SOI n-channel MOSFET according to a fifth embodiment of the present invention.

FIG. 6 is an element sectional view showing the structure of an SOI n-channel MOSFET according to a sixth embodiment of the present invention.

FIG. 7 is an n-channel MOSF according to a seventh embodiment of the present invention.
The element sectional view showing the structure of ET.

FIG. 8 is an n-channel MOSF according to an eighth embodiment of the present invention.
The element sectional view showing the structure of ET.

FIG. 9 is an element sectional view showing the structure of an SOI n-channel MOSFET according to a ninth embodiment of the present invention.

FIG. 10 is an element sectional view showing the structure of an SOI n-channel MOSFET according to a tenth embodiment of the present invention.

FIG. 11 is an n-channel MO according to an eleventh embodiment of the present invention.
The element sectional view showing the structure of SFET.

FIG. 12 is a cross-sectional view of elements for each step showing a manufacturing process of the FET structure shown in FIG. 1.

FIG. 13 is a sectional view of the element for each step showing the manufacturing process of the FET structure shown in FIG. 4;

FIG. 14 is a sectional view of an element by step showing the manufacturing process of the FET structure shown in FIG. 11;

FIG. 15 is an element cross-sectional view showing the structure of a conventional n-channel MOSFET.

FIG. 16 is an element cross-sectional view showing the structure of a conventional SOI n-channel MOSFET.

FIG. 17 is an equipotential diagram showing a potential distribution in a conventional SOI n-channel MOSFET.

18 is an SOI n-channel MOSFE shown in FIG.
The curve diagram which shows the VD-ID characteristic in T.

[Explanation of symbols]

11, 21, 31, 41, 51, 61, 71, 81, 9
1, 101, 201 p-type silicon substrate 12, 22, 32, 43, 53, 63, 72, 82, 9
3, 103, 204 n ⁺ type source region 13, 23, 33, 44, 54, 64, 73, 83, 9
4, 104, 205 n ⁺ type drain region 14, 24, 34, 45, 55, 65, 74, 84, 9
5,105,206 Gate oxide film 15, 25, 35, 46, 56, 66, 75, 85, 9
6, 106, 207 Gate electrode 16, 26, 47, 57, 76, 97, 211 Channel forming layer 17, 28, 37, 48, 59, 68 Constant energy layer 27, 36, 58, 67, 77, 86, 98 , 107,
212 transition layer 42, 52, 62, 92, 102, 202 interlayer isolation oxide film

Claims (5)

[Claims] 1. An insulated gate transistor, comprising: a gate insulating film, which is disposed below a gate insulating film and has a polarity opposite to that of a main conduction carrier, on a side farther from the gate insulating film. A semiconductor device comprising an energy state adjusting layer whose energy state is adjusted to be lower than that on the side closer to the film. 2. The semiconductor device according to claim 1, wherein the energy state adjusting layer is provided with a constant energy layer having a constant energy over the entire area thereof. 3. The semiconductor device according to claim 1, wherein the energy state adjusting layer includes a transition layer whose energy decreases from the gate insulating film side toward the semiconductor substrate side. 4. The semiconductor device according to claim 1, wherein the energy state adjusting layer includes a transition layer whose energy decreases from the drain region side toward the source region side. 5. An interlayer isolation insulating layer for electrically insulating and isolating the semiconductor substrate and the energy state adjusting layer from each other is provided between the semiconductor substrate and the energy state adjusting layer. Semiconductor device.