JPH051625B2 - - Google Patents
Info
- Publication number
- JPH051625B2 JPH051625B2 JP24631384A JP24631384A JPH051625B2 JP H051625 B2 JPH051625 B2 JP H051625B2 JP 24631384 A JP24631384 A JP 24631384A JP 24631384 A JP24631384 A JP 24631384A JP H051625 B2 JPH051625 B2 JP H051625B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- gate oxide
- insulator
- semiconductor layer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 30
- 239000012212 insulator Substances 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 11
- 239000013078 crystal Substances 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 19
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 230000006866 deterioration Effects 0.000 description 7
- 239000000969 carrier Substances 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、半導体装置に係わり、特に絶縁体上
の半導体層中にMOSトランジスタを形成してな
る半導体装置の改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and more particularly to improvement of a semiconductor device in which a MOS transistor is formed in a semiconductor layer on an insulator.
周知の如く、従来のように半導体層中に形成す
る素子を微細化してこれを高集積化するには限界
があり、最近これを越える手段として多層に素子
を形成する３次元半導体装置、また絶縁基板上の
半導体層中に素子を形成する技術が提案されてい
る。
As is well known, there is a limit to the conventional method of miniaturizing elements formed in a semiconductor layer to increase their integration.Recently, as a means to overcome this, three-dimensional semiconductor devices in which elements are formed in multiple layers, and insulation Techniques have been proposed for forming elements in a semiconductor layer on a substrate.
ところで、上記の半導体装置を構成する素子と
してはMOSトランジスタが用いられているが、
このMOSトランジスタはソース・ドレイン領域
を除き絶縁体に囲まれているので、特にソース・
ドレインの電極を除き電気的に絶縁されているこ
とになる。MOSトランジスタとして、例えばＮ
チヤネルMOSトランジスタを選び動作させると、
ソースより流れ出した電子はドレイン電圧に加速
されてドレイン方向に流れる。この時、加速され
た電子はなだれ現象により電子・正孔対を発生す
る。発生した電子・正孔対の内、電子はドレイン
へ流れるが、正孔はその逃げ場所がないのでチヤ
ネル下の領域に蓄積し、電位を上昇させる。この
ため、より多くの電子が流れてさらに多くの電
子・正孔対が発生し、発生したキヤリアがゲート
酸化膜中に進入し、デバイス特性の劣化を招くこ
とになる。そして、この問題はチヤネル領域が短
くなる程、つまり素子が微細化する程顕著となる
ものである。 By the way, although MOS transistors are used as elements constituting the above semiconductor device,
This MOS transistor is surrounded by an insulator except for the source and drain regions.
It is electrically insulated except for the drain electrode. As a MOS transistor, for example, N
When you select a channel MOS transistor and operate it,
Electrons flowing from the source are accelerated by the drain voltage and flow toward the drain. At this time, the accelerated electrons generate electron-hole pairs due to an avalanche phenomenon. Of the generated electron-hole pairs, the electrons flow to the drain, but the holes have no place to escape, so they accumulate in the region below the channel, increasing the potential. Therefore, more electrons flow, more electron-hole pairs are generated, and the generated carriers enter the gate oxide film, causing deterioration of device characteristics. This problem becomes more pronounced as the channel region becomes shorter, that is, as the element becomes finer.
本発明は上記の事情を考慮してなされたもの
で、その目的とするところは、インパクトイオン
化により発生したキヤリア対のゲート酸化膜への
進入に起因する素子特性劣化を防止することがで
き、高速化及び高集積化に好適する半導体装置を
提供することにある。
The present invention has been made in consideration of the above circumstances, and its purpose is to prevent the deterioration of device characteristics caused by the entry of carrier pairs generated by impact ionization into the gate oxide film, and to prevent the deterioration of device characteristics at high speed. It is an object of the present invention to provide a semiconductor device suitable for increasing the size and integration.
本発明の骨子は、チヤネル領域をゲート酸化膜
に沿つた曲面状に形成することにより、インパク
トイオン化により発生したキヤリア対のゲート酸
化膜への進入を軽減することにある。
The gist of the present invention is to reduce the intrusion of carrier pairs generated by impact ionization into the gate oxide film by forming the channel region in a curved shape along the gate oxide film.
即ち本発明は、絶縁体上の半導体層中にMOS
トランジスタを形成してなる半導体装置におい
て、前記半導体層に前記絶縁膜に達する深さまで
開孔部を形成し、この開孔部の壁面にゲート酸化
膜を形成し、このゲート酸化膜に接する前記半導
体層にソース・ドレイン領域を形成し、さらに前
記開孔部に上記ゲート酸化膜を介してゲート電極
を埋込み形成するようにしたものである。 That is, the present invention has a MOS in a semiconductor layer on an insulator.
In a semiconductor device formed with a transistor, an opening is formed in the semiconductor layer to a depth that reaches the insulating film, a gate oxide film is formed on a wall surface of the opening, and the semiconductor layer is in contact with the gate oxide film. A source/drain region is formed in the layer, and a gate electrode is buried in the opening through the gate oxide film.
本発明によれば、チヤネル領域が曲面状に形成
されることになるので、ソースより流れ出たキヤ
リアは弧を描きながらドレイン方向に流れ、ドレ
イン近傍では加速されてゲート酸化膜から離れて
流れるようになる。このため、インパクトイオン
化により発生したキヤリア対のゲート酸化膜への
進入が少なくなり、ゲート酸化膜の劣化を未然に
防止することができる。従つて、素子特性の劣化
を防止することができ、高速・高集積の素子とし
て実用上十分な特性を持たせることが可能とな
る。
According to the present invention, since the channel region is formed in a curved shape, carriers flowing out from the source flow in an arc toward the drain, and are accelerated near the drain and flow away from the gate oxide film. Become. Therefore, carrier pairs generated by impact ionization are less likely to enter the gate oxide film, and deterioration of the gate oxide film can be prevented. Therefore, deterioration of device characteristics can be prevented, and it is possible to provide practically sufficient characteristics as a high-speed, highly integrated device.
以下、本発明の詳細を図示の実施例によつて説
明する。
Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.
第１図乃至第３図は本発明の一実施例に係わる
半導体装置の製造工程を示す図である。まず、第
１図ａに平面図を、第１図ｂに同図ａの矢視Ａ−
Ａ断面を示す如く、絶縁基板（絶縁体）１１上に
形成され既に素子分離された厚さ0.2［μm］のシ
リコン層（半導体層）１２に対して、中央部に直
径0.1［μm］の円形の開孔部１３を形成する。こ
こで、上記絶縁体１１としては、サフアイア等の
単結晶絶縁基板若しくは単結晶半導体基板上に絶
縁膜を形成してなるものであつてもよい。また、
シリコン層１２は絶縁体１１上に形成されたの
ち、ビームアニール等によつて再結晶化されたも
のである。その後、シリコン層１２の表面を酸化
して開孔部１３の側壁にゲート酸化膜１４を形成
する。なお、このシリコン層１２の上面にも酸化
膜１４′が形成される。 1 to 3 are diagrams showing the manufacturing process of a semiconductor device according to an embodiment of the present invention. First, Fig. 1a shows a plan view, and Fig. 1b shows the arrow A--
As shown in cross-section A, a circular shape with a diameter of 0.1 [μm] is formed in the center of a silicon layer (semiconductor layer) 12 with a thickness of 0.2 [μm] formed on an insulating substrate (insulator) 11 and already separated into elements. An opening 13 is formed. Here, the insulator 11 may be formed by forming an insulating film on a single crystal insulating substrate such as sapphire or a single crystal semiconductor substrate. Also,
The silicon layer 12 is formed on the insulator 11 and then recrystallized by beam annealing or the like. Thereafter, the surface of the silicon layer 12 is oxidized to form a gate oxide film 14 on the side walls of the opening 13. Note that an oxide film 14' is also formed on the upper surface of this silicon layer 12.
次に、第２図ａに平面図を、第２図ｂに同図ａ
の矢視Ｂ−Ｂ断面を示す如く、開孔部１３内にゲ
ート電極用のポリシリコン膜１５を埋込み形成す
る。次いで、ソース・ドレイン領域となるべきと
ころの酸化膜１４′をエツチングにより除去した
のち、該領域に例えばAs等のＮ型不純物のイオ
ン注入を行いソース・ドレイン領域１６ａ，１６
ｂを形成する。このとき、チヤネル領域１７はソ
ース・ドレイン間にゲート酸化膜１４に沿つて曲
面状に形成されることになる。 Next, Figure 2a shows the plan view, and Figure 2b shows the same figure a.
As shown in the cross section taken along line B-B, a polysilicon film 15 for a gate electrode is buried in the opening 13. Next, after removing the oxide film 14' that is to become the source/drain regions by etching, ions of N-type impurities such as As are implanted into the regions to form the source/drain regions 16a, 16.
form b. At this time, the channel region 17 is formed in a curved shape along the gate oxide film 14 between the source and drain.
次に、第３図ａに平面図を、第３図ｂに同図ａ
の矢視Ｃ−Ｃ断面を示す如く、気相成長法で全面
にSiO2膜（層間絶縁膜）１８を形成し、この
SiO2膜１８にゲート電極及びソース・ドレイン
電極間のコンタクトホール１９をそれぞれ開孔す
る。その後、Al配線層２０を形成することによ
つて、ＮチヤネルMOSトランジスタが完成する
ことになる。 Next, Figure 3a shows a plan view, and Figure 3b shows the same figure a.
As shown in the cross section taken along arrow C-C, a SiO 2 film (interlayer insulating film) 18 is formed on the entire surface by vapor phase growth.
Contact holes 19 are formed in the SiO 2 film 18 between the gate electrode and between the source and drain electrodes. Thereafter, by forming an Al wiring layer 20, an N-channel MOS transistor is completed.
かくして作成されたMOSトランジスタにおい
ては、シリコン中でのキヤリアの平均自由行程が
数100［Å］と短いため、このMOSトランジスタ
を動作させると、第４図に示す如くソース１６ａ
から流れ出した電子はゲート酸化膜１４に沿つて
弧を描きながら流れる。ところが、ドレイン１６
ｂ近傍では電子が加速されるため、電子はゲート
酸化膜１４を離れてバルクシリコン中を流れるよ
うになる。この状態で発生するホツトキヤリア
は、ゲート酸化膜１４に到達する前に減速される
ため、ゲート酸化膜１４に侵入することが難しく
なり、これによりゲート酸化膜１４の劣化が妨げ
られることになる。 In the MOS transistor thus created, the mean free path of carriers in silicon is as short as several hundred angstroms, so when this MOS transistor is operated, the source 16a as shown in FIG.
The electrons flowing from the gate oxide film 14 flow in an arc along the gate oxide film 14. However, drain 16
Since the electrons are accelerated in the vicinity of b, the electrons leave the gate oxide film 14 and flow through the bulk silicon. The hot carriers generated in this state are decelerated before reaching the gate oxide film 14, making it difficult for them to penetrate into the gate oxide film 14, thereby preventing deterioration of the gate oxide film 14.
このように本実施例によれば、チヤネル領域１
７をゲート酸化膜１４に沿つて曲面状に形成して
いるので、インパクトイオン化により発生するキ
ヤリアのゲート酸化膜１４への侵入を軽減するこ
とができる。このため、素子特性の劣化を未然防
止することができ、高速・高集積化に極めて有効
である。 As described above, according to this embodiment, the channel area 1
7 is formed in a curved shape along the gate oxide film 14, it is possible to reduce the intrusion of carriers generated by impact ionization into the gate oxide film 14. Therefore, it is possible to prevent deterioration of element characteristics, and it is extremely effective for achieving high speed and high integration.
なお本発明は上述した実施例に限定されるもの
ではない。例えば、前記半導体層中に形成する開
孔部は円形に限るものではなく、楕円形であつて
もよいし、多角形を適用することも可能である。
さらに、開孔部の径及び深さ（半導体層の厚み）
等の条件は、仕様に応じて適宜変更可能である。
また、前記絶縁体としてはサフアイア等の単結晶
絶縁基板、或いは単結晶半導体基板上に絶縁膜を
形成したものを用いればよい。さらに、絶縁体上
に形成する半導体層はシリコンに限るものではな
く、他の半導体であつてもよいのは勿論のことで
ある。また、デバイスは絶縁体上に形成したが、
ＮチヤネルトランジスタであればＰ型基板上に、
ＰチヤネルトランジスタであればＮ型基板上に形
成することも可能である。その他、本発明の要旨
を逸脱しない範囲で、種々変形して実施すること
ができる。 Note that the present invention is not limited to the embodiments described above. For example, the opening formed in the semiconductor layer is not limited to a circular shape, but may be elliptical or polygonal.
Furthermore, the diameter and depth of the opening (thickness of the semiconductor layer)
These conditions can be changed as appropriate depending on the specifications.
Further, as the insulator, a single crystal insulating substrate such as sapphire, or a single crystal semiconductor substrate on which an insulating film is formed may be used. Furthermore, it goes without saying that the semiconductor layer formed on the insulator is not limited to silicon, and may be other semiconductors. Also, although the device was formed on an insulator,
If it is an N-channel transistor, on a P-type substrate,
A P-channel transistor can also be formed on an N-type substrate. In addition, various modifications can be made without departing from the gist of the present invention.
第１図ａ，ｂ乃至第３図ａ，ｂは本発明の一実
施例に係わるMOS型半導体装置の製造工程を示
すもので、第１図ａは平面図、第１図ｂは同図ａ
の矢視Ａ−Ａ断面図、第２図ａは平面図、第２図
ｂは同図ａの矢視Ｂ−Ｂ断面図、第３図ａは平面
図、第３図ｂは同図ａの矢視Ｃ−Ｃ断面図、第４
図は上記実施例の作用を説明するためのものでソ
ースからドレイン方向に流れる電子の動きを示す
模式図である。
１１…絶縁基板（絶縁体）、１２…シリコン層
（半導体層）、１３…開孔部、１４…ゲート酸化
膜、１５…ポリシリコン膜（ゲート電極）、１６
ａ，１６ｂ…ソース・ドレイン領域、１７…チヤ
ネル領域、１８…SiO2膜（層間絶縁膜）、１９…
コンタクトホール、２０…Al配線層。
1a, b to 3a, b show the manufacturing process of a MOS type semiconductor device according to an embodiment of the present invention, in which FIG. 1a is a plan view and FIG. 1b is a plan view of the same.
Fig. 2a is a plan view, Fig. 2b is a sectional view taken along arrow B-B in Fig. 3a, Fig. 3b is a plan view, and Fig. 3b is a plan view. Cross-sectional view taken along arrow C-C, No. 4
The figure is for explaining the operation of the above embodiment, and is a schematic diagram showing the movement of electrons flowing from the source toward the drain. DESCRIPTION OF SYMBOLS 11... Insulating substrate (insulator), 12... Silicon layer (semiconductor layer), 13... Opening part, 14... Gate oxide film, 15... Polysilicon film (gate electrode), 16
a, 16b... Source/drain region, 17... Channel region, 18... SiO 2 film (interlayer insulating film), 19...
Contact hole, 20...Al wiring layer.
Claims (1)
を形成してなる半導体装置において、前記半導体
層に前記絶縁膜に達する深さまで開孔された開孔
部と、この開孔部の壁面に形成されたゲート酸化
膜と、このゲート酸化膜に接する上記半導体層に
相互に離間して形成されたソース・ドレイン領域
と、前記開孔部に上記ゲート酸化膜を介して埋込
み形成されたゲート電極とを具備してなることを
特徴とする半導体装置。 ２ 前記絶縁体は、単結晶絶縁基板であることを
特徴とする特許請求の範囲第１項記載の半導体装
置。 ３ 前記絶縁体は、単結晶半導体基板上に絶縁膜
を形成してなるものであることを特徴とする特許
請求の範囲第１項記載の半導体装置。[Scope of Claims] 1. A semiconductor device in which a MOS transistor is formed in a semiconductor layer on an insulator, comprising: an opening formed in the semiconductor layer to a depth reaching the insulating film; and the opening. a gate oxide film formed on the wall surface of the gate oxide film, a source/drain region formed at a distance from each other in the semiconductor layer in contact with the gate oxide film, and a source/drain region formed in the opening through the gate oxide film. What is claimed is: 1. A semiconductor device comprising: a gate electrode; 2. The semiconductor device according to claim 1, wherein the insulator is a single crystal insulating substrate. 3. The semiconductor device according to claim 1, wherein the insulator is formed by forming an insulating film on a single crystal semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24631384A JPS61125174A (en) | 1984-11-22 | 1984-11-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24631384A JPS61125174A (en) | 1984-11-22 | 1984-11-22 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61125174A JPS61125174A (en) | 1986-06-12 |
| JPH051625B2 true JPH051625B2 (en) | 1993-01-08 |
Family
ID=17146695
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24631384A Granted JPS61125174A (en) | 1984-11-22 | 1984-11-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61125174A (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2510599B2 (en) * | 1987-07-01 | 1996-06-26 | 三菱電機株式会社 | Field effect transistor |
| US5308997A (en) * | 1992-06-22 | 1994-05-03 | Motorola, Inc. | Self-aligned thin film transistor |
| JP3356162B2 (en) | 1999-10-19 | 2002-12-09 | 株式会社デンソー | Semiconductor device and manufacturing method thereof |
| JP3528750B2 (en) | 2000-03-16 | 2004-05-24 | 株式会社デンソー | Semiconductor device |
| US6642577B2 (en) | 2000-03-16 | 2003-11-04 | Denso Corporation | Semiconductor device including power MOSFET and peripheral device and method for manufacturing the same |
| JP3534084B2 (en) | 2001-04-18 | 2004-06-07 | 株式会社デンソー | Semiconductor device and manufacturing method thereof |
| US9129681B2 (en) | 2012-04-13 | 2015-09-08 | Sandisk Technologies Inc. | Thin film transistor |
| US9165933B2 (en) | 2013-03-07 | 2015-10-20 | Sandisk 3D Llc | Vertical bit line TFT decoder for high voltage operation |
| US9240420B2 (en) | 2013-09-06 | 2016-01-19 | Sandisk Technologies Inc. | 3D non-volatile storage with wide band gap transistor decoder |
-
1984
- 1984-11-22 JP JP24631384A patent/JPS61125174A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61125174A (en) | 1986-06-12 |
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