JP2985825B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2985825B2 JP2985825B2 JP9064589A JP6458997A JP2985825B2 JP 2985825 B2 JP2985825 B2 JP 2985825B2 JP 9064589 A JP9064589 A JP 9064589A JP 6458997 A JP6458997 A JP 6458997A JP 2985825 B2 JP2985825 B2 JP 2985825B2
- Authority
- JP
- Japan
- Prior art keywords
- nitride film
- film
- thickness
- gate electrode
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 25
- 150000004767 nitrides Chemical class 0.000 claims description 47
- 239000000758 substrate Substances 0.000 claims description 19
- 238000009792 diffusion process Methods 0.000 description 10
- 239000010410 layer Substances 0.000 description 10
- 238000000034 method Methods 0.000 description 7
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- 239000001257 hydrogen Substances 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/564—Details not otherwise provided for, e.g. protection against moisture
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Formation Of Insulating Films (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、外部から水素の侵
入を防止する窒化膜を備えた半導体装置に関し、特にゲ
ート酸化膜の破壊寿命を向上させた半導体装置に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device provided with a nitride film for preventing intrusion of hydrogen from the outside, and more particularly to a semiconductor device having an improved gate oxide film having a longer life.
【０００２】[0002]
【従来の技術】従来の技術について図を用いて説明す
る。図３はゲート電極３上に窒化膜８を備えた従来の半
導体装置を示す断面図である。図３において、Ｓｉ基板
である半導体基板１には、ソース領域４とドレイン領域
５とが互いに離隔して形成されている。そして、このソ
ース領域４とドレイン領域５との間における半導体基板
１の主表面上には、酸化シリコン膜によってゲート絶縁
膜２が形成され、ゲート絶縁膜２上にはゲート電極３が
形成されている。2. Description of the Related Art A conventional technique will be described with reference to the drawings. FIG. 3 is a cross-sectional view showing a conventional semiconductor device provided with a nitride film 8 on a gate electrode 3. In FIG. 3, a source region 4 and a drain region 5 are formed on a semiconductor substrate 1 which is a Si substrate so as to be separated from each other. On the main surface of the semiconductor substrate 1 between the source region 4 and the drain region 5, a gate insulating film 2 is formed by a silicon oxide film, and a gate electrode 3 is formed on the gate insulating film 2. I have.
【０００３】また、ゲート電極３の両側には側壁膜６が
形成され、その結果半導体基板１における拡散層はＬＤ
Ｄ構造となっている。さらに、ゲート電極３は薄い酸化
膜１２によって覆われている。この酸化膜１２およびゲ
ート電極３からはみ出た半導体基板１は、窒化膜８によ
って覆われている。窒化膜８の上には層間絶縁膜１３が
形成され、層間絶縁膜１３の上にはプラズマ窒化膜１４
が形成されている。A sidewall film 6 is formed on both sides of the gate electrode 3 so that the diffusion layer in the semiconductor substrate 1 is
It has a D structure. Further, the gate electrode 3 is covered with a thin oxide film 12. The semiconductor substrate 1 protruding from the oxide film 12 and the gate electrode 3 is covered with a nitride film 8. An interlayer insulating film 13 is formed on the nitride film 8, and a plasma nitride film 14 is formed on the interlayer insulating film 13.
Are formed.
【０００４】このように従来は、ゲート電極３の直上に
窒化膜８を形成することによって外部から水素の侵入を
防止し、ホットキャリア耐性の低下を抑制していた。As described above, conventionally, the formation of the nitride film 8 immediately above the gate electrode 3 prevents the intrusion of hydrogen from the outside and suppresses the decrease in hot carrier resistance.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、このよ
うにゲート電極３の直上に窒化膜８を形成すると、種々
の問題点が生じる。すなわち、窒化膜８の上層に形成す
る層間絶縁膜やプラズマ窒化膜等を形成するプロセス時
の熱履歴によって窒化膜の応力が激しく変化し、その結
果この応力がゲート酸化膜に作用してゲート酸化膜の信
頼性寿命が低下するという問題点がある。本発明は、こ
のような課題を解決するためのものであり、熱履歴等に
よって窒化膜に応力が発生しても、ゲート酸化膜の破壊
を防止することができる半導体装置を提供することを目
的とする。However, when the nitride film 8 is formed directly on the gate electrode 3 as described above, various problems occur. That is, the stress of the nitride film changes drastically due to the thermal history during the process of forming an interlayer insulating film, a plasma nitride film, and the like formed on the nitride film 8, and as a result, this stress acts on the gate oxide film to cause gate oxide film formation. There is a problem that the reliability life of the film is reduced. An object of the present invention is to solve such a problem, and an object of the present invention is to provide a semiconductor device capable of preventing a gate oxide film from being broken even when a stress is generated in a nitride film due to thermal history or the like. And
【０００６】[0006]
【課題を解決するための手段】このような目的を達成す
るために、本発明に係る半導体装置は、下地絶縁膜上に
所定の厚さの窒化膜を形成し、上記下地絶縁膜の厚さは
上記窒化膜の厚さの２０倍以上にしたものである。この
ように構成することにより、本発明は拡散中の熱履歴に
よって生じた応力がゲート酸化膜に作用しないため、ゲ
ート酸化膜の寿命が低下することがない。In order to achieve the above object, a semiconductor device according to the present invention comprises forming a nitride film having a predetermined thickness on a base insulating film, and forming a nitride film having a predetermined thickness on the base insulating film. Is 20 times or more the thickness of the nitride film. With this configuration, in the present invention, since the stress generated by the thermal history during diffusion does not act on the gate oxide film, the life of the gate oxide film does not decrease.
【０００７】[0007]
【発明の実施の形態】次に、本発明の一つの実施の形態
の製造工程について詳細に説明する。図１は本発明の一
つの実施の形態およびその製造工程を示す説明図であ
る。Next, a manufacturing process according to one embodiment of the present invention will be described in detail. FIG. 1 is an explanatory view showing one embodiment of the present invention and a manufacturing process thereof.
【０００８】まず、図１（ａ）において、Ｓｉ基板であ
る半導体基板１上に熱酸化によってゲート酸化膜２（膜
厚は３〜１５ｎｍ程度）を形成する。そして、このゲー
ト酸化膜２上にゲート電極３の材料となる伝導物（例え
ばポリシリコン等）を基板全面に亘ってスパッタまたは
ＣＶＤよって成膜し、リソグラフィー技術およびドライ
エッチング技術等を用いてゲート電極３を形成する。First, in FIG. 1A, a gate oxide film 2 (having a thickness of about 3 to 15 nm) is formed on a semiconductor substrate 1, which is an Si substrate, by thermal oxidation. Then, a conductive material (for example, polysilicon or the like) as a material of the gate electrode 3 is formed on the gate oxide film 2 by sputtering or CVD over the entire surface of the substrate, and the gate electrode is formed by using a lithography technique and a dry etching technique. Form 3
【０００９】さらに、ＬＤＤ構造のＭＯＳＴｒを作成す
るため、拡散領域となるソース領域４およびドレイン領
域５に対してＮＭＯＳであればＮ型のリン等を低加速電
圧でイオン注入して浅い拡散層を形成する。同様にＰＭ
ＯＳであればＰ型のボロン等を低加速電圧でイオン注入
して浅い拡散層を形成する。Further, in order to form a MOSTr having an LDD structure, if a NMOS is used, N-type phosphorus or the like is ion-implanted at a low accelerating voltage into the source region 4 and the drain region 5 serving as diffusion regions to form a shallow diffusion layer. Form. Similarly PM
In the case of OS, P-type boron or the like is ion-implanted at a low acceleration voltage to form a shallow diffusion layer.
【００１０】その後、半導体基板１の全面に亘って酸化
膜をＣＶＤ法によって形成し、全面をエッチバックして
側壁膜６（膜厚は１００ｎｍ程度）を形成する。そし
て、ソース領域４およびドレイン領域５に対してＮＭＯ
ＳであればＮ型のヒ素等をイオン注入し、低抵抗の深い
拡散層を形成する。同様にＰＭＯＳであればＰ型のＢＦ
2 等をイオン注入し、低抵抗の深い拡散層を形成する。
さらに、ゲート電極３等を含む半導体基板１の全面に亘
って第１の下地絶縁膜７（膜厚は５００ｎｍ程度）をＣ
ＶＤ法によって形成する。Thereafter, an oxide film is formed over the entire surface of the semiconductor substrate 1 by a CVD method, and the entire surface is etched back to form a sidewall film 6 (having a thickness of about 100 nm). NMO is applied to the source region 4 and the drain region 5.
In the case of S, N-type arsenic or the like is ion-implanted to form a low resistance deep diffusion layer. Similarly, for a PMOS, a P-type BF
2 etc. are ion-implanted to form a low resistance deep diffusion layer.
Further, the first base insulating film 7 (having a thickness of about 500 nm) is formed over the entire surface of the semiconductor substrate 1 including the gate electrode 3 and the like.
It is formed by the VD method.
【００１１】図１（ｂ）において、下地絶縁膜７上には
ＬＰ−ＣＶＤ法によって窒化膜８（膜厚は２０ｎｍ程
度）を形成する。窒化膜８上にはＣＶＤ法によって第２
の下地絶縁膜９（膜厚は５００ｎｍ程度）を形成する。
その後、ＳＯＧ（Ｓｐｉｎ Ｏｆ Ｇｌａｓｓ）を用い
たエッチバック法またはＣＭＰを施して第２の下地絶縁
膜７の表面を平坦化する。そして、基板の全面に亘って
レジスト１０を塗布し、コンタクト開口のためのパター
ニングを施す。なお、窒化膜８の膜厚は下地絶縁膜９か
らの水分侵入を防止するため５ｎｍ以上に保つことが望
ましい。In FIG. 1B, a nitride film 8 (having a thickness of about 20 nm) is formed on the base insulating film 7 by LP-CVD. A second layer is formed on the nitride film 8 by CVD.
Of the base insulating film 9 (having a thickness of about 500 nm).
After that, the surface of the second base insulating film 7 is planarized by performing an etch-back method using SOG (Spin Of Glass) or CMP. Then, a resist 10 is applied over the entire surface of the substrate, and patterning for contact opening is performed. Note that the thickness of the nitride film 8 is desirably kept at 5 nm or more in order to prevent moisture penetration from the underlying insulating film 9.
【００１２】図１（ｃ）において、下地絶縁膜９等に半
導体基板１に達するコンタクトホールを開口した後、配
線層１１の材料を基板全面に亘ってスパッタする。そし
て、リソグラフィー技術およびドライエッチング技術等
によって所望の配線パターンを形成する。以上の結果、
本発明に係る半導体装置の一つの実施の形態が作成され
た。In FIG. 1C, after a contact hole reaching the semiconductor substrate 1 is opened in the base insulating film 9 and the like, the material of the wiring layer 11 is sputtered over the entire surface of the substrate. Then, a desired wiring pattern is formed by a lithography technique, a dry etching technique, or the like. As a result,
One embodiment of the semiconductor device according to the present invention has been created.
【００１３】次に、図１に係る半導体装置のゲート酸化
膜の寿命について、実験結果に基づいて説明する。図２
は図１に係るゲート酸化膜２の破壊寿命を示すグラフで
ある。図２において、横軸はゲート電極３−窒化膜８間
の距離（ｎｍ）を示し、縦軸は１ｃｍ2 当たりのゲート
酸化膜２に注入された総注入電荷量を示す。すなわち、
この総注入電荷量はゲート酸化膜２が破壊されるまで注
入された電荷の総量を示し、ゲート酸化膜２の破壊寿命
に相当するものである。Next, the life of the gate oxide film of the semiconductor device shown in FIG. 1 will be described based on experimental results. FIG.
3 is a graph showing a breakdown life of the gate oxide film 2 according to FIG. In FIG. 2, the horizontal axis indicates the distance (nm) between the gate electrode 3 and the nitride film 8, and the vertical axis indicates the total amount of injected charges injected into the gate oxide film 2 per 1 cm 2 . That is,
This total injected charge amount indicates the total amount of charges injected until the gate oxide film 2 is destroyed, and corresponds to the destruction life of the gate oxide film 2.
【００１４】図２から明らかなように、窒化膜８の膜厚
が５ｎｍの場合は、ゲート電極３の位置と窒化膜８の位
置とを約１００ｎｍ以上離すことによって窒化膜８が無
いときと同等の破壊寿命となっている。また、ゲート電
極３と窒化膜８との離隔距離を大きくするにつれてさら
に総注入電荷量を大きくできることが図２よりわかる。
すなわち、ゲート電極３と窒化膜８とは１００ｎｍ／５
ｎｍ＝２０（倍）以上離す必要がある。As is apparent from FIG. 2, when the thickness of the nitride film 8 is 5 nm, the position of the gate electrode 3 and the position of the nitride film 8 are separated from each other by about 100 nm or more, which is equivalent to the case where the nitride film 8 is not provided. Has a destructive life. FIG. 2 shows that the total injected charge amount can be further increased as the separation distance between the gate electrode 3 and the nitride film 8 is increased.
That is, the gate electrode 3 and the nitride film 8 are 100 nm / 5
It is necessary to separate them by at least nm = 20 (times).
【００１５】ところが、ゲート電極３と窒化膜８の離隔
距離を約１００ｎｍ以下にすると窒化膜８の応力がゲー
ト酸化膜２に対して及ぼす影響が大きくなり、総注入電
荷量は低下している。すなわち、ゲート電極３と窒化膜
８とを近づけすぎるとゲート酸化膜２の寿命は低下す
る。同様の理由で、窒化膜厚が２０ｎｍの場合は、ゲー
ト電極３と窒化膜８との離隔距離を約５００ｎｍ以上に
保つ必要があり、窒化膜８とゲート電極３とは５００ｎ
ｍ／２０ｎｍ＝２５（倍）以上離す必要がある。However, when the distance between the gate electrode 3 and the nitride film 8 is set to about 100 nm or less, the influence of the stress of the nitride film 8 on the gate oxide film 2 increases, and the total injected charge decreases. That is, if the gate electrode 3 is too close to the nitride film 8, the life of the gate oxide film 2 is reduced. For the same reason, when the nitride film thickness is 20 nm, the distance between the gate electrode 3 and the nitride film 8 needs to be maintained at about 500 nm or more.
m / 20 nm = 25 (times) or more.
【００１６】ところで、水素の侵入を防ぐため、窒化膜
８の膜厚はただ厚くすればよいと言うわけではない。窒
化膜８の膜厚はＭＯＳトランジスタの特性や信頼性に対
して大きく影響するものである。すなわち、窒化膜８の
膜厚が２０ｎｍを越えると窒化膜８は水素の拡散に対す
るバリアとなる一方、ゲート酸化膜２−半導体基板１の
界面に存在する界面準位密度が高くなってトランジスタ
の特性が不安定になる。例えば、図示してはいないがゲ
ート電極３と窒化膜８との離隔距離を１５０ｎｍ、窒化
膜８の膜厚が５０ｎｍとなるとトランジスタ特性のう
ち、特にしきい値電圧Ｖｔのばらつきが窒化膜８が無い
場合と比較して約２倍になることが実験によってわかっ
ている。By the way, in order to prevent intrusion of hydrogen, it is not always necessary to simply increase the thickness of the nitride film 8. The thickness of the nitride film 8 greatly affects the characteristics and reliability of the MOS transistor. That is, when the thickness of the nitride film 8 exceeds 20 nm, the nitride film 8 functions as a barrier against diffusion of hydrogen, while the interface state density existing at the interface between the gate oxide film 2 and the semiconductor substrate 1 increases, thereby increasing the characteristics of the transistor. Becomes unstable. For example, although not shown, when the separation distance between the gate electrode 3 and the nitride film 8 becomes 150 nm and the film thickness of the nitride film 8 becomes 50 nm, among the transistor characteristics, in particular, the variation in the threshold voltage Vt is reduced. Experiments have shown that the value is about twice as large as the case without.
【００１７】一方、窒化膜８の膜厚が５ｎｍ未満になる
と窒化膜８の水分に対するバリア性が低下し、多層配線
化すると配線層間膜から水分がゲート酸化膜まで拡散し
てスロートラップ（ＢＴ時の特性変動）やホットキャリ
ア等のトランジスタの特性が変動してしまう。したがっ
て、窒化膜８の膜厚は５ｎｍ以上かつ２０ｎｍ以下にす
ることが望ましいといえる。さらに、ゲート電極３と窒
化膜８との離隔距離を窒化膜８の膜厚の２０倍以上にす
ることが望ましいといえる。On the other hand, when the thickness of the nitride film 8 is less than 5 nm, the barrier property of the nitride film 8 against moisture is reduced. Of the transistor) and the characteristics of the transistor, such as hot carriers, fluctuate. Therefore, it can be said that the thickness of the nitride film 8 is desirably 5 nm or more and 20 nm or less. Furthermore, it can be said that it is desirable that the separation distance between the gate electrode 3 and the nitride film 8 be at least 20 times the thickness of the nitride film 8.
【００１８】[0018]
【発明の効果】このように本発明は、ゲート電極と窒化
膜との間に形成した下地絶縁膜の膜厚を窒化膜の膜厚の
２０倍以上にしている。そのため、熱履歴等によって窒
化膜に応力が発生しても、下地絶縁膜によってゲート酸
化膜に作用する応力は緩和され、その結果ゲート酸化膜
の破壊寿命の向上を図ることができる。As described above, according to the present invention, the thickness of the underlying insulating film formed between the gate electrode and the nitride film is set to be at least 20 times the thickness of the nitride film. Therefore, even if stress occurs in the nitride film due to thermal history or the like, the stress acting on the gate oxide film is alleviated by the base insulating film, and as a result, the breakdown life of the gate oxide film can be improved.
【図１】 本発明の一つの実施の形態を示す断面図であ
る。FIG. 1 is a sectional view showing one embodiment of the present invention.
【図２】 図１に係る半導体装置のゲート電極−窒化膜
間の距離とゲート酸化膜の破壊電荷量との関係を示すグ
ラフである。2 is a graph showing a relationship between a distance between a gate electrode and a nitride film of the semiconductor device shown in FIG. 1 and a breakdown charge amount of a gate oxide film.
【図３】 従来例を示す断面図である。FIG. 3 is a sectional view showing a conventional example.
１…半導体基板、２…ゲート酸化膜、３…ゲート電極、
４…ソース側拡散層領域（ソース領域）、５…ドレイン
側拡散層領域（ドレイン領域）、６…側壁膜、７，９…
下地絶縁膜、８…窒化膜、１０…レジスト、１１…配線
層。DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Gate oxide film, 3 ... Gate electrode,
4 ... source side diffusion layer region (source region), 5 ... drain side diffusion layer region (drain region), 6 ... side wall film, 7, 9 ...
Underlying insulating film, 8: nitride film, 10: resist, 11: wiring layer.
Claims (2)
に互いに離隔して形成されたソースおよびドレインと、
前記ソースおよびドレインの間における前記半導体基板
に形成されたゲートと、このゲートおよびゲートからは
み出ている半導体基板を覆うように形成された下地絶縁
膜とを備えた半導体装置において、 前記下地絶縁膜上に所定の厚さの窒化膜を形成し、前記
下地絶縁膜の厚さは前記窒化膜の厚さの２０倍以上にす
ることを特徴とする半導体装置。A semiconductor substrate; a source and a drain formed on a main surface of the semiconductor substrate so as to be separated from each other;
A semiconductor device comprising: a gate formed on the semiconductor substrate between the source and the drain; and a base insulating film formed so as to cover the semiconductor substrate protruding from the gate and the gate; A nitride film having a predetermined thickness, and the thickness of the base insulating film is set to be at least 20 times the thickness of the nitride film.
ことを特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein the thickness of the nitride film is 5 nm or more and 20 nm or less.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9064589A JP2985825B2 (en) | 1997-03-18 | 1997-03-18 | Semiconductor device |
| US09/040,750 US5994764A (en) | 1997-03-18 | 1998-03-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9064589A JP2985825B2 (en) | 1997-03-18 | 1997-03-18 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10261634A JPH10261634A (en) | 1998-09-29 |
| JP2985825B2 true JP2985825B2 (en) | 1999-12-06 |
Family
ID=13262601
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9064589A Expired - Fee Related JP2985825B2 (en) | 1997-03-18 | 1997-03-18 | Semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US5994764A (en) |
| JP (1) | JP2985825B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100688023B1 (en) | 2005-12-28 | 2007-02-27 | 동부일렉트로닉스 주식회사 | Method of fabricating semiconductor device |
| US20150206794A1 (en) * | 2014-01-17 | 2015-07-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for Removing Micro Scratches In Chemical Mechanical Polishing Processes |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR920001716A (en) * | 1990-06-05 | 1992-01-30 | 김광호 | Structure and manufacturing method of stacked capacitor of DRAM cell |
| JPH04186675A (en) * | 1990-11-16 | 1992-07-03 | Matsushita Electron Corp | Semiconductor device |
| JP3172321B2 (en) * | 1993-04-26 | 2001-06-04 | 三洋電機株式会社 | Method for manufacturing semiconductor memory device |
| JPH08316430A (en) * | 1995-05-15 | 1996-11-29 | Mitsubishi Electric Corp | Semiconductor storage device, its manufacture, and stacked capacitor |
-
1997
- 1997-03-18 JP JP9064589A patent/JP2985825B2/en not_active Expired - Fee Related
-
1998
- 1998-03-18 US US09/040,750 patent/US5994764A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US5994764A (en) | 1999-11-30 |
| JPH10261634A (en) | 1998-09-29 |
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