JPH10256534A - Semiconductor device with dmos structure and its manufacture - Google Patents
Semiconductor device with dmos structure and its manufactureInfo
- Publication number
- JPH10256534A JPH10256534A JP9056002A JP5600297A JPH10256534A JP H10256534 A JPH10256534 A JP H10256534A JP 9056002 A JP9056002 A JP 9056002A JP 5600297 A JP5600297 A JP 5600297A JP H10256534 A JPH10256534 A JP H10256534A
- Authority
- JP
- Japan
- Prior art keywords
- region
- substrate
- locos
- gate electrode
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 239000012535 impurity Substances 0.000 claims abstract description 26
- 238000009792 diffusion process Methods 0.000 claims description 24
- 239000010408 film Substances 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 239000010409 thin film Substances 0.000 claims description 4
- 230000005684 electric field Effects 0.000 abstract description 5
- 210000003323 beak Anatomy 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 7
- 241000293849 Cordylanthus Species 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、ＤＭＯＳ構造を
有する半導体装置に関するものであり、特に、耐圧向上
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a DMOS structure, and more particularly, to an improvement in breakdown voltage.
【０００２】[0002]
【従来技術】従来、図４に示すようなＤＭＯＳトランジ
スタが知られている。ＤＭＯＳトランジスタ６１は、ソ
ース領域４を取囲むように、ｐ型拡散領域を設けた二重
拡散型の半導体装置である。ＤＭＯＳトランジスタ６１
は、チャネル領域１６の横方向の拡散を制御することに
よって、チャネル長の決定を行なう。したがって、その
決定が容易となる。2. Description of the Related Art Conventionally, a DMOS transistor as shown in FIG. 4 has been known. The DMOS transistor 61 is a double diffusion type semiconductor device provided with a p-type diffusion region so as to surround the source region 4. DMOS transistor 61
Determines the channel length by controlling the lateral diffusion of the channel region 16. Therefore, the determination is facilitated.
【０００３】かかるＤＭＯＳトランジスタについて、高
耐圧の半導体装置を提供するために、発明者は、図５に
示すようなＬＯＣＯＳ領域の下にドリフトドレイン領域
を形成した半導体装置を考えた。ＤＭＯＳトランジスタ
７１は、ドレイン領域３とソース領域４の間にＬＯＣＯ
Ｓ領域１１が形成されており、ゲート電極１７がＬＯＣ
ＯＳ領域１１の一部に覆うように形成されている。これ
により、ＬＯＣＯＳ領域１１の下部の基板表面領域をド
リフトドレイン領域として用いることができる。また、
ＬＯＣＯＳ領域を有するので、ドリフトドレイン領域と
ゲート電極１７との間の耐圧も向上する。In order to provide a high breakdown voltage semiconductor device for such a DMOS transistor, the inventor has considered a semiconductor device in which a drift drain region is formed below a LOCOS region as shown in FIG. The DMOS transistor 71 has a LOCO between the drain region 3 and the source region 4.
The S region 11 is formed, and the gate electrode 17 is
It is formed so as to cover a part of the OS region 11. Thus, the substrate surface region below the LOCOS region 11 can be used as a drift drain region. Also,
With the LOCOS region, the breakdown voltage between the drift drain region and the gate electrode 17 is also improved.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、ＤＭＯ
Ｓトランジスタ７１においては、以下の様な問題があっ
た。ＤＭＯＳトランジスタ７１においては、ゲート電極
１７が矢印α方向にマスクずれを起こした場合に、ゲー
ト電極１７とともにＰ型拡散層７も矢印α方向にずれ
る。これにより、ゲート電極１７の下のゲート絶縁膜に
位置するＰ型拡散層７がＬＯＣＯＳ領域１１の端部のバ
ーズビーク部の下側に入り、ゲート電極１７に対してチ
ャネル長が短くなる。このため、ゲート電極１７の位置
がずれた場合でも、チャネル長を一定とする為に、図６
に示すように、ＬＯＣＯＳ領域１１の端部のバーズビー
ク部から幅ｗ１だけすきま領域１５を設けて、Ｐ型拡散
層７を形成することも考えられる。しかし、このような
すきま領域１５を設けると、電界集中により絶縁破壊を
おこすおそれがある。However, the DMO
The S transistor 71 has the following problem. In the DMOS transistor 71, when the gate electrode 17 shifts the mask in the direction of the arrow α, the P-type diffusion layer 7 is shifted in the direction of the arrow α together with the gate electrode 17. As a result, the P-type diffusion layer 7 located in the gate insulating film below the gate electrode 17 enters below the bird's beak at the end of the LOCOS region 11, and the channel length becomes shorter than that of the gate electrode 17. For this reason, even if the position of the gate electrode 17 is displaced, in order to keep the channel length constant, FIG.
As shown in FIG. 7, it is conceivable to form a P-type diffusion layer 7 by providing a clearance region 15 with a width w1 from the bird's beak portion at the end of the LOCOS region 11. However, if such a clearance region 15 is provided, there is a possibility that the dielectric breakdown may occur due to the concentration of the electric field.
【０００５】本発明は、上記の様な問題を解決し、ＤＭ
ＯＳ構造を有する半導体装置において、チャネル長の決
定を正確にできると共に、耐圧を向上させた半導体装置
を提供することを目的とする。[0005] The present invention solves the above-mentioned problems and provides a DM
In a semiconductor device having an OS structure, an object is to provide a semiconductor device in which a channel length can be accurately determined and a withstand voltage is improved.
【０００６】[0006]
【課題を解決するための手段】請求項１のＤＭＯＳ構造
を有する半導体装置においては、第１導電型の基板領
域、前記基板領域表面に形成されたＬＯＣＯＳ領域、前
記基板領域の上にゲート絶縁膜を介して形成されたゲー
ト電極であって、その一部が前記ＬＯＣＯＳ領域上に位
置するように形成されたゲート電極、前記ゲート電極の
前記ＬＯＣＯＳ領域とは逆側の前記基板領域表面に形成
された第１導電型のソース領域、前記ＬＯＣＯＳ領域を
挟んで前記ソース領域と逆側の前記基板領域表面に形成
された第１導電型のドレイン領域、前記ソース領域を覆
うように形成された第２導電型の拡散領域であって、前
記ゲート電極に印加される電圧により前記ゲート電極の
下部の領域の表面が導通状態または非導通状態に切換え
られる拡散領域、を備え、前記拡散領域と前記ＬＯＣＯ
Ｓ領域との間のゲート絶縁薄膜の下部の基板領域表面の
不純物濃度が前記ＬＯＣＯＳ領域の下部の基板領域より
も薄いこと、を特徴とする。According to a first aspect of the present invention, there is provided a semiconductor device having a DMOS structure, wherein a first conductivity type substrate region, a LOCOS region formed on the surface of the substrate region, and a gate insulating film on the substrate region. A gate electrode formed through the gate electrode, a part of which is formed on the LOCOS region, and a gate electrode formed on the surface of the substrate region opposite to the LOCOS region of the gate electrode. A first conductive type source region, a first conductive type drain region formed on the surface of the substrate region opposite to the source region with the LOCOS region therebetween, and a second conductive region formed to cover the source region. A diffusion region of a conductivity type, wherein a surface of a region below the gate electrode is switched to a conductive state or a non-conductive state by a voltage applied to the gate electrode; For example, the and the diffusion region LOCO
The impurity concentration on the surface of the substrate region below the gate insulating thin film between the S region and the gate insulating thin film is lower than that of the substrate region below the LOCOS region.
【０００７】請求項２のＤＭＯＳ構造を有する半導体装
置の製造方法においては、第１導電型の基板領域表面に
ＬＯＣＯＳ領域を形成し、少なくとも、前記ＬＯＣＯＳ
領域の一端側の基板領域表面の不純物濃度が前記ＬＯＣ
ＯＳ領域の下部の基板領域よりも薄くなるように、第２
導電型の不純物を添加し、前記基板領域の上にゲート絶
縁膜を介して、その一部が前記ＬＯＣＯＳ領域上に位置
するようにゲート電極を形成し、前記ＬＯＣＯＳ領域お
よびドレイン形成予定領域をレジストで覆い、第２導電
型の不純物を添加し、前記第２導電型の不純物を添加し
た領域を拡散させて、拡散領域が前記ゲート電極の下部
まで及んだ第２導電型拡散領域を形成し、前記第２導電
型拡散領域内のソース形成予定領域およびこのソース形
成予定領域とは前記ＬＯＣＯＳ領域を挟んだ逆側の前記
基板領域の表面のドレイン形成予定領域を除いてレジス
トで覆い、このレジストおよび前記ゲート電極をマスク
として、第１導電型の不純物を添加すること、を特徴と
する。According to a second aspect of the present invention, in a method of manufacturing a semiconductor device having a DMOS structure, a LOCOS region is formed on a surface of a substrate region of a first conductivity type, and at least the LOCOS region is formed.
The impurity concentration on the surface of the substrate region at one end of the region is
The second region is thinner than the substrate region below the OS region.
A conductive type impurity is added, and a gate electrode is formed on the substrate region via a gate insulating film so that a part of the gate electrode is located on the LOCOS region. And adding a second conductivity type impurity, and diffusing the region doped with the second conductivity type impurity to form a second conductivity type diffusion region in which the diffusion region extends below the gate electrode. A region for forming a source in the diffusion region of the second conductivity type and a region other than the region for forming a drain on the surface of the substrate region on the opposite side of the LOCOS region with respect to the source forming region; And using the gate electrode as a mask, adding a first conductivity type impurity.
【０００８】[0008]
【発明の効果】請求項１のＤＭＯＳ構造を有する半導体
装置においては、前記拡散領域と前記ＬＯＣＯＳ領域と
の間のゲート絶縁薄膜の下部の基板領域表面の不純物濃
度が前記ＬＯＣＯＳ領域の下部の基板領域よりも薄い。
したがって、前記すきま部分に電界が集中することがな
く、高耐圧となる。また、ＤＭＯＳ構造を有するので、
チャネル長の決定を正確にできる。In the semiconductor device having the DMOS structure according to the first aspect, the impurity concentration on the surface of the substrate region below the gate insulating thin film between the diffusion region and the LOCOS region is lower than the substrate region below the LOCOS region. Thinner than.
Therefore, the electric field does not concentrate on the clearance, and the breakdown voltage is high. Also, because it has a DMOS structure,
The channel length can be determined accurately.
【０００９】請求項２のＤＭＯＳ構造を有する半導体装
置の製造方法においては、前記第２導電型拡散領域内の
ソース形成予定領域およびこのソース形成予定領域とは
前記ＬＯＣＯＳ領域を挟んだ逆側の前記基板領域の表面
のドレイン形成予定領域を除いてレジストで覆い、この
レジストおよび前記ゲート電極をマスクとして、第１導
電型の不純物を添加する。したがって、前記すきま部分
の下部の基板領域の不純物濃度が低くなり、電界集中を
防ぐことができる。これにより高耐圧の半導体装置を製
造することができる。また、ＤＭＯＳ構造を有するの
で、チャネル長の決定を正確にできる。According to a second aspect of the present invention, in the method of manufacturing a semiconductor device having a DMOS structure, a source formation region in the second conductivity type diffusion region and the source formation region on the opposite side of the LOCOS region with respect to the source formation region. Except for a region where a drain is to be formed on the surface of the substrate region, the surface is covered with a resist, and a first conductivity type impurity is added using the resist and the gate electrode as a mask. Therefore, the impurity concentration in the substrate region below the gap becomes low, and electric field concentration can be prevented. As a result, a semiconductor device having a high breakdown voltage can be manufactured. In addition, since it has a DMOS structure, the channel length can be determined accurately.
【００１０】[0010]
【発明の実施の形態】本発明の一実施例を図面に基づい
て説明する。図１に、本発明にかかるＤＭＯＳ構造を有
する半導体装置１の要部断面図を示す。DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing a main part of a semiconductor device 1 having a DMOS structure according to the present invention.
【００１１】第１導電型のＮー型基板２の表面に、ＬＯ
ＣＯＳ領域１１が形成されており、その両側にドレイン
領域３およびソース領域４が形成されている。ＬＯＣＯ
Ｓ領域１１の下部の基板領域は、ドリフトドレイン領域
３ａとして機能する。The LO of the first conductivity type N - type substrate 2 is
A COS region 11 is formed, and a drain region 3 and a source region 4 are formed on both sides thereof. LOCO
The substrate region below S region 11 functions as drift drain region 3a.
【００１２】ソース領域４は第２導電型のＰ型拡散層７
で覆われている。Ｐ型拡散層７のソース領域４とＬＯＣ
ＯＳ領域１１の間の表面は、ゲート電極１７に所定の電
圧を印加することにより、チャネルが形成されるチャネ
ル領域として機能する。The source region 4 is a P-type diffusion layer 7 of the second conductivity type.
Covered with. Source region 4 of P-type diffusion layer 7 and LOC
The surface between the OS regions 11 functions as a channel region where a channel is formed by applying a predetermined voltage to the gate electrode 17.
【００１３】ゲート電極１７は、ゲート絶縁膜２１を介
して基板２の表面上に形成されている。ゲート電極１７
はその一部がＬＯＣＯＳ領域１１の上に被さっている。
ゲート電極１７は、ＰＳＧ膜２２で覆われている。ＰＳ
Ｇ膜２２には開口部が設けられ、ドレイン電極２３、ソ
ース電極２４が形成されている。The gate electrode 17 is formed on the surface of the substrate 2 via the gate insulating film 21. Gate electrode 17
Is partially covered on the LOCOS region 11.
The gate electrode 17 is covered with the PSG film 22. PS
An opening is provided in the G film 22, and a drain electrode 23 and a source electrode 24 are formed.
【００１４】ＬＯＣＯＳ領域１１のバーズビーク部の端
部とＰ型拡散層７の端部との間にすきま領域１５が形成
されている。このすきま領域１５の表面近傍の不純物濃
度は基板２の不純物濃度よりも薄く形成されている。こ
のように、すきま領域１５の部分の不純物濃度を低くす
ることにより、この部分における電界の集中を防止し、
これにより、高耐圧の半導体装置を提供することができ
る。A gap region 15 is formed between the end of the bird's beak of the LOCOS region 11 and the end of the P-type diffusion layer 7. The impurity concentration near the surface of the clearance region 15 is formed to be lower than the impurity concentration of the substrate 2. As described above, by lowering the impurity concentration in the portion of the clearance region 15, concentration of the electric field in this portion is prevented,
Thus, a semiconductor device with a high withstand voltage can be provided.
【００１５】つぎに、ＤＭＯＳ構造を有する半導体装置
１の製造方法について説明する。Ｎ型不純物濃度１×１
０15〜１×１０16／cm3程度の基板２の表面に、図２Ａ
に示すようにＬＯＣＯＳ領域１１を形成する。Next, a method of manufacturing the semiconductor device 1 having a DMOS structure will be described. N-type impurity concentration 1 × 1
2A on the surface of the substrate 2 of about 0 15 to 1 × 10 16 / cm 3 .
The LOCOS region 11 is formed as shown in FIG.
【００１６】つぎに、図２Ｂに示すようにレジスト３１
を形成し、Ｐ型の不純物をイオン注入する。本実施形態
においては、不純物注入後の不純物濃度が、８×１０14
〜８×１０15／cm3程度となるように、Ｐ型不純物であ
るボロンを注入した。Next, as shown in FIG.
Is formed, and P-type impurities are ion-implanted. In this embodiment, the impurity concentration after the impurity implantation is 8 × 10 14
Boron, which is a P-type impurity, was implanted so as to be about 8 × 10 15 / cm 3 .
【００１７】つぎに、図２Ｃに示すようにレジスト３１
を除去した後、ゲート絶縁膜２１およびゲート電極１７
を形成する。その後、通常のＤＭＯＳトランジスタと同
様に、所定のレジストを用いてＰ型拡散層７を形成し、
横方向および深さ方向に拡散する。Ｎ型の不純物をイオ
ン注入して、図３Ａに示すようにドレイン領域３、ソー
ス領域４を形成する。そして、全面にＰＳＧ膜２２を形
成した後、開口部を設けドレイン電極２３、ソース電極
２４を形成する。Next, as shown in FIG.
Is removed, the gate insulating film 21 and the gate electrode 17 are removed.
To form After that, similarly to a normal DMOS transistor, a P-type diffusion layer 7 is formed using a predetermined resist,
Spread laterally and depthwise. N-type impurities are ion-implanted to form a drain region 3 and a source region 4 as shown in FIG. 3A. Then, after the PSG film 22 is formed on the entire surface, an opening is provided and a drain electrode 23 and a source electrode 24 are formed.
【００１８】なお、上記実施形態においては、ＬＯＣＯ
Ｓ領域１１の端部の基板表面にＰ型の不純物を注入する
場合に、図２Ｂに示すように、レジスト３１を形成した
が、レジスト３１を設けることなく、全面にＰ型不純物
のイオン注入を行ってもよい。In the above embodiment, the LOCO
When implanting a P-type impurity into the substrate surface at the end of the S region 11, a resist 31 was formed as shown in FIG. 2B, but without providing the resist 31, ion implantation of a P-type impurity was performed on the entire surface. May go.
【００１９】また、本実施形態においては、第１導電型
をＮ型、第２導電型をＰ型としたが、逆でもよい。In the present embodiment, the first conductivity type is N-type and the second conductivity type is P-type.
【００２０】なお、本実施形態においては、Ｎ型の基板
領域として、基板そのものを用いたが、基板内のウェル
領域を基板領域として用いてもよい。In the present embodiment, the substrate itself is used as the N-type substrate region, but a well region in the substrate may be used as the substrate region.
【００２１】また、本発明は、ＤＭＯＳトランジスタを
有する半導体装置であれば、どのような半導体装置、例
えば、ＤＭＯＳトランジスタ、ＤＭＯＳトランジスタ部
を有するＩＣ等に適用することができる。The present invention can be applied to any semiconductor device having a DMOS transistor, such as a DMOS transistor and an IC having a DMOS transistor portion.
【図１】本発明にかかるＤＭＯＳ構造を有する半導体装
置１の要部断面図である。FIG. 1 is a sectional view of a main part of a semiconductor device 1 having a DMOS structure according to the present invention.
【図２】図１に示すＤＭＯＳ構造を有する半導体装置１
の製造工程を示す図である。FIG. 2 is a semiconductor device 1 having a DMOS structure shown in FIG.
It is a figure which shows the manufacturing process of.
【図３】図１に示すＤＭＯＳ構造を有する半導体装置１
の製造工程を示す図である。FIG. 3 is a semiconductor device 1 having a DMOS structure shown in FIG.
It is a figure which shows the manufacturing process of.
【図４】従来のＤＭＯＳ構造の半導体装置の要部断面図
である。FIG. 4 is a cross-sectional view of a main part of a conventional semiconductor device having a DMOS structure.
【図５】高耐圧構造を有するＤＭＯＳ構造の半導体装置
の要部断面図である。FIG. 5 is a sectional view of a principal part of a semiconductor device having a DMOS structure having a high breakdown voltage structure.
【図６】図５に示すＤＭＯＳトランジスタ７１のチャネ
ル領域１６近傍の状態を説明する図である。6 is a diagram illustrating a state near the channel region 16 of the DMOS transistor 71 shown in FIG.
２ 基板 ３ ドレイン領域 ４ ソース領域 ７ Ｐ型拡散層 １１ ＬＯＣＯＳ領域 １５ すきま領域 １７ ゲート電極 ２１ ゲート絶縁膜 2 Substrate 3 Drain region 4 Source region 7 P-type diffusion layer 11 LOCOS region 15 Clearance region 17 Gate electrode 21 Gate insulating film
Claims (2)
ート電極であって、その一部が前記ＬＯＣＯＳ領域上に
位置するように形成されたゲート電極、 前記ゲート電極の前記ＬＯＣＯＳ領域とは逆側の前記基
板領域表面に形成された第１導電型のソース領域、 前記ＬＯＣＯＳ領域を挟んで前記ソース領域と逆側の前
記基板領域表面に形成された第１導電型のドレイン領
域、 前記ソース領域を覆うように形成された第２導電型の拡
散領域であって、前記ゲート電極に印加される電圧によ
り前記ゲート電極の下部の領域の表面が導通状態または
非導通状態に切換えられる拡散領域、 を備え、 前記拡散領域と前記ＬＯＣＯＳ領域との間のゲート絶縁
薄膜の下部の基板領域表面の不純物濃度が前記ＬＯＣＯ
Ｓ領域の下部の基板領域よりも薄いこと、 を特徴とするＤＭＯＳ構造を有する半導体装置。A first conductive type substrate region, a LOCOS region formed on a surface of the substrate region, and a gate electrode formed on the substrate region via a gate insulating film, and a part of the gate electrode is formed. A gate electrode formed so as to be located on a LOCOS region; a first conductivity type source region formed on a surface of the substrate region opposite to the LOCOS region of the gate electrode; and the source sandwiching the LOCOS region. A first conductive type drain region formed on the surface of the substrate region opposite to the region, a second conductive type diffusion region formed to cover the source region, and a voltage applied to the gate electrode. A diffusion region in which a surface of a region below the gate electrode is switched between a conductive state and a non-conductive state by the following: a region under the gate insulating thin film between the diffusion region and the LOCOS region. The impurity concentration on the surface of the substrate region
A semiconductor device having a DMOS structure, which is thinner than a substrate region below an S region.
域を形成し、 少なくとも、前記ＬＯＣＯＳ領域の一端側の基板領域表
面の不純物濃度が前記ＬＯＣＯＳ領域の下部の基板領域
よりも薄くなるように、第２導電型の不純物を添加し、 前記基板領域の上にゲート絶縁膜を介して、その一部が
前記ＬＯＣＯＳ領域上に位置するようにゲート電極を形
成し、 前記ＬＯＣＯＳ領域およびドレイン形成予定領域をレジ
ストで覆い、第２導電型の不純物を添加し、 前記第２導電型の不純物を添加した領域を拡散させて、
拡散領域が前記ゲート電極の下部まで及んだ第２導電型
拡散領域を形成し、 前記第２導電型拡散領域内のソース形成予定領域および
このソース形成予定領域とは前記ＬＯＣＯＳ領域を挟ん
だ逆側の前記基板領域の表面のドレイン形成予定領域を
除いてレジストで覆い、このレジストおよび前記ゲート
電極をマスクとして、第１導電型の不純物を添加するこ
と、 を特徴とするＤＭＯＳ構造を有する半導体装置の製造方
法。2. A LOCOS region is formed on a surface of a substrate region of a first conductivity type, and at least an impurity concentration on a surface of a substrate region on one end side of the LOCOS region is lower than that of a substrate region below the LOCOS region. Adding a second conductivity type impurity, forming a gate electrode on the substrate region via a gate insulating film such that a part thereof is located on the LOCOS region, and forming the LOCOS region and the drain Covering the region with a resist, adding a second conductivity type impurity, and diffusing the second conductivity type added region,
Forming a second conductivity type diffusion region in which the diffusion region extends to below the gate electrode; and a source formation planned region in the second conductivity type diffusion region and a reverse of the LOCOS region with respect to the source formation planned region. A semiconductor device having a DMOS structure, wherein the semiconductor device is covered with a resist except for a region where a drain is to be formed on the surface of the substrate region on the side of the substrate, and an impurity of a first conductivity type is added using the resist and the gate electrode as a mask. Manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05600297A JP3625603B2 (en) | 1997-03-11 | 1997-03-11 | Semiconductor device having DMOS structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05600297A JP3625603B2 (en) | 1997-03-11 | 1997-03-11 | Semiconductor device having DMOS structure and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10256534A true JPH10256534A (en) | 1998-09-25 |
| JP3625603B2 JP3625603B2 (en) | 2005-03-02 |
Family
ID=13014872
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP05600297A Expired - Lifetime JP3625603B2 (en) | 1997-03-11 | 1997-03-11 | Semiconductor device having DMOS structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3625603B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006128668A (en) * | 2004-10-27 | 2006-05-18 | Samsung Electronics Co Ltd | High voltage transistor and methods of manufacturing the same |
| JP2006245517A (en) * | 2005-03-07 | 2006-09-14 | Oki Electric Ind Co Ltd | Semiconductor device and manufacturing method thereof |
| CN100459073C (en) * | 2005-02-23 | 2009-02-04 | 旺宏电子股份有限公司 | LDMOS device and method of fabrication of LDMOS device |
| US8507982B2 (en) | 2010-03-11 | 2013-08-13 | Panasonic Corporation | Semiconductor device and method for fabricating the same |
-
1997
- 1997-03-11 JP JP05600297A patent/JP3625603B2/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006128668A (en) * | 2004-10-27 | 2006-05-18 | Samsung Electronics Co Ltd | High voltage transistor and methods of manufacturing the same |
| JP2012119718A (en) * | 2004-10-27 | 2012-06-21 | Samsung Electronics Co Ltd | High breakdown voltage transistor and method of manufacturing the same |
| CN100459073C (en) * | 2005-02-23 | 2009-02-04 | 旺宏电子股份有限公司 | LDMOS device and method of fabrication of LDMOS device |
| JP2006245517A (en) * | 2005-03-07 | 2006-09-14 | Oki Electric Ind Co Ltd | Semiconductor device and manufacturing method thereof |
| US8507982B2 (en) | 2010-03-11 | 2013-08-13 | Panasonic Corporation | Semiconductor device and method for fabricating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3625603B2 (en) | 2005-03-02 |
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