JP3625603B2 - Semiconductor device having DMOS structure and manufacturing method thereof - Google Patents

Semiconductor device having DMOS structure and manufacturing method thereof Download PDF

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JP3625603B2
JP3625603B2 JP05600297A JP5600297A JP3625603B2 JP 3625603 B2 JP3625603 B2 JP 3625603B2 JP 05600297 A JP05600297 A JP 05600297A JP 5600297 A JP5600297 A JP 5600297A JP 3625603 B2 JP3625603 B2 JP 3625603B2
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locos
conductivity type
gate electrode
substrate
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JPH10256534A (en
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一文 島内
晴之 高田
靖史 濱澤
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Rohm Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

【０００１】
【発明の属する技術分野】
この発明は、ＤＭＯＳ構造を有する半導体装置に関するものであり、特に、耐圧向上に関する。
【０００２】
【従来技術】
従来、図４に示すようなＤＭＯＳトランジスタが知られている。ＤＭＯＳトランジスタ６１は、ソース領域４を取囲むように、ｐ型拡散領域を設けた二重拡散型の半導体装置である。ＤＭＯＳトランジスタ６１は、チャネル領域１６の横方向の拡散を制御することによって、チャネル長の決定を行なう。したがって、その決定が容易となる。
【０００３】
かかるＤＭＯＳトランジスタについて、高耐圧の半導体装置を提供するために、発明者は、図５に示すようなＬＯＣＯＳ領域の下にドリフトドレイン領域を形成した半導体装置を考えた。ＤＭＯＳトランジスタ７１は、ドレイン領域３とソース領域４の間にＬＯＣＯＳ領域１１が形成されており、ゲート電極１７がＬＯＣＯＳ領域１１の一部に覆うように形成されている。これにより、ＬＯＣＯＳ領域１１の下部の基板表面領域をドリフトドレイン領域として用いることができる。また、ＬＯＣＯＳ領域を有するので、ドリフトドレイン領域とゲート電極１７との間の耐圧も向上する。
【０００４】
【発明が解決しようとする課題】
しかしながら、ＤＭＯＳトランジスタ７１においては、以下の様な問題があった。ＤＭＯＳトランジスタ７１においては、ゲート電極１７が矢印α方向にマスクずれを起こした場合に、ゲート電極１７とともにＰ型拡散層７も矢印α方向にずれる。これにより、ゲート電極１７の下のゲート絶縁膜に位置するＰ型拡散層７がＬＯＣＯＳ領域１１の端部のバーズビーク部の下側に入り、ゲート電極１７に対してチャネル長が短くなる。このため、ゲート電極１７の位置がずれた場合でも、チャネル長を一定とする為に、図６に示すように、ＬＯＣＯＳ領域１１の端部のバーズビーク部から幅ｗ１だけすきま領域１５を設けて、Ｐ型拡散層７を形成することも考えられる。しかし、このようなすきま領域１５を設けると、電界集中により絶縁破壊をおこすおそれがある。
【０００５】
本発明は、上記の様な問題を解決し、ＤＭＯＳ構造を有する半導体装置において、チャネル長の決定を正確にできると共に、耐圧を向上させた半導体装置を提供することを目的とする。
【０００６】
【課題を解決するための手段】
請求項１のＤＭＯＳ構造を有する半導体装置においては、第１導電型の基板領域、前記基板領域表面に形成されたＬＯＣＯＳ領域、前記基板領域の上にゲート絶縁膜を介して形成されたゲート電極であって、その一部が前記ＬＯＣＯＳ領域上に位置するように形成されたゲート電極、前記ゲート電極の前記ＬＯＣＯＳ領域とは逆側の前記基板領域表面に形成された第１導電型のソース領域、前記ＬＯＣＯＳ領域を挟んで前記ソース領域と逆側の前記基板領域表面に形成された第１導電型のドレイン領域、前記ソース領域を覆うように形成された第２導電型の拡散領域であって、前記ゲート電極に印加される電圧により前記ゲート電極の下部の領域の表面が導通状態または非導通状態に切換えられる拡散領域、を備え、前記拡散領域と前記ＬＯＣＯＳ領域との間のゲート絶縁薄膜の下部の基板領域表面の不純物濃度が前記ＬＯＣＯＳ領域の下部の基板領域よりも薄く、かつ、前記ゲート電極に覆われたＬＯＣＯＳ領域には、前記第２導電型の不純物が注入されていること、を特徴とする。
【０００７】
請求項２のＤＭＯＳ構造を有する半導体装置の製造方法においては、
第１導電型の基板領域表面にＬＯＣＯＳ領域を形成し、
少なくとも、前記ＬＯＣＯＳ領域の一端側の基板領域表面の不純物濃度が前記ＬＯＣＯＳ領域の下部の基板領域よりも薄くなるように、第２導電型の不純物を添加し、
前記基板領域の上にゲート絶縁膜を介して、その一部が前記ＬＯＣＯＳ領域上に位置するようにゲート電極を形成し、
前記ＬＯＣＯＳ領域およびドレイン形成予定領域をレジストで覆い、第２導電型の不純物を添加し、
前記第２導電型の不純物を添加した領域を拡散させて、拡散領域が前記ゲート電極の下部まで及んだ第２導電型拡散領域を形成し、
前記第２導電型拡散領域内のソース形成予定領域およびこのソース形成予定領域とは前記ＬＯＣＯＳ領域を挟んだ逆側の前記基板領域の表面のドレイン形成予定領域を除いてレジストで覆い、このレジストおよび前記ゲート電極をマスクとして、第１導電型の不純物を添加すること、
を特徴とする。
【０００８】
【発明の効果】
請求項１のＤＭＯＳ構造を有する半導体装置においては、前記拡散領域と前記ＬＯＣＯＳ領域との間のゲート絶縁薄膜の下部の基板領域表面の不純物濃度が前記ＬＯＣＯＳ領域の下部の基板領域よりも薄く、かつ、前記ゲート電極に覆われたＬＯＣＯＳ領域には、前記第２導電型の不純物が注入されている。したがって、前記すきま部分に電界が集中することがなく、高耐圧となる。また、ＤＭＯＳ構造を有するので、チャネル長の決定を正確にできる。
【０００９】
請求項２のＤＭＯＳ構造を有する半導体装置の製造方法においては、前記第２導電型拡散領域内のソース形成予定領域およびこのソース形成予定領域とは前記ＬＯＣＯＳ領域を挟んだ逆側の前記基板領域の表面のドレイン形成予定領域を除いてレジストで覆い、このレジストおよび前記ゲート電極をマスクとして、第１導電型の不純物を添加する。したがって、前記すきま部分の下部の基板領域の不純物濃度が低くなり、電界集中を防ぐことができる。これにより高耐圧の半導体装置を製造することができる。また、ＤＭＯＳ構造を有するので、チャネル長の決定を正確にできる。
【００１０】
【発明の実施の形態】
本発明の一実施例を図面に基づいて説明する。図１に、本発明にかかるＤＭＯＳ構造を有する半導体装置１の要部断面図を示す。
【００１１】
第１導電型のＮー型基板２の表面に、ＬＯＣＯＳ領域１１が形成されており、その両側にドレイン領域３およびソース領域４が形成されている。ＬＯＣＯＳ領域１１の下部の基板領域は、ドリフトドレイン領域３ａとして機能する。
【００１２】
ソース領域４は第２導電型のＰ型拡散層７で覆われている。Ｐ型拡散層７のソース領域４とＬＯＣＯＳ領域１１の間の表面は、ゲート電極１７に所定の電圧を印加することにより、チャネルが形成されるチャネル領域として機能する。
【００１３】
ゲート電極１７は、ゲート絶縁膜２１を介して基板２の表面上に形成されている。ゲート電極１７はその一部がＬＯＣＯＳ領域１１の上に被さっている。ゲート電極１７は、ＰＳＧ膜２２で覆われている。ＰＳＧ膜２２には開口部が設けられ、ドレイン電極２３、ソース電極２４が形成されている。
【００１４】
ＬＯＣＯＳ領域１１のバーズビーク部の端部とＰ型拡散層７の端部との間にすきま領域１５が形成されている。このすきま領域１５の表面近傍の不純物濃度は基板２の不純物濃度よりも薄く形成されている。このように、すきま領域１５の部分の不純物濃度を低くすることにより、この部分における電界の集中を防止し、これにより、高耐圧の半導体装置を提供することができる。
【００１５】
つぎに、ＤＭＯＳ構造を有する半導体装置１の製造方法について説明する。Ｎ型不純物濃度１×１０１５〜１×１０１６／ｃｍ３程度の基板２の表面に、図２Ａに示すようにＬＯＣＯＳ領域１１を形成する。
【００１６】
つぎに、図２Ｂに示すようにレジスト３１を形成し、Ｐ型の不純物をイオン注入する。本実施形態においては、不純物注入後の不純物濃度が、８×１０１４〜８×１０１５／ｃｍ３程度となるように、Ｐ型不純物であるボロンを注入した。
【００１７】
つぎに、図２Ｃに示すようにレジスト３１を除去した後、ゲート絶縁膜２１およびゲート電極１７を形成する。その後、通常のＤＭＯＳトランジスタと同様に、所定のレジストを用いてＰ型拡散層７を形成し、横方向および深さ方向に拡散する。Ｎ型の不純物をイオン注入して、図３Ａに示すようにドレイン領域３、ソース領域４を形成する。そして、全面にＰＳＧ膜２２を形成した後、開口部を設けドレイン電極２３、ソース電極２４を形成する。
【００１８】
なお、上記実施形態においては、ＬＯＣＯＳ領域１１の端部の基板表面にＰ型の不純物を注入する場合に、図２Ｂに示すように、レジスト３１を形成したが、レジスト３１を設けることなく、全面にＰ型不純物のイオン注入を行ってもよい。
【００１９】
また、本実施形態においては、第１導電型をＮ型、第２導電型をＰ型としたが、逆でもよい。
【００２０】
なお、本実施形態においては、Ｎ型の基板領域として、基板そのものを用いたが、基板内のウェル領域を基板領域として用いてもよい。
【００２１】
また、本発明は、ＤＭＯＳトランジスタを有する半導体装置であれば、どのような半導体装置、例えば、ＤＭＯＳトランジスタ、ＤＭＯＳトランジスタ部を有するＩＣ等に適用することができる。
【図面の簡単な説明】
【図１】本発明にかかるＤＭＯＳ構造を有する半導体装置１の要部断面図である。
【図２】図１に示すＤＭＯＳ構造を有する半導体装置１の製造工程を示す図である。
【図３】図１に示すＤＭＯＳ構造を有する半導体装置１の製造工程を示す図である。
【図４】従来のＤＭＯＳ構造の半導体装置の要部断面図である。
【図５】高耐圧構造を有するＤＭＯＳ構造の半導体装置の要部断面図である。
【図６】図５に示すＤＭＯＳトランジスタ７１のチャネル領域１６近傍の状態を説明する図である。
【符号の説明】
２ 基板
３ ドレイン領域
４ ソース領域
７ Ｐ型拡散層
１１ ＬＯＣＯＳ領域
１５ すきま領域
１７ ゲート電極
２１ ゲート絶縁膜[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a DMOS structure, and more particularly to an improvement in breakdown voltage.
[0002]
[Prior art]
Conventionally, a DMOS transistor as shown in FIG. 4 is known. The DMOS transistor 61 is a double diffusion type semiconductor device in which a p-type diffusion region is provided so as to surround the source region 4. The DMOS transistor 61 determines the channel length by controlling the lateral diffusion of the channel region 16. Therefore, the determination becomes easy.
[0003]
In order to provide a high breakdown voltage semiconductor device for such a DMOS transistor, the inventor has considered a semiconductor device in which a drift drain region is formed under a LOCOS region as shown in FIG. In the DMOS transistor 71, a LOCOS region 11 is formed between the drain region 3 and the source region 4, and the gate electrode 17 is formed so as to cover a part of the LOCOS region 11. Thereby, the substrate surface region below the LOCOS region 11 can be used as the drift drain region. Moreover, since the LOCOS region is provided, the breakdown voltage between the drift drain region and the gate electrode 17 is also improved.
[0004]
[Problems to be solved by the invention]
However, the DMOS transistor 71 has the following problems. In the DMOS transistor 71, when the gate electrode 17 causes a mask shift in the arrow α direction, the P-type diffusion layer 7 is also shifted in the arrow α direction together with the gate electrode 17. As a result, the P-type diffusion layer 7 located in the gate insulating film under the gate electrode 17 enters under the bird's beak at the end of the LOCOS region 11, and the channel length is shortened with respect to the gate electrode 17. Therefore, even when the position of the gate electrode 17 is shifted, in order to make the channel length constant, as shown in FIG. 6, a gap region 15 is provided by a width w1 from the bird's beak portion at the end of the LOCOS region 11, Forming the P-type diffusion layer 7 is also conceivable. However, if such a clearance region 15 is provided, there is a risk of causing dielectric breakdown due to electric field concentration.
[0005]
An object of the present invention is to solve the above problems and to provide a semiconductor device having a DMOS structure in which the channel length can be accurately determined and the breakdown voltage is improved.
[0006]
[Means for Solving the Problems]
The semiconductor device having a DMOS structure according to claim 1 includes a first conductivity type substrate region, a LOCOS region formed on a surface of the substrate region, and a gate electrode formed on the substrate region via a gate insulating film. A gate electrode formed so that a part thereof is positioned on the LOCOS region, a source region of a first conductivity type formed on the surface of the substrate region opposite to the LOCOS region of the gate electrode, A drain region of a first conductivity type formed on the surface of the substrate region opposite to the source region across the LOCOS region; a diffusion region of a second conductivity type formed so as to cover the source region; A diffusion region in which a surface of a region under the gate electrode is switched to a conductive state or a non-conductive state by a voltage applied to the gate electrode, and the diffusion region and the LO The impurity concentration of the surface of the substrate region under the gate insulating film between the OS area is rather thin than the substrate area of the lower portion of the LOCOS region, and the LOCOS region covered with the gate electrode, the second conductive A type impurity is implanted .
[0007]
In a method of manufacturing a semiconductor device having a DMOS structure according to claim 2,
Forming a LOCOS region on the surface of the substrate region of the first conductivity type;
Adding an impurity of the second conductivity type so that at least the impurity concentration of the surface of the substrate region on one end side of the LOCOS region is thinner than the substrate region below the LOCOS region;
Forming a gate electrode on the substrate region via a gate insulating film so that a part thereof is located on the LOCOS region;
Covering the LOCOS region and the drain formation scheduled region with a resist, adding an impurity of the second conductivity type,
Diffusing the region doped with the second conductivity type impurity to form a second conductivity type diffusion region where the diffusion region extends to the lower portion of the gate electrode;
A source formation planned region in the second conductivity type diffusion region and this source formation planned region are covered with a resist except for a drain formation planned region on the surface of the substrate region opposite to the LOCOS region. Adding a first conductivity type impurity using the gate electrode as a mask;
It is characterized by.
[0008]
【The invention's effect】
The semiconductor device having a DMOS structure according to claim 1, wherein an impurity concentration of a substrate region surface below the gate insulating thin film between the diffusion region and the LOCOS region is thinner than a substrate region below the LOCOS region , and The impurity of the second conductivity type is implanted into the LOCOS region covered with the gate electrode . Therefore, the electric field does not concentrate in the gap portion, and a high breakdown voltage is obtained. In addition, since the DMOS structure is used, the channel length can be determined accurately.
[0009]
3. The method of manufacturing a semiconductor device having a DMOS structure according to claim 2, wherein the source formation scheduled region in the second conductivity type diffusion region and the source formation scheduled region are opposite to the substrate region on the opposite side of the LOCOS region. Except for the region where the drain is to be formed on the surface, it is covered with a resist, and an impurity of the first conductivity type is added using this resist and the gate electrode as a mask. Therefore, the impurity concentration in the substrate region below the gap is reduced, and electric field concentration can be prevented. Thereby, a high breakdown voltage semiconductor device can be manufactured. In addition, since the DMOS structure is used, the channel length can be determined accurately.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a cross-sectional view of a main part of a semiconductor device 1 having a DMOS structure according to the present invention.
[0011]
A LOCOS region 11 is formed on the surface of the N - type substrate 2 of the first conductivity type, and a drain region 3 and a source region 4 are formed on both sides thereof. The substrate region below the LOCOS region 11 functions as the drift drain region 3a.
[0012]
The source region 4 is covered with a P-type diffusion layer 7 of the second conductivity type. The surface between the source region 4 and the LOCOS region 11 of the P-type diffusion layer 7 functions as a channel region where a channel is formed by applying a predetermined voltage to the gate electrode 17.
[0013]
The gate electrode 17 is formed on the surface of the substrate 2 via the gate insulating film 21. A part of the gate electrode 17 covers the LOCOS region 11. The gate electrode 17 is covered with the PSG film 22. The PSG film 22 has an opening, and a drain electrode 23 and a source electrode 24 are formed.
[0014]
A gap region 15 is formed between the end portion of the bird's beak portion of the LOCOS region 11 and the end portion of the P-type diffusion layer 7. The impurity concentration in the vicinity of the surface of the gap region 15 is formed thinner than the impurity concentration of the substrate 2. In this way, by reducing the impurity concentration in the gap region 15, the concentration of the electric field in this portion can be prevented, thereby providing a high breakdown voltage semiconductor device.
[0015]
Next, a method for manufacturing the semiconductor device 1 having the DMOS structure will be described. A LOCOS region 11 is formed on the surface of the substrate 2 having an N-type impurity concentration of about 1 × 10 15 to 1 × 10 16 / cm 3 as shown in FIG. 2A.
[0016]
Next, as shown in FIG. 2B, a resist 31 is formed, and P-type impurities are ion-implanted. In this embodiment, boron, which is a P-type impurity, is implanted so that the impurity concentration after the impurity implantation is about 8 × 10 14 to 8 × 10 15 / cm 3 .
[0017]
Next, as shown in FIG. 2C, after removing the resist 31, the gate insulating film 21 and the gate electrode 17 are formed. Thereafter, like a normal DMOS transistor, a P-type diffusion layer 7 is formed using a predetermined resist and diffused in the lateral direction and the depth direction. N-type impurities are ion-implanted to form the drain region 3 and the source region 4 as shown in FIG. 3A. Then, after the PSG film 22 is formed on the entire surface, an opening is provided and a drain electrode 23 and a source electrode 24 are formed.
[0018]
In the above embodiment, when the P-type impurity is implanted into the substrate surface at the end of the LOCOS region 11, the resist 31 is formed as shown in FIG. 2B. Alternatively, ion implantation of P-type impurities may be performed.
[0019]
In the present embodiment, the first conductivity type is N-type and the second conductivity type is P-type.
[0020]
In this embodiment, the substrate itself is used as the N-type substrate region, but a well region in the substrate may be used as the substrate region.
[0021]
The present invention can be applied to any semiconductor device having a DMOS transistor, for example, a DMOS transistor, an IC having a DMOS transistor portion, or the like.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a main part of a semiconductor device 1 having a DMOS structure according to the present invention.
2 is a diagram showing a manufacturing process of the semiconductor device 1 having the DMOS structure shown in FIG. 1;
3 is a diagram showing a manufacturing process of the semiconductor device 1 having the DMOS structure shown in FIG. 1; FIG.
FIG. 4 is a cross-sectional view of a main part of a conventional semiconductor device having a DMOS structure.
FIG. 5 is a fragmentary cross-sectional view of a DMOS structure semiconductor device having a high breakdown voltage structure;
6 is a diagram illustrating a state in the vicinity of channel region 16 of DMOS transistor 71 shown in FIG.
[Explanation of symbols]
2 Substrate 3 Drain region 4 Source region 7 P-type diffusion layer 11 LOCOS region 15 Crevice region 17 Gate electrode 21 Gate insulating film

Claims (2)

第１導電型の基板領域、
前記基板領域表面に形成されたＬＯＣＯＳ領域、
前記基板領域の上にゲート絶縁膜を介して形成されたゲート電極であって、その一部が前記ＬＯＣＯＳ領域上に位置するように形成されたゲート電極、
前記ゲート電極の前記ＬＯＣＯＳ領域とは逆側の前記基板領域表面に形成された第１導電型のソース領域、
前記ＬＯＣＯＳ領域を挟んで前記ソース領域と逆側の前記基板領域表面に形成された第１導電型のドレイン領域、
前記ソース領域を覆うように形成された第２導電型の拡散領域であって、前記ゲート電極に印加される電圧により前記ゲート電極の下部の領域の表面が導通状態または非導通状態に切換えられる拡散領域、
を備え、
前記拡散領域と前記ＬＯＣＯＳ領域との間のゲート絶縁薄膜の下部の基板領域表面の不純物濃度が前記ＬＯＣＯＳ領域の下部の基板領域よりも薄く、かつ、前記ゲート電極に覆われたＬＯＣＯＳ領域には、前記第２導電型の不純物が注入されていること、
を特徴とするＤＭＯＳ構造を有する半導体装置。A substrate region of a first conductivity type;
A LOCOS region formed on the surface of the substrate region;
A gate electrode formed on the substrate region via a gate insulating film, a gate electrode formed so that a part thereof is positioned on the LOCOS region;
A source region of a first conductivity type formed on the surface of the substrate region opposite to the LOCOS region of the gate electrode;
A drain region of a first conductivity type formed on the surface of the substrate region opposite to the source region across the LOCOS region;
A diffusion region of a second conductivity type formed so as to cover the source region, wherein the surface of the region under the gate electrode is switched to a conductive state or a non-conductive state by a voltage applied to the gate electrode region,
With
In the LOCOS region covered with the gate electrode, the impurity concentration of the surface of the substrate region below the gate insulating thin film between the diffusion region and the LOCOS region is lower than the substrate region below the LOCOS region. The second conductivity type impurity is implanted ;
A semiconductor device having a DMOS structure. 第１導電型の基板領域表面にＬＯＣＯＳ領域を形成し、
少なくとも、前記ＬＯＣＯＳ領域の一端側の基板領域表面の不純物濃度が前記ＬＯＣＯＳ領域の下部の基板領域よりも薄くなるように、第２導電型の不純物を添加し、
前記基板領域の上にゲート絶縁膜を介して、その一部が前記ＬＯＣＯＳ領域上に位置するようにゲート電極を形成し、
前記ＬＯＣＯＳ領域およびドレイン形成予定領域をレジストで覆い、第２導電型の不純物を添加し、
前記第２導電型の不純物を添加した領域を拡散させて、拡散領域が前記ゲート電極の下部まで及んだ第２導電型拡散領域を形成し、
前記第２導電型拡散領域内のソース形成予定領域およびこのソース形成予定領域とは前記ＬＯＣＯＳ領域を挟んだ逆側の前記基板領域の表面のドレイン形成予定領域を除いてレジストで覆い、このレジストおよび前記ゲート電極をマスクとして、第１導電型の不純物を添加すること、
を特徴とするＤＭＯＳ構造を有する半導体装置の製造方法。Forming a LOCOS region on the surface of the substrate region of the first conductivity type;
Adding an impurity of the second conductivity type so that at least the impurity concentration of the surface of the substrate region on one end side of the LOCOS region is thinner than the substrate region below the LOCOS region;
Forming a gate electrode on the substrate region via a gate insulating film so that a part thereof is located on the LOCOS region;
Covering the LOCOS region and the drain formation scheduled region with a resist, adding an impurity of the second conductivity type,
Diffusing the region doped with the second conductivity type impurity to form a second conductivity type diffusion region where the diffusion region extends to the lower portion of the gate electrode;
A source formation planned region in the second conductivity type diffusion region and this source formation planned region are covered with a resist except for a drain formation planned region on the surface of the substrate region opposite to the LOCOS region. Adding a first conductivity type impurity using the gate electrode as a mask;
A method of manufacturing a semiconductor device having a DMOS structure.
JP05600297A 1997-03-11 1997-03-11 Semiconductor device having DMOS structure and manufacturing method thereof Expired - Lifetime JP3625603B2 (en)

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