KR0165348B1 - Method for manufacturing mos transistor - Google Patents
Method for manufacturing mos transistor Download PDFInfo
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- KR0165348B1 KR0165348B1 KR1019950047458A KR19950047458A KR0165348B1 KR 0165348 B1 KR0165348 B1 KR 0165348B1 KR 1019950047458 A KR1019950047458 A KR 1019950047458A KR 19950047458 A KR19950047458 A KR 19950047458A KR 0165348 B1 KR0165348 B1 KR 0165348B1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title claims description 47
- 239000012535 impurity Substances 0.000 claims abstract description 49
- 238000005498 polishing Methods 0.000 claims abstract description 5
- 150000004767 nitrides Chemical class 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims description 2
- 210000003323 beak Anatomy 0.000 claims 1
- 229920005591 polysilicon Polymers 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005755 formation reaction Methods 0.000 description 3
- 230000001788 irregular Effects 0.000 description 3
- 241000293849 Cordylanthus Species 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
Abstract
본 발명은 MOS 트랜지스터의 제조방법에 관한 것으로서, 더 상세하게는 MOS 트랜지스터의 채널길이가 짧아짐에 따라 발생하는 채널의 불순물 농도 구배의 불균일 문제를 해소할 수 있는 MOS 트랜지스터의 제조방법에 관한 것이다. 이를 위한 본 발명은, 채널이 형성되는 P형 웰(well)의 표면에 리지(ridge)형상의 LOCOS 산화막을 형성하는 단계와, 상기 P형 웰의 농도보다 높은 강도를 갖는 P형 불순물을 주입하는 단계, 및 폴리싱으로 표면을 평탄화하는 단계를 포함함으로써, 채널의 균일한 농도구배를 달성할 수 있으며, 부수적으로 소오스/드레인 영역에서의 LDD구조를 얻을 수 있는 이점을 제공한다.The present invention relates to a method of manufacturing a MOS transistor, and more particularly, to a method of manufacturing a MOS transistor that can solve the problem of non-uniformity of the impurity concentration gradient of the channel generated as the channel length of the MOS transistor is shortened. To this end, the present invention is to form a ridge-type LOCOS oxide film on the surface of the P-type well (channel) is formed, and to inject P-type impurities having a higher strength than the concentration of the P-type well By planarizing the surface by polishing and polishing, it is possible to achieve a uniform concentration gradient of the channel, and concomitantly to provide an advantage of obtaining an LDD structure in the source / drain region.
Description
제1도는 본 발명에 따른 MOS 트랜지스터의 제조방법의 제1공정 단계를 설명하기 위한 공정 단면도.1 is a cross-sectional view illustrating the first process step of the method of manufacturing a MOS transistor according to the present invention.
제2도는 본 발명의 제2공정 단계를 설명하기 위한 공정 단면도.2 is a cross-sectional view illustrating the second process step of the present invention.
제3도는 본 발명의 제3공정 단계를 설명하기 위한 공정 단면도.3 is a cross-sectional view illustrating a third process step of the present invention.
제4도는 본 발명의 제4공정 단계를 설명하기 위한 공정 단면도.4 is a cross-sectional view illustrating the fourth process step of the present invention.
제5도는 본 발명의 제5공정 단계를 설명하기 위한 공정 단면도.5 is a cross-sectional view illustrating the fifth process step of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : N형 기판 2 : P형 웰(well)1: N type substrate 2: P type well
3 : 산화막 4 : 질화막3: oxide film 4: nitride film
5 : LOCOS 산화막 6 : 산화막창5: LOCOS oxide film 6: oxide window
7 : P형 불순물층 9 : N형 불순물층7: P-type impurity layer 9: N-type impurity layer
본 발명은 MOS 트랜지스터의 제조방법에 관한 것으로서, 더 상세하게는 MOS 트랜지스터의 채널길이가 짧아짐에 따라 발생하는 채널의 불순물 농도 구배의 불균일 문제를 해소할 수 있는 MOS 트랜지스터의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a MOS transistor, and more particularly, to a method of manufacturing a MOS transistor that can solve the problem of non-uniformity of the impurity concentration gradient of the channel generated as the channel length of the MOS transistor is shortened.
현재, 반도체 제조 기술이 비약적으로 발전하고 있지만, 1㎛ 이하의 채널 길이를 가지는 MOS 트랜지스터에서는 스레쉬홀드(threshold) 전압강하, 단위폭당 펀치스루우(punchthrough) 전류증가, 서브-스레쉬홀드 스윙(swing) 증가등의 문제점이 있다. 이와 같은 현상은 트랜지스터의 채널길이가 작아짐에 따라 채널이 형성되는 P형의 표면농도가 소오스, 드레인이 형성되는 N형 고농도 확산층에 의해 영향을 받게 되어 채널 양단부분의 P형 불순물이 인접한 고농도 N형쪽으로 확산되면서 나타나게 되는 현상이다. 즉, 게이트 하단부에 존재하는 P형의 불순물이 이를 중심으로 양쪽단부에 존재하는 N형 불순물쪽으로 확산됨에 따라 상대적으로 채널의 중심부보다 양쪽 단부의 농도가 작아 불규칙한 농도 구배를 갖기 때문에 발생하는 것이다.At present, although semiconductor manufacturing technology is evolving rapidly, in a MOS transistor having a channel length of 1 μm or less, a threshold voltage drop, an increase in punchthrough current per unit width, and a sub-threshold swing ( There is a problem such as an increase in swing. As the channel length of the transistor decreases, the surface concentration of the P-type in which the channel is formed is affected by the N-type high concentration diffusion layer in which the source and the drain are formed. It is a phenomenon that appears as it spreads toward. In other words, as the P-type impurities present in the lower end of the gate diffuse toward the N-type impurities present in both ends, the concentration of both ends is relatively smaller than that of the center of the channel, resulting in an irregular concentration gradient.
상기와 같은 불규칙한 농도 구배에 의해 발생하는 문제점은 채널의 길이가 어느정도 이상일 때에는 트랜지스터의 특성에 별 문제를 야기하지 않지만, 쇼트(short) 채널을 가지는 트랜지스터에서는 상기에서 언급한 문제점을 갖게 된다.The problem caused by the irregular concentration gradient does not cause any problem in the characteristics of the transistor when the length of the channel is more than a certain degree, but in the transistor having a short channel has the problems described above.
본 발명은 상기와 같은 문제점을 해결하기 위하여 창출한 것으로서, P형 웰(well)의 표면을 LOCOS 형상방법을 이용하여 리지(ridge)형상으로 한 후, 폴리싱으로 표면을 평탄화하는 공정을 통해 쇼트 채널에서 발생되는 불규칙 농도구배를 방지하는 MOS 트랜지스터의 제조방법을 제공함에 그 목적이 있다.The present invention has been made in order to solve the above problems, the surface of the P-type wells (ridge) to form a ridge using the LOCOS shape method, and then the short channel through the process of flattening the surface by polishing It is an object of the present invention to provide a method for manufacturing a MOS transistor that prevents irregular concentration gradients generated in the system.
본 발명의 다른 목적은 채널에 주입되는 P형 불순물을 이용하여 채널 양쪽 단부의 N형 불순물을 줄여줌으로써 자체-정렬(self-align)된 LDD를 갖게 할 수 있는 MOS 트랜지스터의 제조방법을 제공하는데 있다.Another object of the present invention is to provide a method of manufacturing a MOS transistor capable of having a self-aligned LDD by reducing N-type impurities at both ends of the channel by using P-type impurities injected into the channel. .
상기 목적을 달성하기 위하여 본 발명에 따른 MOS 트랜지스터의 제조방법은,In order to achieve the above object, a method of manufacturing a MOS transistor according to the present invention,
MOS 트랜지스터의 제조방법에 있어서, N형 기판상에 P형 웰(well)을 형성한 후 채널형성부위를 지정하는 제1공정 단계와, 상기 채널형성부위 및 채널형성부위 양쪽에 산화막과 질화막을 형성하는 제2공정 단계와, 상기 산화막과 질화막이 형성된 그 사이에 소정의 두께를 갖는 2개의 산화막을 형성하는 LOCOS 형성의 제3공정 단계와, 상기 LOCOS 형성의 제3공정 단계에서 형성된 산화막 및 상기 제2공정 단계에서 형성된 산화막과 질화막을 제거하는 제4공정 단계와, 상기 제3공정 단계에서 형성되었던 산화막 형성부분 이외의 부분에 산화막창을 만든 후, P형 불순물을 이온주입하여 리지형상의 P형 불순물층을 형성하는 제5공정 단계와, 상기 제5공정 단계에서 형성된 리지형상의 P형 불순물층이 상기 채널형성부위의 중심을 기준으로 두부분으로 분할될 때까지 폴리싱(polishing)하여 평탄화하는 제6공정 단계와, 상기 제6공정 단계를 통해 얻어진 두부분으로 분할된 P형 불순물층상에 게이트용 산화막과 절연막 산화막 및 게이트용 다결정 실리콘을 적층하는 제7공정 단계와, 상기 제7공정 단계후, 소정 농도의 N형 불순물을 이온주입하고 확산시켜 소오스/드레인 전극만드는 제8공정 단계를 포함하여 상기 채널의 농도구배를 일정하게 하는 점에 그 특징이 있다.A method of manufacturing a MOS transistor, comprising: forming a P well on an N-type substrate and then designating a channel forming region, and forming an oxide film and a nitride film on both the channel forming region and the channel forming region A third process step of forming a second oxide film having a predetermined thickness between the oxide film and the nitride film formed thereon; a third process step of forming a LOCOS; and an oxide film and the first film formed in the third process step of forming a LOCOS. A fourth process step of removing the oxide film and the nitride film formed in the second process step, and an oxide film window is formed in a portion other than the oxide film forming portion formed in the third process step, followed by ion implantation of P-type impurities to form a ridge P-type. Until the fifth process step of forming the impurity layer and the ridge-shaped P-type impurity layer formed in the fifth process step are divided into two parts based on the center of the channel formation region. A sixth process step of polishing and planarization, a seventh process step of laminating a gate oxide film, an insulating film oxide film and a gate polycrystalline silicon on a P-type impurity layer divided into two parts obtained through the sixth process step; After the seventh process step, the concentration gradient of the channel is constant, including an eighth process step of ion implanting and diffusing N-type impurities of a predetermined concentration to create a source / drain electrode.
본 발명 MOS 트랜지스터의 제조방법에 있어서, 상기 제3공정 단계에서 형성된 LOCOS의 2개의 산화막은 버드스 비크(bird's beak)를 갖게 하고, 상기 제5공정 단계에서 이온주입되는 P형 불순물의 농도는 P형 웰의 불순물 농도보다 밀하도록 하는 것이 바람직하다.In the method of manufacturing the MOS transistor of the present invention, two oxide films of LOCOS formed in the third process step have a bird's beak, and the concentration of the P-type impurity implanted in the fifth process step is P It is desirable to be denser than the impurity concentration of the mold well.
또한, 본 발명 MOS 트랜지스터의 제조방법에 있어서, 상기 버드스 비크를 갖는 상기 2개의 산화막은 서로 대향되어 맞닿도록 되어 있게 하는 것이 바람직하다.Moreover, in the manufacturing method of the MOS transistor of this invention, it is preferable to make the two oxide films which have the said Buds bec mutually oppose and contact each other.
이하, 첨부된 도면을 참조하면서 본 발명에 따른 MOS 트랜지스터의 제조방법의 바람직한 일실시예를 상세하게 설명한다.Hereinafter, a preferred embodiment of a method of manufacturing a MOS transistor according to the present invention will be described in detail with reference to the accompanying drawings.
본 발명에 따른 MOS 트랜지스터의 제조방법은, MOS 트랜지스터의 채널의 농도구배를 일정하게 하기 위해 P형 불순물층을 LOCOS 형성방법으로 형성시킨 것으로서 쇼트(short) 채널에서의 펀치스루우의 전류증가, 스레쉬홀드 전압강하와 같은 문제점을 해결한 것이다.In the method for manufacturing a MOS transistor according to the present invention, a P-type impurity layer is formed by a LOCOS forming method in order to make the concentration gradient of the channel of the MOS transistor constant, and the current of punch-through in the short channel is increased and threshed. Problems such as hold voltage drop have been solved.
제1도 내지 제5도를 참조하면, 본 발명에 따른 MOS 트랜지스터의 제조방법은 다음과 같은 제조공정 단계를 포함한다.1 to 5, a method of manufacturing a MOS transistor according to the present invention includes the following manufacturing process steps.
먼저, 제1도에 도시된 바와 같이 N형 기판(1)상에 P형 웰(well;2)을 형성한다. 그 다음, 채널이 형성될 부분(C)과 그 양쪽 부분에 산화막(3)과 질화막(4)을 각각 형성한다.First, as shown in FIG. 1, a P type well 2 is formed on the N type substrate 1. Then, the oxide film 3 and the nitride film 4 are formed in the portion C and the both portions where the channel is to be formed.
상기와 같은 제조공정 후에 제2도에 도시되어 있는 바와 같이, 고온산화를 통해 버드스 비크(bird's beak)를 갖는 두터운 산화막(5)의 LOCOS 형성(local oxidation of silicon)를 2개 만드는데, 이 경우 상기 2개의 LOCOS의 산화막(5)이 서로 맞닿을 정도로 근접시키는 것이 바람직하다.As shown in FIG. 2 after the manufacturing process as described above, two LOCOS formations of the thick oxide film 5 having the bird's beak are made through high temperature oxidation, in which case Preferably, the two LOCOS oxide films 5 are brought into close contact with each other.
제2도에 도시되어 있는 바와 같이 2개의 산화막(5)를 채널형성부위(C)를 중심으로 양쪽으로 형성된 뒤에, 이를 2개의 산화막(5)과 상기 제1도에서 형성되었던 산화막(3), 질화막(4) 모두를 함께 제거한다.As shown in FIG. 2, two oxide films 5 are formed on both sides of the channel forming region C, and then two oxide films 5 and the oxide film 3 formed in FIG. All of the nitride films 4 are removed together.
LOCOS 형성때 만들어진 산화막(5)과 이들 위에 존재하는 산화막(3), 질화막(4)을 함께 제거한 후, 채널의 농도구배 조절을 위한 P형 불순물의 이온주입을 위한 산화막창(6)을 제3도와 같이 만든다. 제3도와 같이 산화막창(6)을 만든 후, 채널 농도 구배 조절용 불순물층(7)을 이온주입을 통해 실질적으로 만든다. 이때, 상기 불순물층(7)의 확산폭은 표면에서 일정하게 되어 리치(ridge) 형상의 층으로 된다. 여기서, 상기 P형 불순물은 붕소(Boron;B)로 하는 것이 바람직하다. 또한, 상기 P형 불순물의 농도는 상기 P형 웰(2)의 이온농도 보다 높은 농도로 하여야만 채널의 균일한 농도 구배를 맞출 수 있다.After removing the oxide film 5 formed at the time of LOCOS, the oxide film 3, and the nitride film 4 present thereon, the oxide film window 6 for ion implantation of P-type impurities for the concentration gradient control of the channel is removed. Make it together After the oxide film window 6 is formed as shown in FIG. 3, the impurity layer 7 for adjusting the channel concentration gradient is substantially made through ion implantation. At this time, the diffusion width of the impurity layer 7 becomes constant on the surface to form a ridge layer. Herein, the P-type impurity is preferably made of boron (B). In addition, the concentration of the P-type impurity must be higher than the ion concentration of the P-type well 2 so that the uniform concentration gradient of the channel can be matched.
제3도에 도시되어 있는 바와 같이 해서, 리지 형상의 P형 불순물층(7)을 형성한 다음, 채널형성부위(C)의 중심을 기준으로 상기 불순물층(7)이 2분할되도록 폴리싱하여 평탄화한다. 상기와 같이 폴리싱을 하면 제4도에 도시되어 있는 바와 같이 P형 불순물층이 도랑 형상의 두개의 불순물층(7a)(7b)으로 되는데, 이와 같은 두개의 불순물층은 채널의 균일한 농도구배를 위한 확산층 역할을 하게 된다.As shown in FIG. 3, the ridge-shaped P-type impurity layer 7 is formed, and then polished so that the impurity layer 7 is divided into two with respect to the center of the channel formation portion C to be flattened. do. As described above, as shown in FIG. 4, the P-type impurity layer is formed as two impurity layers 7a and 7b in the shape of a groove, and the two impurity layers provide a uniform concentration gradient of the channel. It will serve as a diffusion layer.
상기와 같이 해서 만들어진 도랑 형상의 두개의 불순물층(7a)(7b)에 게이트용 산화막 및 절연용 산화막(8)을 형성하고, 게이트용 다결정 실리콘(10)을 적층시킨 후, 고농도의 N형 불순물(9)을 이온주입/확산하여 소오스/드레인 전극(미도시)을 만든다(제5도). 이 경우, 상기 고농도의 N형 불순물층(9)이 이온주입/확산되면, 상대적으로 농도가 높은 P형 불순물층(7a)(7b)에서 P형 불순물이 확산되기 때문에 채널 하부의 불순물 농도구배는 최종적으로 균일하게 된다.The gate oxide film and the insulating oxide film 8 are formed in the two trench-shaped impurity layers 7a and 7b formed as described above, and the gate polycrystalline silicon 10 is laminated. (9) is ion implanted / diffused to form a source / drain electrode (not shown) (FIG. 5). In this case, when the high concentration of the N-type impurity layer 9 is ion implanted / diffused, the impurity concentration gradient in the lower portion of the channel is diffused because the P-type impurity is diffused in the relatively high P-type impurity layers 7a and 7b. Finally it becomes uniform.
따라서, 본 발명 제조방법에 따르면, 종래와 같이 P형의 불순물이 양쪽의 N형 불순물쪽으로 확산됨에 따라 상대적으로 채널의 중심부보다 양쪽 단부의 불순물 농도가 작아지는 문제점이 해결될 수 있게 되는 것이다. 더욱이, 상기와 같이 도랑 형상의 P형 불순물층(7a)(7b)에서 그 양옆에 존재하는 N형 불순층(실질적으로 소오스/드레인 영역)으로 P형 불순물이 확산되면, 상기 P형 불순물층(7a)(7b)과 인접해 있는 상기 N형 불순층(9)의 농도가 다른 부분의 농도보다 낮아지기 때문에 제5도에 도시되어 있는 바와 같은 소정의 LDD구조(7c)가 자체적으로 만들어지게 된다. 즉, 본 발명에 따르면, 채널에 주입된 P형 불순물을 이용하여 채널 양쪽 단부 부분의 N형 불순물의 농도를 감소시켜 줌으로써 자체-정렬된 LDD구조를 갖게 할 수 있다.Therefore, according to the manufacturing method of the present invention, as the conventional P-type impurities are diffused toward both of the N-type impurities, the problem that the impurity concentration at both ends is relatively smaller than the center of the channel can be solved. In addition, when the P-type impurity is diffused from the trench-shaped P-type impurity layers 7a and 7b to the N-type impurity layer (substantially source / drain regions) existing as described above, the P-type impurity layer ( Since the concentration of the N-type impurity layer 9 adjacent to 7a) and 7b is lower than that of the other portions, the predetermined LDD structure 7c as shown in FIG. 5 is made by itself. That is, according to the present invention, it is possible to have a self-aligned LDD structure by reducing the concentration of N-type impurities at both ends of the channel by using P-type impurities injected into the channel.
상술한 바와 같이 본 발명에 따른 MOS 트랜지스터의 제조방법은 쇼트 채널 형성시 채널이 형성되어질 P형 영역의 농도구배 변화를 방지하기 위한 제조방법으로, 채널의 농도구배 균일성 및 드레인 단자의 이온 임팩트(impact) 현상 방지를 위한 LDD(lightly doped drain) 구조를 위해 리지형상의 이온주입을 하고, 게이트 폭을 조절함으로써 MOS 트랜지스터의 특성을 최적화시킬 수 있는 이점을 제공한다. 더욱이, 본 발명 MOS 트랜지스터의 제조방법에 의하면 별도의 N층을 사용하지 않고 채널영역에 주입되는 P형 불순물의 농도를 조절함으로써 소오스/드레인 영역의 LDD구조가 동시에 실현될 수 있는 이점을 제공한다.As described above, the manufacturing method of the MOS transistor according to the present invention is a manufacturing method for preventing the concentration gradient change of the P-type region in which the channel is to be formed when the short channel is formed, and the uniformity of the concentration gradient of the channel and the ion impact of the drain terminal ( For the lightly doped drain (LDD) structure to prevent phenomena, the ridge-type ion implantation and the gate width are adjusted to optimize the characteristics of the MOS transistor. Furthermore, the method of manufacturing the MOS transistor of the present invention provides the advantage that the LDD structure of the source / drain regions can be simultaneously realized by controlling the concentration of the P-type impurities injected into the channel region without using a separate N layer.
본 발명은 상기 실시예에 한정되지 않으며, 많은 변형이 본 발명의 기술적 사상내에서 당 분야에 통상의 지식을 가진 자에 의하여 가능함은 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.
Claims (5)
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