JPH0786423A - Manufacture of mis type semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To cut down a forming process of the gate, the source and the drain of a CMOS semiconductor integrated circuit device of LDD structure. CONSTITUTION:A field region (an oxide film) 103 and a gate oxide film 104 are formed on a P-type silicon substrate 101, and a source.drain region 109 of N-type high impurity concentration is formed. An oxide film 110 is formed on the whole surface, and the oxide film 110 and poly silicon 105 on an N-well are patterned. An oxide film is deposited on the whole surface, and a side wall oxide film of the gate electrode of a PMOS transistor is formed by etching- back. A source.drain region of N-type high impurity concentration is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a MIS type semiconductor integrated circuit device, and more particularly to a method of manufacturing a CMOS type semiconductor integrated circuit device having an LDD structure with a shortened process.

[0002]

2. Description of the Related Art Generally, in a CMOS semiconductor device, an NMO is used.
Sources of S and PMOS transistors,
Since it is necessary to form the drains with different masks, there is a drawback that the manufacturing process becomes long. In order to avoid the drawback, a manufacturing method has been proposed in which the number of masks is reduced and the number of steps is reduced (JP-A-1-147856). FIG. 3 shows the method. First, the N well 20 is formed on the P-type silicon substrate 201.
2 are formed, and the field region 203 and the gate oxide film 20 are formed.
After forming No. 4, n-type polysilicon 205 of about 4000 Å is formed on the entire surface. The polysilicon is patterned while leaving the polysilicon on the N well to form a gate electrode on the NMOS side. Subsequently, phosphorus is ion-implanted at a dose of about 10 ¹³ cm ^-2 to form an n-type low impurity concentration LDD region 207 in a self-aligned manner with the gate electrode. (Fig. 3a)

Further, an oxide film of about 2000 Å is deposited on the entire surface and etched back to form a sidewall oxide film 208, and then arsenic is ion-implanted at a dose of about 4 × 10 ¹⁵ cm ^-2 to form a gate electrode. And the source / drain regions 20 of n-type high impurity concentration in self-alignment with the sidewall oxide film
9 is formed. (FIG. 3b) Further, the polysilicon 205 on the N well is patterned using a photoresist to form a gate electrode on the PMOS side. Subsequently, boron is ion-implanted at a dose of about 1 × 10 ¹⁵ cm ⁻² to form p-type high impurity concentration source / drain regions 214 in a self-aligned manner with the gate electrode.
(FIG. 3c) In the above manufacturing method, the mask used for patterning only needs to form the NMOS gate electrode and the PMOS gate electrode.
It is possible to reduce the number of masks required for four LDD formations, SD formations, and PMOS SD formations from two to two, and it is possible to greatly reduce the number of steps.

[0004]

However, in the conventional method of manufacturing a CMOS semiconductor device described above, the NMO is used.
S is an LDD structure transistor, and PMOS is a single drain structure transistor. Generally, in order to miniaturize MOS transistors, it is necessary to suppress the short channel effect in order to prevent the threshold voltage from lowering and punch through when the gate length becomes small. LDD structure is required. Therefore, in the above manufacturing method, NMOS, PMO
There is a problem that both S cannot simultaneously realize the LDD structure. P
In order to form the LDD structure on the MOS side as well, it is necessary to make the structure shown in FIG.

First, in place of forming the p-type high impurity concentration region 214 in FIG. 3C, boron is ion-implanted at a dose of about 10 ¹³ cm ^-2 , and the p-type low impurity concentration LDD is self-aligned with the gate electrode. A region 212 is formed. (FIG. 4a) Next, an oxide film of about 2000 Å is deposited on the entire surface and etched back to form a sidewall oxide film 213 of the gate electrode of the PMOS, and subsequently, the source / drain regions of the NMOS are masked with a photoresist, by boron ions are implanted at an 1 × 10 ¹⁵ cm ^-2 order of dose to form the source and drain regions 214 of the self-aligned manner p-type high impurity concentration in the gate electrode and the side wall oxide film. That is, the conventional method for manufacturing a CMOS semiconductor device is
Mask is 1 when MOS and PMOS are LDD structure
There is a drawback that a large number of sheets are required and the number of steps is increased.

[0006]

In order to solve the above-mentioned problems, in a semiconductor integrated circuit device of the present invention, a first conductivity type first impurity region and a second conductivity type second impurity region which are element formation bases. A step of forming a field region for element isolation in the impurity region, and a step of forming a field region other than the field region.
Forming a gate insulating film on the semiconductor substrate in the S-transistor formation region; forming a conductor layer on the entire surface of the field region and the element formation region; and processing the conductor layer in the first impurity region to form a gate electrode. Forming process, first
A second conductivity type impurity is introduced into the semiconductor region of the impurity region, and the source has a low impurity concentration in a self-aligned manner with the gate electrode,
A step of forming a drain, a step of forming a sidewall on the gate electrode in the first impurity region, and a step of introducing a second conductivity type impurity into the semiconductor region of the first impurity region to enhance the self-alignment with the gate electrode and the sidewall. A step of forming a source and a drain having an impurity concentration, a step of depositing a thick insulating film on the entire surface, a step of processing the thick insulating film and the conductor layer in the second impurity region to form a gate electrode, A step of introducing a first conductivity type impurity into the semiconductor region of the impurity region to form a source and a drain with a low impurity concentration in a self-aligned manner with the gate electrode, and a step of forming a sidewall on the gate electrode in the second impurity region. And a step of introducing an impurity of the first conductivity type into the semiconductor region of the second impurity region and forming a source and a drain having a high impurity concentration in a self-aligned manner with the gate electrode and the side wall.

[0007]

In the method of manufacturing the MIS type semiconductor integrated circuit device of the present invention, the first conductivity type first impurity region (NMO) is used.
When the gate electrode of (S) is formed, the gate material is left on the side of the second impurity region (PMOS) of the second conductivity type, and the gate material is used as a mask for ion implantation.
The LDD layer and the source / drain layers of S are formed using only one mask for forming the gate electrode. After that, a thick oxide film is formed on the entire surface, the gate electrode of the PMOS is formed on the oxide film, and this thick oxide film is used as a mask for ion implantation, so that the LDD of the PMOS is formed.
The layer and the source / drain layer can be formed with another mask for forming the gate electrode.

[0008]

Embodiments of the present invention will now be described with reference to the drawings. [Embodiment 1] FIG. 1 is a process sectional view of an embodiment of the present invention. In this embodiment, the first impurity region of the first conductivity type is the region where the NMOS is formed, that is, the P substrate 101 region other than the N well 102, and the second impurity region of the second conductivity type is the region where the PMOS is formed, that is, the N well 102. Well area 10
It is 2. First, the N well 10 is formed on the P-type silicon substrate 101.
2 is formed, a field region (oxide film) 103 and a gate oxide film 104 are formed, and then n of about 4000 Å is formed on the entire surface.
A type polysilicon 105 is formed. Patterning the polysilicon leaving the polysilicon on the N-well,
A gate electrode on the S side is formed. Subsequently, phosphorus is ion-implanted at a dose of about 10 ¹³ cm ^-2 to form an LDD region 107 having a low n-type impurity concentration in a self-aligned manner with the gate electrode.
At this time, ion implantation is performed before removing the photoresist.
Either after removal is okay. (Figure 1a) further deposited oxide film of about 2000Å on the entire surface, forming a sidewall oxide film 108 is etched back, then, arsenic ions are implanted with 4 × 10 ¹⁵ cm ^-2 order of dose, the gate Source / drain regions 109 of n-type high impurity concentration are formed in self-alignment with the electrodes and the sidewall oxide film. (FIG. 1b) Next, an oxide film 110 of about 3000 Å is formed on the entire surface (FIG. 1c).

Subsequently, the photoresist 111 is used to pattern the oxide film 110 and the polysilicon 105 on the N well to form a gate electrode on the PMOS side.
Further, boron is ion-implanted at a dose of about 10 ¹³ cm ^-2 to form p-type low impurity concentration source / drain regions 112 in a self-aligned manner with the gate electrode. The ion implantation at this time may be performed before or after removing the photoresist. (FIG. 2d) Next, a side wall oxide film 113 of the gate electrode of the PMOS is formed by depositing an oxide film of about 2000 Å on the entire surface and etching back. At this time, a thick oxide film 110 remains on the NMOS region. To Then 1 × 10 ¹⁵ cm
By implanting boron with a dose of ^-2 ,
Source / drain regions 114 of high p-type impurity concentration are formed in self-alignment with the gate electrode and the sidewall oxide film. (FIG. 2e) The mask used for patterning in the above-described manufacturing method is only required to form an NMOS gate electrode and a PMOS gate electrode.
A D-structure transistor can be realized.

[Second Embodiment] Next, a second embodiment of the present invention will be described. Although the drawing is the same as FIG. 1, in the second embodiment, the oxide film thickness and the etch back amount of NMOS and PMOS are changed. For example, in the case of NMOS, about 2000 Å of etch-back and PMOS of 2000 Å of oxide film are deposited.
Then, 1500 Å oxide film deposition and etch back are performed.
Using this method, the widths of the sidewalls of the NMOS and PMOS can be set to 0.2 μm and 0.15 μm, respectively, and the LDD structure can be optimized for each. That is, in NMOS, the side wall width is increased to improve hot carrier resistance, in PMOS, the side wall width is decreased, and the resistance of the LDD region is reduced to improve the on-current. Can be expected.
In the manufacturing method described above, the NMOS was formed first, but P
The same method can be used even if the MOS is formed first.

[0011]

As described above, according to the manufacturing method of the present invention, the gate, the source and the drain of the CMOS semiconductor device having the LDD structure NMOS and PMOS are two.
It is possible to form with only one mask. That is, a highly integrated and high-performance CMOS semiconductor device corresponding to miniaturization can be realized with a small number of steps, and effective effects can be obtained in terms of manufacturing period and cost.

[Brief description of drawings]

FIG. 1 is a sectional view of steps (a), (b) and (c) of an embodiment of the present invention.

FIG. 2 is a sectional view of steps (d) and (e) of the embodiment of the present invention.

FIG. 3 is a process sectional view of a conventional example.

FIG. 4 is a process sectional view of a conventional example.

[Explanation of symbols]

 101, 201. P-type silicon substrate 102, 202. N-well 103, 203. Field oxide film 104, 204. Gate oxide film 105, 205. Polysilicon 106. Photoresist 107, 207. n-type low impurity concentration region 108, 208. Side wall oxide film 109, 209. n-type high impurity concentration region 110. Oxide film 111, 211. Photoresist 112, 212. p-type low impurity concentration region 113, 213. Side wall oxide film 114, 214. p-type high impurity concentration region 215. Photoresist

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[Procedure amendment]

[Submission date] July 15, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction content]

[0006]

In order to solve the above-mentioned problems, in a semiconductor integrated circuit device of the present invention, a first conductivity type first impurity region and a second conductivity type second impurity region which are element formation bases. A step of forming a field region for element isolation in the impurity region, and a step of forming a field region other than the field region.
Forming a gate insulating film on the semiconductor substrate in the S-transistor formation region; forming a conductor layer on the entire surface of the field region and the element formation region; and processing the conductor layer in the first impurity region to form a gate electrode. Forming process, first
A second conductivity type impurity is introduced into the semiconductor region of the impurity region, and the source has a low impurity concentration in a self-aligned manner with the gate electrode,
A step of forming a drain, a step of forming a sidewall on the gate electrode in the first impurity region, and a step of introducing a second conductivity type impurity into the semiconductor region of the first impurity region to enhance the self-alignment with the gate electrode and the sidewall. A step of forming a source and a drain having an impurity concentration, a step of depositing a thick insulating film on the entire surface, a step of processing the thick insulating film and the conductor layer in the second impurity region to form a gate electrode, A step of introducing a first conductivity type impurity into the semiconductor region of the impurity region to form a source and a drain with a low impurity concentration in a self-aligned manner with the gate electrode, and a step of forming a sidewall on the gate electrode in the second impurity region. And a step of introducing a first conductivity type impurity into the semiconductor region of the second impurity region and forming a source and a drain having a high impurity concentration in a self-aligned manner with the gate electrode and the side wall. Also, the first conductivity type first impurity region is
The method for manufacturing a MIS type semiconductor integrated circuit device is characterized in that the second impurity region of the second conductivity type is a region for forming an NMOS, and the second impurity region of the second conductivity type is a region for forming a PMOS.

Claims (1)

[Claims] 1. A step of forming a field region for element isolation in a first impurity region of a first conductivity type and a second impurity region of a second conductivity type which are element formation bases, and a MOS other than the field region. Forming a gate insulating film on the semiconductor substrate in the transistor forming region, forming a conductor layer over the entire field region and element forming region, and processing the conductor layer in the first impurity region to form a gate electrode And a step of introducing a second conductivity type impurity into the semiconductor region of the first impurity region to form a source and a drain having a low impurity concentration in a self-aligned manner with the gate electrode, and a gate electrode in the first impurity region. Forming a sidewall on the
A step of introducing a second conductivity type impurity into the semiconductor region of the first impurity region to form a source and a drain having a high impurity concentration in a self-aligned manner with the gate electrode and the sidewall; and a step of depositing a thick insulating film on the entire surface. A step of processing a thick insulating film and a conductor layer in the second impurity region to form a gate electrode, and introducing a first conductivity type impurity into a semiconductor region of the second impurity region so as to be self-aligned with the gate electrode. A step of forming a low impurity concentration source and drain, a step of forming a sidewall on the gate electrode in the second impurity region, and a step of introducing a first conductivity type impurity into the semiconductor region of the second impurity region to form a gate electrode. And a step of forming a source and a drain having a high impurity concentration in a self-aligning manner with the side wall, and a method of manufacturing a MIS type semiconductor integrated circuit device.