KR100852819B1 - method for fabricating liquid crystal display - Google Patents

Abstract

The present invention discloses a method of manufacturing a liquid crystal display device which can reduce the number of masks in a field fringe switching (FFS) mode having a wide viewing angle characteristic.

According to an aspect of the present invention, there is provided a method of manufacturing a FFS mode liquid crystal display device having a BCE structure, the method including: providing an insulating substrate having a pixel portion and a thin film transistor portion defined thereon, forming a first metal film on the entire surface of the substrate, and performing a first photolithography process Etching the first metal film to form a gate electrode in the thin film transistor portion, sequentially forming an insulating film and an amorphous silicon film on the entire surface of the substrate including the gate electrode, and etching the amorphous silicon film by a second photolithography process. Forming an active layer. Forming a second metal film on the entire surface of the resulting substrate, and then etching the second metal film by a third photolithography process to form a source / drain electrode; and forming a protective film on the entire surface of the substrate including the source / drain electrode. Next, the protective film is etched by a fourth photolithography process to expose a predetermined portion, the ITO film is formed on the resultant, and the ITO film is etched by a fifth photolithography process to cover the etched portion of the protective film. And forming a pixel electrode and a common electrode each having a slit shape without overlapping each other.

Description

Method for fabricating liquid crystal display

1 is a cross-sectional view illustrating a method of manufacturing a liquid crystal display device according to a first embodiment of the present invention, in a FFS mode having a BCE structure.

FIG. 2 is a cross-sectional view illustrating a method of manufacturing a liquid crystal display device according to a second embodiment of the present invention, wherein the pixel is in the FFS mode of an ES (Etch Stopper) structure.

3 is a view illustrating a method of manufacturing a liquid crystal display device according to a first embodiment of the present invention, wherein the pixel plan view in the FFS mode of the BCE structure.

Figures 4a to 4e is a cross-sectional view showing a plane cut along the line AB of FIG.

5 is a view illustrating a method of manufacturing a liquid crystal display device according to a second embodiment of the present invention, wherein the pixel plan view in the FFS mode of the ES structure.

6A to 6G are cross-sectional views illustrating a plane cut along the CD line of FIG. 4.

The present invention relates to a liquid crystal display device, and more particularly, to a method of manufacturing a liquid crystal display device which can reduce the number of masks in a field fringe switching (FFS) mode having a wide viewing angle characteristic.                         

FIG. 1 is a cross-sectional view illustrating a method of manufacturing a liquid crystal display device according to a first embodiment of the present invention, in a FFS mode having a back channel etching (BCE) structure.

In the method of manufacturing the liquid crystal display according to the first exemplary embodiment, as shown in FIG. 1, the first ITO (the first ITO ( After forming an Indium Tin Oxide film (not shown), the first ITO film is etched by a first photolithography process to form a first ITO electrode 3 in the pixel portion I.

Subsequently, a first metal film (not shown) is formed on the entire surface of the substrate including the ITO electrode 3, the first metal film is etched by a second photolithography process, and the gate electrode 5 is formed on the thin film transistor unit II. ).

Then, an insulating film 7 is formed on the entire surface of the resultant substrate, an amorphous silicon film (not shown) is formed on the insulating film 7, and then the amorphous silicon film is etched by a third photolithography process. The active layer 11 is formed.

Thereafter, a second metal film (not shown) is formed on the entire surface of the resultant substrate, and then the second metal film is etched by a fourth photolithography process to form source / drain electrodes 13 and 15.

Subsequently, after the passivation layer 17 is formed on the entire surface of the substrate including the source / drain electrodes 13 and 15, the passivation layer is etched by a fifth photolithography process to expose a portion where the second ITO electrode is to be formed.

Thereafter, after forming the second ITO film on the entire surface of the resultant substrate, the second ITO film is etched by a sixth photolithography process to form a second ITO electrode 19 covering the exposed portion of the protective film.

FIG. 2 is a cross-sectional view illustrating a method of manufacturing a liquid crystal display device according to a second embodiment of the present invention, in the FFS mode of an ES (Etch Stopper) structure.

In the method of manufacturing the liquid crystal display according to the second exemplary embodiment, as shown in FIG. 2, an ITO (Indium) is formed on the entire surface of the insulating substrate 1 on which the pixel portion I and the thin film transistor portion II are defined. After forming a Tin Oxide film (not shown), the ITO film is etched by a first photolithography process to form a first ITO electrode 3 in the pixel portion I.

Subsequently, a first metal film (not shown) is formed on the entire surface of the substrate including the first ITO electrode 3, and the first metal film is etched by a second photolithography process to form a gate electrode (II) in the thin film transistor unit II. 5) form.

Then, a first insulating film and a second insulating film 7 and 9 are sequentially formed on the entire surface of the resultant substrate, and then an amorphous silicon film (not shown) and an etch stopper film (on the second insulating film 9) are formed. After the formation of the etch stopper 13, the etch stopper film is etched by a third photolithography process.

Thereafter, the amorphous silicon film is etched by the fourth photolithography process to form the active layer 13.

Subsequently, after the second ITO film (not shown) is formed on the entire surface of the substrate including the active layer 13, the second ITO film is etched by a fifth photolithography process to form the second ITO electrode 17 on the pixel portion I. Form.

Then, a contact hole (not shown) is formed on the entire surface of the substrate including the second ITO electrode 17 by a sixth photolithography process. Subsequently, after forming the second metal film (not shown), the second metal film is etched by the seventh photolithography process to form source / drain electrodes 15 and 16.

Thereafter, a passivation layer 21 is formed on the entire surface of the substrate including the source / drain electrodes 15 and 16, and then the passivation layer is etched by an eighth photolithography process.

However, the manufacturing method of the FFS mode liquid crystal display device having the BCE structure according to the first embodiment of the present invention proceeds to six mask processes, and as the eighth process proceeds to the FFS mode liquid crystal display device of the ES structure according to the second embodiment of the present invention, There was a problem that the process is complicated.

Accordingly, an object of the present invention is to provide a method of manufacturing a liquid crystal display device, which is designed to solve the above problems and can simplify the entire process by reducing a mask process.

In the manufacturing method of the FCE mode liquid crystal display device of the BCE structure according to the present invention for achieving the above object, providing a dielectric substrate with a pixel portion and a thin film transistor portion respectively defined; And etching the first metal film by a first photolithography process to form a gate electrode in the thin film transistor unit, sequentially forming an insulating film and an amorphous silicon film on the entire surface of the substrate including the gate electrode, and Etching the amorphous silicon film by a lithography process to form an active layer, forming a second metal film on the entire surface of the resultant substrate, and then etching the second metal film by a third photolithography process to form a source / drain electrode. Forming a protective film on the entire surface of the substrate including the source / drain electrodes; The protective layer is etched by a fourth photolithography process, wherein the thin film transistor is etched so that a predetermined region of the drain electrode is exposed, and the pixel portion is exposed to the substrate and the insulating film under the protective layer at a predetermined portion. After etching, and forming an ITO film on the resultant, the ITO film is etched by a fifth photolithography process so that the pixel electrode and the common electrode having a slit shape do not overlap each other, and the common electrode is formed on the fourth photo. The substrate is exposed by etching to the insulating film of the pixel portion by a lithography process, and the pixel electrode is formed on the passivation film remaining on the pixel portion by a fourth photolithography process and simultaneously exposes the drain electrode of the thin film transistor portion. It characterized in that it comprises a step of forming a covered portion .

After etching the passivation layer, it is preferable to add a step of performing a surface stabilization process using H 2, Ar, and O 2 plasma gases.

In addition, the surface stabilization process is preferably carried out in a power of 100 ~ 700 Wat and pressure range of 1mTorr ~ 10Torr.

In the manufacturing method of the FFS mode liquid crystal display device of the ES structure according to the present invention, providing an insulating substrate having a pixel portion and a thin film transistor portion, respectively, forming a first metal film on the entire surface of the substrate, the first photolithography Etching the first metal film by a process to form a gate electrode, sequentially forming an insulating film, an amorphous silicon film not doped with impurities, and an etch stopper thin film on the entire surface of the substrate including the gate electrode; Etching the etch stopper film by a photolithography process to form an etch stopper; forming an amorphous silicon film doped with impurities on the entire surface of the substrate including the etch stopper; and then doping the impurity by a third photolithography process. Each amorphous silicon film and an amorphous silicon film that is not doped with impurities Forming a layered layer and an ohmic contact layer, forming a transparent conductive film on the entire surface of the resultant substrate, and etching the transparent conductive film by a fourth photolithography process to form a comb-shaped pixel electrode; Etching an insulating film of a portion of the pixel portion where the pixel electrode is not formed by a photolithography process, forming a second metal film on the entire surface of the resultant, and then etching the second metal film by a sixth photolithography process. A source / drain electrode and a common electrode are formed, and the common electrode is formed in a comb-tooth shape so as not to overlap the pixel electrode in a portion where the insulating film is etched by the fifth photolithography process, and among the source / drain electrodes Forming a drain electrode to cover the pixel electrode formed on the thin film transistor; and before the source / drain And after forming a protective film over the entire surface of the substrate including a common electrode, by a seventh photolithography process characterized by including the step of etching a portion of the protective film.

After etching the insulating film, it is preferable to add a step of performing a surface stabilization process by H2, Ar, and O2 plasma gas.

In addition, the surface stabilization process is preferably carried out in a power of 100 ~ 700 Watt and pressure range of 1mTorr ~ 10Torr.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a view illustrating a method of manufacturing a liquid crystal display device according to a first embodiment of the present invention, which is a plan view of a pixel in an FFS mode of a BCE structure.

4A to 4E are cross-sectional views illustrating a plane cut along the line AB of FIG. 3.

In the FFS mode liquid crystal display device having the BCE structure according to the first embodiment of the present invention, as shown in FIG. 3, the ITO electrode used as the common electrode 114a and the pixel electrode 114b may serve as a lower electrode and an upper plate. It acts as an electrode and does not cross each other.

In addition, since the insulating film does not exist between the common electrode 114a and the pixel electrode 114b among the ITO electrodes, the common electrode 114a and the pixel electrode 114b do not overlap each other to prevent a short between the electrodes. It does not have a structure and is manufactured in a slit shape.

Meanwhile, an insulating film 104 to be described later is etched between the common electrode 114a and the pixel electrode 114b to prevent trapping of ions or electrons in the gate insulating film.

In the method of manufacturing the FFS mode liquid crystal display device having the BCE structure according to the first embodiment of the present invention, as shown in FIG. 4A, the insulating substrate 100 in which the pixel portion III and the thin film transistor portion IV are defined, respectively, is defined. A first metal film (not shown) is formed on the entire surface, and the first metal film is etched by the first photolithography process to form the gate electrode 102 in the thin film transistor unit IV.

Subsequently, as shown in FIG. 4B, an insulating film 104 is formed on the entire surface of the substrate including the gate electrode 102, and then an amorphous silicon film (not shown) and impurities doped with impurities are formed on the insulating film 104. After the undoped amorphous silicon film (not shown) is formed sequentially, the films are etched by a second photolithography process to form the active layer 106.

Then, as shown in FIG. 4C, a second metal film (not shown) is formed on the entire surface of the resultant substrate, and then the second metal film is etched by a third photolithography process to source / drain electrodes 110a. ) 110b. In this case, in the etching process for forming the source / drain electrodes 110a and 110b, an ohmic contact layer 108 is formed by etching an amorphous silicon film doped with impurities.

Thereafter, as shown in FIG. 4D, after forming the passivation layer 112 on the entire surface of the substrate including the source / drain electrodes 110a and 110b, the passivation layer 112 is etched by a fourth photolithography process. The thin film transistor unit IV is etched to expose a predetermined region of the drain electrode 110b, and the insulating layer 104 under the passivation layer 112 is formed at a portion where the common electrode 114a, which will be described later, of the pixel unit III is to be formed. Etch to). In this case, the insulating film 104 is preferably etched until the substrate 100 is exposed.
In addition, in the protective layer etching process, H2, Ar and O2 gas is supplied to the surface to induce surface stabilization, and the surface stabilization process is performed at a power of 100 to 700 Watt and a pressure range of 1 mTorr to 10 Torr.

Subsequently, as shown in FIG. 4E, after forming an ITO film (not shown) on the entire surface of the resultant substrate, the ITO film is etched by a fifth photolithography process to slit the common electrode 114a and the pixel. The electrode 114b is formed. At this time, the common electrode 114a is etched to the insulating film 104 in the pixel portion III by the fourth photolithography process and is formed in the exposed portion of the substrate, and the pixel electrode 114b is formed by the fourth photolithography process. The upper portion of the passivation layer 112 remaining in the pixel unit III and the passivation layer 112 of the thin film transistor unit IV are etched to cover the exposed portions of the drain electrode 110b so as to be electrically connected.
That is, the common electrode 114a and the pixel electrode 114b are formed on different layers and are patterned so as to be spaced apart from each other and do not overlap each other.

FIG. 5 is a view illustrating a manufacturing method of a liquid crystal display according to a second exemplary embodiment of the present invention and is a plan view of a pixel in an FFS mode of an ES structure.

6A to 6G are cross-sectional views showing a plane cut along the CD line of FIG. 4.

In the FFS mode liquid crystal display of the ES structure according to the second embodiment of the present invention, as shown in FIG. 5, the common electrode 114 and the pixel electrode 113 do not cross each other. Since there is no insulating film between the electrodes, the common electrode 114 and the pixel electrode 113 do not overlap each other and are manufactured in a slit shape to prevent a short between the electrodes.

The insulating film 104 is etched between the common electrode 114 and the pixel electrode 113 to prevent trapping of ions or electrons on the gate insulating film.

In the method of manufacturing the FFS mode liquid crystal display device having the ES structure according to the second embodiment of the present invention, as shown in FIG. 6A, the insulating substrate 100 defined in each of the pixel portion III and the thin film transistor portion IV is defined. A first metal film (not shown) is formed on the entire surface, and the gate electrode 102 is formed in the thin film transistor unit IV by etching the first metal film by a first photolithography process.

Subsequently, as shown in FIG. 6B, an insulating film 104 is formed on the entire surface of the substrate including the gate electrode 102, and then an amorphous silicon film 106a without doping impurities is formed on the insulating film 104. do. Thereafter, an etch stopper film (not shown) is formed on the amorphous silicon film 106a that is not doped with impurities, and the etch stopper 109 is etched by etching the etch stopper film by a second photolithography process. Form.

Subsequently, as shown in FIG. 6C, an amorphous silicon film (not shown) doped with impurities is formed on the entire surface of the substrate including the etch stopper 109, and then the impurities are doped with amorphous by a third photolithography process. The silicon layer and the amorphous silicon layer 106a not doped with impurities are etched to form the active layer 106 and the ohmic contact layer 108.

6D, an ITO film (not shown) is formed on the entire surface of the resultant substrate, and the ITO film is etched by a fourth photolithography process to form a pixel electrode 113. In this case, the pixel electrode 113 is patterned in the shape of a comb.

Then, as illustrated in FIG. 6E, the insulating layer 104 of the portion of the pixel portion III where the pixel electrode 113 is not formed is etched by the fifth photolithography process.

Thereafter, as shown in FIG. 6F, a second metal film (not shown) is formed on the entire surface of the resultant, and the second metal film is etched by a sixth photolithography process to provide a source / The drain electrodes 110a and 110b are formed, and in the pixel portion III, the insulating layer 104 is etched by the fifth photolithography process to form a common electrode 114 at a portion where the substrate 100 is exposed. That is, the common electrode 114 and the pixel electrode 113 are formed on different layers and are patterned so as to be spaced apart from each other and do not overlap each other.
In addition, the common electrode 114 has a structure that does not overlap the pixel electrode 113, and is patterned in the same comb teeth as the pixel electrode 113.

Next, as shown in FIG. 6G, a protective film is formed on the entire surface of the substrate including the source / drain electrodes 110a, 110b and the common electrode 114, and then the pad portion (not shown) is formed by a seventh photolithography process. A portion of the passivation layer 112 is etched to expose C).

As described above, in the first embodiment of the present invention, by reducing the number of photo processes in a five mask process, productivity is increased by lowering the manufacturing cost and reducing the defective rate.

The pre-tilt angle can be increased by removing the gate insulating film inside the pixel, and a larger electric field can be formed by removing the insulating film between the pixel electrode and the common electrode, thereby lowering the liquid crystal driving voltage.

In the second embodiment of the present invention, by reducing the number of photo processes in the seven mask process, the productivity is increased by lowering the manufacturing cost and reducing the defective rate.                     

In the present invention, after the insulating film etching process, plasma gas treatment is performed on the surface to induce surface stabilization, thereby removing residual ion sources.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (6)

In the manufacturing method of the FFS mode liquid crystal display device of a BCE structure, Providing an insulating substrate having a pixel portion and a thin film transistor portion defined therein, Forming a first metal film on the entire surface of the substrate and etching the first metal film by a first photolithography process to form a gate electrode in the thin film transistor unit; Sequentially forming an insulating film and an amorphous silicon film on the entire surface of the substrate including the gate electrode; Etching the amorphous silicon film by a second photolithography process to form an active layer; Forming a second metal film on the entire surface of the resultant substrate, and then etching the second metal film by a third photolithography process to form source / drain electrodes; After forming a protective film on the entire surface of the substrate including the source / drain electrodes, the protective film is etched by a fourth photolithography process, wherein the thin film transistor part is etched so that a predetermined region of the drain electrode is exposed, and the pixel part is formed on a predetermined portion. Etching the passivation layer and the insulating layer under the passivation layer to expose the substrate; After the ITO film is formed on the resultant, the ITO film is etched by a fifth photolithography process so that the pixel electrode having the slit shape and the common electrode do not overlap each other. The common electrode is etched to the insulating film of the pixel portion by the fourth photolithography process and formed on the exposed portion of the substrate, and the pixel electrode is formed on the protective film remaining on the pixel portion by the fourth photolithography process. And covering the exposed portion of the drain electrode of the thin film transistor unit. The method of claim 1, further comprising, after etching the passivation layer, performing a surface stabilization process using H 2, Ar, and O 2 plasma gases. The method of claim 1, wherein the surface stabilization process is performed at a power of 100 to 700 Wat and a pressure range of 1 mTorr to 10 Torr. In the manufacturing method of the FFS mode liquid crystal display device of an ES structure, Providing an insulating substrate having a pixel portion and a thin film transistor portion respectively defined; Forming a first metal film on the entire surface of the substrate and etching the first metal film by a first photolithography process to form a gate electrode; Sequentially forming an insulating film, an amorphous silicon film not doped with impurities, and an etch stopper thin film on the entire surface of the substrate including the gate electrode; Etching the film for etching etch stop by a second photolithography process to form an etch stopper; After forming an amorphous silicon film doped with an impurity on the entire surface of the substrate including the etch stopper, the amorphous silicon film doped with the impurity and the amorphous silicon film not doped with the impurity are etched by a third photolithography process, respectively. Forming a contact layer, Forming a transparent electrode film on the entire surface of the resultant substrate, and then etching the transparent conductive film by a fourth photolithography process to form comb-shaped pixel electrodes; Etching an insulating film of a portion of the pixel portion in which the pixel electrode is not formed by a fifth photolithography process; After forming a second metal film on the entire surface of the resultant, the second metal film is etched by a sixth photolithography process to form a source / drain electrode and a common electrode, The common electrode is formed in the shape of a comb so as not to overlap with the pixel electrode in a portion where the insulating film is etched by the fifth photolithography process, and the drain electrode of the source / drain electrode is the pixel electrode formed on the thin film transistor. Forming to cover the; And forming a protective film on the entire surface of the substrate including the source / drain electrodes and the common electrode, and then etching a part of the protective film by a seventh photolithography process. The method of claim 4, further comprising, after etching the insulating film, performing a surface stabilization process using H 2, Ar, and O 2 plasma gases. The method of claim 5, wherein the surface stabilization process is performed at a power of 100 to 700 Wat and a pressure range of 1 mTorr to 10 Torr.

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