JPH09283763A - Active matrix substrate manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify the production process and obtain a good TFT characteristics by side-etching a semiconductor layer beneath a channel protective insulation film at forming a first and second contact layers. SOLUTION: After forming resist patterns 12 of a first and second contact layers 6a, 6b, they are dry etched with SF6 gas to result in that a semiconductor 4 below the ends of a channel protective insulation film pattern not overlapped with the resist patterns of the contact layers 6a, 6b are side-etched to form spaces, depending on the quantity of overetching. The channel protective insulation film part is etched to be removed according to a pattern to form source and drain electrodes 7 and 8. This reduces the OFF-current Ioff of a TFT, without producing a conductive reaction layer 10 at the semiconductor layer side faces to be a leak path of the TFT.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an active matrix substrate used in a liquid crystal display device or the like.

[0002]

2. Description of the Related Art FIGS. 6 and 7 are process cross-sectional explanatory views showing a process of forming a contact layer in a conventional method of manufacturing an active matrix substrate.

Since the planar shape of the conventional active matrix substrate is the same as that of the active matrix substrate of the present invention shown in FIG. 1, the conventional active matrix substrate will be described with reference to FIG. The manufacturing method will be described. 6 is a sectional view taken along line XX shown in FIG. 1, and FIG. 7 is a sectional view taken along line YY shown in FIG. In FIGS. 6 and 7, 1 is a glass substrate, 2 is a gate electrode, 3 is a gate insulating film, 4 is a semiconductor layer, 5 is a channel protective insulating film, 6 is a first contact layer 6a and a second contact layer 6b. Contact layer, 7 is a source electrode composed of an upper layer source electrode 7a and a lower layer source electrode 7b, 8 is a drain electrode composed of an upper layer drain electrode 8a and a lower layer drain electrode 8b, 10
Indicates a conductive reaction layer, AL indicates an aluminum film, and HF indicates a heat resistant metal film. 6 (a) and 7
As shown in (a), first, a gate electrode 2 made of chromium is formed in a predetermined pattern on the glass substrate 1 by a sputtering method using a photomask, and then the glass electrode 1 is formed so as to cover the gate electrode 2. A gate insulating film 3 made of silicon nitride is formed on the entire surface of. Next, in the upper layer of the gate electrode with the gate insulating film 3 interposed therebetween, the a-Si layer is formed in substantially the same size and position as the gate electrode, that is, in the same region as the gate electrode region.
A semiconductor layer 4 made of is formed, and a channel protection insulating film 5 made of silicon nitride is patterned on the semiconductor layer 4. At this time, the channel protection insulating film 5 has the same length as the semiconductor layer 4 and a width smaller than that of the semiconductor layer 4, and is formed in the central portion of the semiconductor layer 4.
The semiconductor layer 4 is exposed on both sides of the channel protection insulating film 5. After that, FIG. 6 (b) and FIG.
As shown in FIG. 6B, phosphorus ions are implanted into the exposed portion of the semiconductor layer 4 from above the channel protective insulating film 5, and then, as shown in FIG.
(Not shown in FIG. 7C) is etched to form the semiconductor layer 4 in a pattern corresponding to the size of the channel protection insulating film 5, whereby the first contact layer 6 is formed.
a and the second contact layer 6b are formed. That is, of the two regions of the semiconductor layer 4 which are exposed without being covered with the channel protection insulating film 5, the pixel electrode 9
The region closer to (see FIG. 1) is the first contact layer 6
a, the region farther from the pixel electrode 9 (see FIG. 1) becomes the second contact layer 6a. In this way, the semiconductor layer 4
The first contact layer 6a and the second contact layer 6b which are in contact with are patterned.

Next, a heat-resistant metal single film such as chromium is formed on the upper layer of the first contact layer 6a and the second layer of the second contact layer 6b thus patterned, or as shown in FIG. As shown in FIG. 6E, after the source electrode 7 and the drain electrode 8 formed of a two-layer film of the aluminum film AL and the heat resistant metal film HF are patterned, the channel protection of the aluminum film AL and the heat resistant metal film HF is performed. The pattern of the insulating film portion is removed by etching.

Here, the source electrode 7 and the drain electrode 8 are composed of the two-layer film as shown in FIG. 6 (e). That is, as the source electrode 7, the lower layer source electrode 7b made of aluminum and the upper layer source electrode 7a made of chromium are formed, and similarly, as the drain electrode 8, the lower layer drain electrode 8b made of aluminum and the upper layer drain electrode 8a made of chromium are formed. To do.

Accordingly, a thin film transistor (thin f
An ilm transistor (hereinafter, simply referred to as TFT) is manufactured, and the pixel electrode 9 is electrically connected to the drain electrode.

[0007]

By the way, the first contact layer 6a and the second contact layer 6 are formed by the above-mentioned procedure.
In the case of forming b, the source electrode 7 and the drain electrode 8 are formed by patterning, and then the pattern shown in FIG.
As shown in (e), the conductive reaction layer 10 (FIGS. 6D and 6E) formed on the exposed side surface of the semiconductor layer 4 by the reaction between the heat resistant metal film HF and the semiconductor layer 4 is also formed. (As shown) is formed.

Therefore, the conductive reaction layer 10 must be removed without damaging the pixel electrode 9, the source electrode 7 and the drain electrode 8 after the source electrode 7 and the drain electrode 8 are patterned. As a removing method, it is often difficult to use strong acid wet etching, and it is limited to amorphous silicon (hereinafter simply referred to as a-Si) dry etching using a fluorine gas. However, the removal of the conductive reaction layer 10 formed on the side surface of the semiconductor layer 4 is not perfect even by etching by the RIE (reactive ion etching) method, and a current leak occurs with the side surface of the semiconductor layer 4 as a leak path, which deteriorates the TFT characteristics. There is a drawback that

In order to solve such a drawback, a heat resistant metal such as titanium, tantalum, tungsten and molybdenum or an alloy film thereof which can form a reaction layer which can be easily dry-etched by a fluorine-based gas is used as a source electrode and a drain. It may be used as the lower layer of the electrode. However, according to this method, the kinds of heat-resistant metal film materials that can be selected are limited, flexibility in selecting a process is reduced, and an extra process for removing the conductive reaction layer 10 is required. There is a problem, and an effective method for obtaining a low-cost active matrix substrate without deterioration of TFT characteristics has not been realized.

The present invention solves the problems of the prior art as described above, and after simplifying the manufacturing process,
It is an object of the present invention to provide a method for manufacturing an active matrix substrate that can obtain good TFT characteristics.

[0011]

A method of manufacturing an active matrix substrate according to the present invention comprises a gate electrode, a semiconductor layer, a drain electrode, a source electrode and a pixel electrode provided on an insulating substrate, and (a) the gate electrode A gate insulating film is provided so as to cover the gate electrode, and the semiconductor layer is provided in the same region as the gate electrode, which is an upper layer of the gate electrode with the gate insulating film interposed therebetween. A channel protective insulating film having a surface area smaller than that of the semiconductor layer is provided in a central portion on the semiconductor layer so that the semiconductor layer is exposed on both sides of the channel protective insulating film, and (b) the pixel. The electrode is provided on the gate insulating film and in a region different from the region of the gate electrode, and (c) the semiconductor layer,
Of the region not covered by the channel protective insulating film,
A region closer to the pixel electrode is a first contact layer, a region farther from the pixel electrode is a second contact layer, and (d) the drain electrode is composed of two layers, and a lower drain layer is formed. The electrode is provided so as to cover a portion of the channel protection insulating film near the pixel electrode, the first contact layer, and a portion of the gate insulating film near the first contact layer, and the upper drain electrode is provided. It is provided so as to cover the entire surface of the lower layer drain electrode, and (e) the source electrode is composed of two layers, and the lower layer source electrode is a part of the portion of the channel protection insulating film remote from the pixel electrode and the second layer. A thin film transistor which is provided so as to cover a contact layer and a portion of the gate insulating film near the second contact layer, and an upper source electrode is provided so as to cover the entire surface of the lower source electrode. A method of manufacturing an active matrix substrate using a switching element as a switching element, wherein side etching is performed on the semiconductor layer below the channel protection insulating film when patterning the first and second contact layers. Characterized by processing.

Further, it is preferable that the etching process is a plasma etching process using SF ₆ gas because side etching can be surely performed.

It is preferable that the first and second contact layers are n-type silicon films, and the n-type silicon film is formed by doping phosphorus into the silicon film.

Further, it is preferable that the etching process is a plasma etching process using CF ₄ gas because side etching can be surely performed.

Further, it is preferable that the first and second contact layers are n-type silicon films, and the n-type silicon film is formed by doping phosphorus into the silicon film.

Further, the etching processing is HNO ₃ --H
The F-based wet etching process is preferable because side etching can be reliably performed.

The first and second contact layers are n-type silicon films, and the n-type silicon film is preferably formed by doping phosphorus into the silicon film.

In this way, when patterning the first and second contact layers (hereinafter sometimes simply referred to as contact layers) in contact with the semiconductor layer, Si / SiN is used.
By processing so that the side etching of the semiconductor layer under the channel protection insulating film at the pattern end face has a large selection ratio and about 0.1 μm or more enters, the heat-resistant metal on the side surface of the semiconductor layer becomes a leak path in the TFT. Since there is no contact with the membrane, the result is no conductive reactive layer, which achieves the object of the invention.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION As described above, when a contact layer in contact with a semiconductor layer is formed by patterning, the semiconductor layer under the channel protective insulating film is side-etched to form an overhang structure, which becomes a leak path in a TFT. There is no contact with the heat resistant metal film on the side surface. Therefore, even after patterning the source electrode and the drain electrode, the conductive reaction layer generated by the reaction with the heat resistant metal film cannot be formed on the side surface of the semiconductor layer, and the TFT leakage current can be significantly reduced.

According to the method of the present invention, the same effect can be expected even when CF ₄ gas is used instead of SF ₆ gas.

Also, instead of dry etching, HNO
Similar effects can be expected by using _3- HF wet etching.

Further, the same effect can be expected when a phosphorus-doped semiconductor layer is used instead of ion implantation.

[0023]

Embodiments of the present invention will be described below in more detail with reference to the accompanying drawings.

Embodiment 1 FIGS. 1, 2 and 3 show an embodiment relating to a method of manufacturing an active matrix substrate of the present invention, of which FIG. 1 is an active matrix substrate produced by the method of the present invention. 2 (a) to FIG. 2 (a) to FIG. 2 (a) to FIG. 2 (a) to FIG. 2 (c) are plan schematic explanatory views showing a planar structure of FIG.
FIG. 3A to FIG. 3E are process cross-sectional explanatory views taken along line YY of FIG. In FIGS. 1, 2 and 3, the same parts as those of the conventional active matrix substrate are designated by the same reference numerals. Further, 12 indicates a resist pattern. The details will be described below with reference to FIGS. 1, 2, and 3.

First, as shown in FIGS. 2A and 3A, chromium is deposited to a thickness of 100 to 400 nm on the glass substrate 1 by the sputtering method. Then, the gate electrode 2 made of chromium is patterned on the chromium layer by a sputtering method using a photomask. Next, the gate insulating film 3 made of silicon nitride and having a thickness of 200 to 500 nm is formed on the entire surface of the glass substrate 1 so as to cover the gate electrode 2 by plasma CVD.
To form Next, a-Si having a thickness of 20 to 100 nm
After the semiconductor layer 4 made of is formed on the gate electrode 2 with the gate insulating film 3 interposed therebetween, and has substantially the same size and the same position as the gate electrode 2, that is, the same region as the gate electrode 2. Thickness 10 made of silicon nitride
Further CVD of the channel protection insulating film 5 of 0 to 300 nm
Method to deposit and pattern. At this time, since the channel protection insulating film 5 has the same length as the semiconductor layer 4 and a width smaller than that of the semiconductor layer 4 and is formed in the central portion of the semiconductor layer 4, both sides of the channel protection insulating film 5 are covered. The semiconductor layer 4 is exposed. Further, FIG. 2 (b)
Then, as shown in FIG. 3B, phosphorus ions are implanted into the exposed portion of the semiconductor layer 4 from above the channel protection insulating film 5 over the entire surface of the glass substrate 1, and then, on the resist pattern 12 (FIG. 3C). (Not shown) is used to pattern the semiconductor layer 4 in accordance with the size of the channel protection insulating film 5. In this way, of the two regions of the semiconductor layer 4 which are exposed without being covered with the channel protective insulating film, the semiconductor layer 4 in the portion not covered with the channel protective insulating film 5 becomes a contact layer by the implantation of phosphorus ions. The region closer to the pixel electrode is the first contact layer 6a, and the region farther from the pixel electrode is the second contact layer 6b.

Next, as shown in FIG. 2C, a resist pattern 12 for the first contact layer 6a and the second contact layer 6b is formed (not shown in FIG. 3C).
After that, the contact layers 6a and 6b are patterned by overetching by dry etching using SF ₆ gas. At this time, the first contact layer 6
a and the second contact layer 6b, the semiconductor layer 4 below the end portion of the channel protective insulating film pattern portion that does not overlap with the respective resist patterns is subjected to side etching depending on the amount of over-etching to form a space portion 13. The semiconductor layer cross section below the channel protection insulating film pattern end portion 9 has an eaves structure. At this time, the side etching is performed from the edge of the channel protective insulating film 5 to the inside by 0.1 μm or more.

Next, as shown in FIGS. 2D and 3D, a thickness of 50 to 100 nm is formed by a sputtering method.
The chromium film CR and the aluminum film AL having a thickness of 200 to 400 nm are sequentially deposited on the glass substrate 1 so as to cover the first contact layer 6a and the second contact layer 6b, and then, as shown in FIG. e) and FIG.
As shown in (e), the source electrode 7 and the drain electrode 8 are formed by pattern-removing the channel protection insulating film portions of the chromium film CR and the aluminum film AL by etching. That is, as the source electrode 7, the lower layer source electrode 7b made of aluminum and the upper layer source electrode 7a made of chromium are formed, and similarly, as the drain electrode 8, the lower layer drain electrode 8b made of aluminum and the upper layer drain electrode 8a made of chromium are formed. To do.

Then, a glass film 1 having a thickness of 50 is formed on the entire surface.
A transparent electrode made of an indium tin oxide film having a thickness of ˜100 nm is patterned to form a pixel electrode 9 (see FIG. 1).
As a result, an active matrix substrate having the structure shown in FIGS. 1, 2 (e) and 3 (e) is manufactured.

In this embodiment, the contact layers 6a and 6 are formed by plasma etching using SF ₆ gas.
Although b was dry-etched, CF ₄ gas may be used instead of SF ₆ gas, and HNO ₃ —HF-based wet etching may be performed. In these cases, the same effect can be obtained. it can.

To form the source electrode 7 and the drain electrode 8 after forming the channel protective insulating film pattern and further implanting phosphorus ions to form the first and second contact layers 6a and 6b as described above. , The conductive reaction layer 10 is formed on the side surface of the semiconductor layer which becomes a leak path in the TFT.
Does not occur and current leakage between the source electrode 7 and the drain electrode 8 does not occur, so that the off current Ioff of the TFT can be reduced.

Further, the source electrode 7 and the drain electrode 8
It is not necessary to perform the step of removing the conductive reaction layer 10 after forming the and. Therefore, the number of steps can be reduced and the manufacturing time can be shortened, so that a simplified and efficient manufacturing process can be enjoyed.

Embodiment 2 FIGS. 4 and 5 show another embodiment of the present invention, in which an active material using phosphorus-doped amorphous silicon (hereinafter simply referred to as n-Si) instead of phosphorus ion implantation. The manufacturing method of a matrix substrate is shown. That is, as shown in FIGS. 4 and 5, first, a chromium layer is formed on the glass substrate 1 by the sputtering method in the same manner as in the case shown in FIGS.
Deposit to a thickness of 00-400 nm. Then, the gate electrode 2 made of a chromium layer is patterned on the chromium layer using a photomask. Next, the entire surface of the glass substrate 1 so as to cover the gate electrode 2 is formed by plasma CVD to a thickness of 200 to 500 nm made of silicon nitride.
Gate insulating film 3 and semiconductor layer 4 having a thickness of 20 to 100 nm
And silicon nitride having a thickness of 100 to 300 nm
The channel protection insulating film 5 is deposited. Then, the channel protection insulating film 5 is patterned.

Then, the entire surface of the glass substrate 1 is covered with the channel protection insulating film pattern so as to have a thickness of 20 to 50 nm.
Then, the n-Si semiconductor film 11 is deposited.

Next, after forming the resist pattern 12 of the first contact layer 6a and the second contact layer 6b, the contact layer is patterned by dry etching using SF ₆ gas so as to be over-etched.
At this time, the semiconductor layer 4 below the end portion of the channel protective insulating film pattern portion that does not overlap with the resist patterns of the first contact layer 6a and the second contact layer 6b is side-etched depending on the amount of over-etching, and thus the space is formed. The cross section of the semiconductor layer below the end portion of the channel protection insulating film pattern has the eaves structure. At this time,
The side etching is performed from the edge of the channel protective insulating film 5 to the inside of 0.1 μm or more.

Next, the thickness of 50 to 50 is formed by the sputtering method.
100 nm chromium film CR and thickness 200-400 n
An aluminum film AL of m is sequentially deposited on the entire surface of the glass substrate 1 so as to cover the first contact layer 6a and the second contact layer 6b, and then the chromium film CR is formed.
Then, the source electrode 7 and the drain electrode 8 are formed by pattern-removing the channel protection insulating film portion of the aluminum film AL by etching. That is, as the source electrode 7, the lower layer source electrode 7b made of aluminum and the upper layer source electrode 7a made of chromium are formed, and similarly, as the drain electrode 8, the lower layer drain electrode 8b made of aluminum and the upper layer drain electrode 8a made of chromium are formed.
To form

Then, the entire surface of the glass substrate 1 has a thickness of 50.
A pixel electrode 9 is formed by patterning a transparent electrode made of an indium tin oxide film of ˜100 nm. As a result, the active matrix substrate having the structure shown in FIGS. 1, 4 (e) and 5 (e) is manufactured.

In the case of the second embodiment, the first embodiment is also used.
The same effect as described above, that is, since the conductive reaction layer 10 does not occur on the side surface of the semiconductor layer 4 made of a-Si, the source electrode
Since the current leakage between the drain electrode 8 and the drain electrode 8 can be remarkably reduced, the off current Ioff of the TFT can be reduced. Further, since the number of steps can be reduced and the manufacturing time can be shortened, it is possible to obtain the efficiency of enjoying a simplified and efficient manufacturing process.

In this example, the contact layers 6a and 6 were formed by plasma etching using SF ₆ gas.
Although b was dry-etched, CF ₄ gas may be used instead of SF ₆ gas, and HNO ₃ —HF-based wet etching may be performed. In these cases, the same effect can be obtained. it can.

[0039]

According to the method of the present invention described above, a
Since the electric leakage between the source electrode and the drain electrode via the side surface of the semiconductor layer made of -Si can be remarkably reduced, the off current Ioff of the TFT can be reduced. Therefore, an active matrix substrate having excellent TFT characteristics can be realized. Moreover, the process of removing the conductive reaction layer after forming the source electrode and the drain electrode becomes unnecessary. Therefore, the number of steps can be reduced and the manufacturing time can be shortened, so that an efficient manufacturing process can be enjoyed.

[Brief description of drawings]

FIG. 1 is an explanatory plan view showing a planar structure of a thin film transistor according to a method of the present invention.

FIG. 2 is a process cross-sectional explanatory view showing a change in cross-sectional structure during a manufacturing process according to a cross section taken along the line XX of FIG. 1 of the active matrix substrate according to the first embodiment of the present invention.

FIG. 3 is a process cross-sectional explanatory view showing a change in the cross-sectional structure during the manufacturing process according to the Y-Y line cross section shown in FIG. 1 of the active matrix substrate according to the first embodiment of the present invention.

FIG. 4 is a process cross-sectional explanatory view showing a change in cross-sectional structure during a manufacturing process according to a cross section taken along line XX of FIG. 1 of an active matrix substrate according to another embodiment of the present invention.

5A to 5C are process cross-sectional explanatory views showing changes in the cross-sectional structure during the manufacturing process according to the cross section along the line XX of FIG. 1 of the active matrix substrate according to another embodiment of the present invention.

FIG. 6 is a process cross-sectional explanatory view showing a change in the cross-sectional structure during the manufacturing process according to the cross-section taken along the line XX shown in FIG. 1, based on the conventional active-matrix substrate manufacturing method by the ion implantation method.

FIG. 7 is a process cross-sectional explanatory view showing a change in the cross-sectional structure during the manufacturing process according to the cross section taken along the line XX shown in FIG. 1, based on the conventional method for manufacturing an active matrix substrate by the ion implantation method.

[Explanation of symbols]

 1 glass substrate 2 gate electrode 3 gate insulating film 4 semiconductor layer 5 channel protective insulating film 6 contact layer 6a first contact layer 6b second contact layer 7 source electrode 7a lower layer source electrode 7b upper layer source electrode 8 drain electrode 8a lower layer drain Electrode 8b Upper layer drain electrode 9 Pixel electrode 10 Conductive reaction layer 11 n-Si semiconductor film 12 Resist pattern 13 Space part

Claims (7)

[Claims] 1. A gate electrode, a semiconductor layer, a drain electrode, a source electrode and a pixel electrode are provided on an insulating substrate, and (a) a gate insulating film is provided so as to cover the gate electrode. The semiconductor layer is provided in the same region as the gate electrode, which is an upper layer of the gate electrode through a film, and further, a channel protective insulating film having a surface area smaller than the surface area of the semiconductor layer is formed. The semiconductor layer is provided in a central portion on the semiconductor layer so that the semiconductor layer is exposed on both sides of the channel protection insulating film, and (b) the pixel electrode is on the gate insulating film and the gate It is provided in a region different from the region of the electrode, and (c) of the regions of the semiconductor layer not covered by the channel protective insulating film, the region closer to the pixel electrode is the first electrode. Contact layer, and a region far from the pixel electrode is a second contact layer,
(D) The drain electrode is composed of two layers, and the lower layer drain electrode is formed on a portion of the channel protective insulating film near the pixel electrode, the first contact layer, and the first contact layer of the gate insulating film. The upper layer drain electrode is provided so as to cover the entire surface of the lower layer drain electrode, and (e) the source electrode is 2
The lower layer source electrode is provided so as to cover a part of a portion of the channel protection insulating film remote from the pixel electrode, a portion of the second contact layer and a portion of the gate insulating film near the second contact layer. A method for manufacturing an active matrix substrate using a thin film transistor, which is provided as an upper layer source electrode covering the entire surface of the lower layer source electrode, as a switching element, and is used for patterning the first and second contact layers. A method of manufacturing an active matrix substrate, wherein etching is performed so that side etching is formed in the semiconductor layer below the channel protective insulating film. 2. The method for manufacturing an active matrix substrate according to claim 1, wherein the etching process is a plasma etching process using SF ₆ gas. 3. The first and second contact layers are n
The method of manufacturing an active matrix substrate according to claim 2, wherein the n-type silicon film is formed by doping a silicon film with phosphorus. 4. The method for manufacturing an active matrix substrate according to claim 1, wherein the etching process is a plasma etching process using CF ₄ gas. 5. The first and second contact layers are n
5. The method of manufacturing an active matrix substrate according to claim 4, wherein the n-type silicon film is a silicon film, and the n-type silicon film is formed by doping the silicon film with phosphorus. 6. The method for producing an active matrix substrate according to claim 1, wherein the etching process is a HNO ₃ —HF wet etching process. 7. The first and second contact layers are n
7. The method for manufacturing an active matrix substrate according to claim 6, wherein the n-type silicon film is a silicon film, and the n-type silicon film is formed by doping the silicon film with phosphorus.