KR100658057B1 - Method for fabricating tft - Google Patents
Method for fabricating tft Download PDFInfo
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- KR100658057B1 KR100658057B1 KR1020000029772A KR20000029772A KR100658057B1 KR 100658057 B1 KR100658057 B1 KR 100658057B1 KR 1020000029772 A KR1020000029772 A KR 1020000029772A KR 20000029772 A KR20000029772 A KR 20000029772A KR 100658057 B1 KR100658057 B1 KR 100658057B1
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- 238000000034 method Methods 0.000 title claims abstract description 45
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 68
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 25
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 25
- 239000010409 thin film Substances 0.000 claims abstract description 22
- 238000000151 deposition Methods 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 9
- 238000000137 annealing Methods 0.000 claims abstract description 8
- 230000002779 inactivation Effects 0.000 claims abstract description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 3
- 239000010408 film Substances 0.000 claims description 20
- 238000000059 patterning Methods 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 12
- 238000002161 passivation Methods 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 4
- 150000002739 metals Chemical class 0.000 claims description 2
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- 230000004913 activation Effects 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 13
- 238000001312 dry etching Methods 0.000 abstract description 11
- 238000001039 wet etching Methods 0.000 abstract description 4
- 230000008021 deposition Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 44
- 238000000206 photolithography Methods 0.000 description 12
- 239000004020 conductor Substances 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 229910004205 SiNX Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910021334 nickel silicide Inorganic materials 0.000 description 3
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000000415 inactivating effect Effects 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
Abstract
본 발명은 박막 트랜지스터의 제조 방법에 관한 것으로, 게이트 금속을 퇴적하고 사진 인쇄를 한 다음, 습식 또는 건식 에칭을 하는 단계, 비정질 실리콘 및 도핑된 비정질 실리콘으로 구성된 활성화층을 퇴적하고 사진 인쇄를 한 다음, 에칭을 하는 단계, 니켈/알루미늄/니켈로 구성된 소스/드레인 전극을 퇴적하고 사진 인쇄를 한 다음, 에칭을 하는 단계, 실리콘 질화물로 구성된 불활성화층을 퇴적하고 사진 인쇄를 한 다음, 에칭을 하는 단계, ITO 퇴적을 하고 사진 인쇄를 한 다음, 에칭을 하는 단계, 최종 어닐링을 수행하는 단계를 포함함을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor, comprising depositing a gate metal and performing photo printing, followed by wet or dry etching, depositing an active layer composed of amorphous silicon and doped amorphous silicon and performing photo printing. , Etching, depositing a source / drain electrode composed of nickel / aluminum / nickel and performing photo printing, then etching, depositing an inactivation layer made of silicon nitride, performing photo printing, and then etching And ITO deposition and photo printing, followed by etching and final annealing.
Description
도 1은 종래의 박막 트랜지스터의 제조 방법의 공정 순서를 도시한 흐름도.1 is a flowchart showing a process sequence of a conventional method for manufacturing a thin film transistor.
도 2는 본 발명에 따른 박막 트랜지스터의 구조를 나타낸 단면도.2 is a cross-sectional view showing the structure of a thin film transistor according to the present invention.
도 3은 본 발명에 따른 박막 트랜지스터의 제조 방법의 공정 순서를 도시한 흐름도.3 is a flowchart illustrating a process sequence of a method of manufacturing a thin film transistor according to the present invention.
본 발명은 박막 트랜지스터의 제조 방법에 관한 것으로, 특히 니켈/알루미늄 /니켈(Ni/Al/Ni) 다층을 박막 트랜지스터의 배열 공정에 응용한 박막 트랜지스터의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor, and more particularly, to a method for manufacturing a thin film transistor in which a nickel / aluminum / nickel (Ni / Al / Ni) multilayer is applied to an array process of a thin film transistor.
도 1은 종래의 박막 트랜지스터의 제조 방법의 공정 순서를 도시한 흐름도이다.1 is a flowchart illustrating a process procedure of a conventional method for manufacturing a thin film transistor.
도 1에 도시된 바대로, 종래의 박막 트랜지스터 액정표시장치의 제조방법은 절연 기판 상부에 금속막을 증착하고, 제 1 사진 식각 공정으로 게이트 전극 및 스토리지 전극을 형성하는 단계(S10), 상기 게이트 전극 배선이 형성된 절연 기판 상부에 게이트 절연막, 채널용 비정질 실리콘층, 도핑된 반도체층을 적층하는 단계(S 12), 상기 도핑된 반도체층과 비정질 실리콘층을 제 2 사진 식각 공정으로 패터닝하여, 박막 트랜지스터 영역을 한정하는 단계(S14), 상기 절연 기판 결과물 상부에 소스, 드레인용 금속막을 증착하는 단계(S16), 상기 소스, 드레인용 금속막을 제 3 사진 식각 공정에 의하여 비정질 실리콘층의 양측에 배치되도록 패터닝하여, 소스, 드레인 전극을 형성하는 단계(S18), 상기 소스, 드레인 전극을 마스크로 하여, 노출된 도핑된 반도체층을 식각하는 단계(S20), 상기 노출된 비정질 실리콘층을 1차 어닐링하는 단계(S22), 상기 소스, 드레인 전극이 형성된 절연 기판 상부에 패시베이션막을 증착하는 단계(S24), 상기 드레인 전극의 소정 부분이 노출되도록 제 4 사진 식각 공정에 의하여 패시베이션막을 식각하여, 비어홀을 형성하는 단계(S26), 상기 노출된 드레인 전극과 콘택되도록 투명 도전 물질을 증착하는 단계(S28), 상기 투명 도전 물질을 제 5 사진 식각 공정을 통하여 패터닝하여, 화소 전극을 형성하는 단계(S30), 상기 절연 기판 결과물을 2차 어닐링하는 단계(S32)를 포함한다.As shown in FIG. 1, a conventional method of manufacturing a thin film transistor liquid crystal display device includes depositing a metal film on an insulating substrate, and forming a gate electrode and a storage electrode by a first photolithography process (S10). Stacking a gate insulating layer, an amorphous silicon layer for a channel, and a doped semiconductor layer on the insulating substrate on which the wiring is formed (S 12), and patterning the doped semiconductor layer and the amorphous silicon layer by a second photolithography process to form a thin film transistor. Defining a region (S14), depositing a source and drain metal film on the insulating substrate resultant (S16), and disposing the source and drain metal film on both sides of an amorphous silicon layer by a third photolithography process. Patterning to form a source and a drain electrode (S18), using the source and drain electrodes as a mask, and exposing the exposed doped semiconductor layer (S20), first annealing the exposed amorphous silicon layer (S22), depositing a passivation film on an insulating substrate on which the source and drain electrodes are formed (S24), and a predetermined portion of the drain electrode is exposed. Etching the passivation layer by a fourth photolithography process to form a via hole (S26), depositing a transparent conductive material to contact the exposed drain electrode (S28), and etching the transparent conductive material to a fifth photolithography process Patterning through a process to form a pixel electrode (S30); and performing a second annealing of the insulating substrate result (S32).
그런데, 종래에는, 건식 에칭 공정시, Mo/Al/Mo 데이터 라인을 사용할 경우, SF6 가스에 대한 상부 몰리브덴(Mo) 과 불활성화인 SiNx 의 선택도가 좋지 않아 배열 및 셀 공정시 다량의 결함이 발생할 가능성이 있다. However, conventionally, when the Mo / Al / Mo data line is used in the dry etching process, the selectivity of the upper molybdenum (Mo) and the inert SiNx to SF 6 gas is not good, so that a large amount of defects during the arrangement and cell processes This is likely to occur.
또한, SiNx 의 선택도가 우수한 알루미늄을 단일 층으로 사용할 경우, 힐럭 (hillock) 이나 일렉트로 마이그레이션 (electromigration) 등이 발생하여 소자 특성을 저하시키게 된다.In addition, when aluminum having excellent selectivity of SiNx is used as a single layer, hillock, electromigration, or the like occurs, thereby degrading device characteristics.
그리고, 종래에는, n+a-Si 상에 매우 낮은 오옴 접촉 저항을 갖는 니켈-실리사이드(Ni-siliClde)를 생성시키기 위하여 n+a-Si 상에 별도의 극박막(수∼수십 Å)의 니켈을 증착한후, 열처리하여 니켈-실리사이드를 형성시켰다.In the related art, in order to produce nickel-silicide (Ni-siliClde) having a very low ohmic contact resistance on n + a-Si, a separate ultrathin film (tens of tens of kPas) of nickel is formed on n + a-Si. After deposition, heat treatment was performed to form nickel-silicide.
하지만, 이 종래 방법은 추가적으로 잔여 니켈을 제거하여 후속 공정을 진행해야 하므로 차후의 니켈 잔여물이 남는등 많은 문제점을 안고 있다.However, this conventional method has many problems, such as the need for further removal of residual nickel, and subsequent nickel residues.
또한, 현재의 역 스태거드 TFT 배열(Staggered TFT Array) 공정에서의 데이터 라인(Mo/Al/Mo) 은 각각 하부로는 n+a-Si 과, 상부로는 인듐 주석 산화막(Indiu -m Tin Oxide, 이하, ITO 막이라 함)과 접촉한 구조이다. 이 데이터 라인의 스택에서 n+a-Si 은 몰리브덴(Mo) 과 접촉하게 되어 비교적 높은 오옴 접촉 저항을 갖게 된다.In addition, in the current staggered TFT array process, the data lines (Mo / Al / Mo) are respectively n + a-Si at the bottom and indium tin oxide (Indiu-m Tin) at the top. Oxide, hereinafter referred to as ITO film). In this stack of data lines, n + a-Si comes into contact with molybdenum (Mo), resulting in a relatively high ohmic contact resistance.
그리고, 이 계면에 미세한 결함이 존재할 경우, 더 높은 오옴 접촉 저항값을 갖게 되어 화소의 결함등을 야기시켜 생산율을 저하시키는 원인이 되기도 한다.In addition, when a minute defect exists in this interface, it will have higher ohmic contact resistance value, causing a defect of a pixel, etc., and it may become a cause which lowers a production rate.
본 발명은 상기 문제점을 해소하기 위해 안출된 것으로, 니켈/알루미늄/니켈 (Ni/Al/Ni) 다층을 박막 트랜지스터의 배열 공정에 응용한 박막 트랜지스터의 제조 방법을 제공함에 그 목적이 있다.The present invention has been made to solve the above problems, and an object thereof is to provide a method of manufacturing a thin film transistor in which a nickel / aluminum / nickel (Ni / Al / Ni) multilayer is applied to an array process of a thin film transistor.
상기 목적을 달성하기 위한 본 발명에 따른 박막 트랜지스터의 제조 방법은 기판 상에 게이트 금속을 퇴적하고 패터닝하여 게이트 전극을 하는 단계, 상기 기판 상에 게이트 전극을 덮도록 게이트 절연막을 형성하고 상기 게이트 절연막 상에 불순물이 도핑되지 않은 비정질 실리콘과 불순물이 도핑된 비정질 실리콘으로 구성된 활성화층을 적층하고 상기 게이트 전극과 대응하는 부분이 잔류하도록 사진 인쇄 및 에칭에 의해 패터닝하여 채널층과 반도체층을 형성하는 단계, 상기 게이트 절연막 상에 상기 반도체층과 접촉되며 상층 및 하층에 니켈을 포함하는 다층의 소스/드레인 금속을 증착하고 패터닝하여 소스/드레인 전극을 형성하는 단계, 상기 게이트 절연막 상에 실리콘질화물로 구성된 불활성화층을 상기 소스/드레인 전극을 덮도록 증착하고 패터닝하여 상기 드레인 전극을 노출시키는 접촉홀을 형성하는 단계, 상기 불활성화층 상에 상기 접촉홀을 통해 상기 드레인 전극과 접촉되게 ITO막을 증착하고 패터닝하여 화소전극을 형성하는 단계, 최종 어닐링을 300℃ 정도의 온도로 수행하여 상기 소스/드레인 전극을 이루는 상기 하층의 니켈과 상기 반도체층 사이에 오옴 접촉을 이루도록 실리사이드층을 형성하는 단계를 포함한다.According to an aspect of the present invention, there is provided a method of manufacturing a thin film transistor, in which a gate electrode is formed by depositing and patterning a gate metal on a substrate, forming a gate insulating film to cover the gate electrode on the substrate, and forming a gate electrode on the gate insulating film. Forming a channel layer and a semiconductor layer by laminating an activating layer composed of amorphous silicon not doped with impurities and amorphous silicon doped with impurities, and patterning by photo printing and etching so that a portion corresponding to the gate electrode remains; Depositing and patterning a plurality of source / drain metals including nickel on and in contact with the semiconductor layer on the gate insulating layer to form a source / drain electrode, and inactivating silicon nitride on the gate insulating layer A layer is deposited to cover the source / drain electrodes Patterning to form a contact hole exposing the drain electrode, depositing and patterning an ITO film in contact with the drain electrode through the contact hole on the inactivation layer to form a pixel electrode, and final annealing at 300 ° C. And forming a silicide layer to form ohmic contact between the lower layer of nickel forming the source / drain electrode and the semiconductor layer.
이하, 본 발명의 바람직한 실시예를 첨부 도면들을 참조하여 상세히 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명에 따른 박막 트랜지스터의 구조를 나타낸 단면도이다.2 is a cross-sectional view showing the structure of a thin film transistor according to the present invention.
도 3은 본 발명에 따른 박막 트랜지스터의 제조 방법의 공정 순서를 도시한 흐름도이다.3 is a flowchart illustrating a process sequence of a method of manufacturing a thin film transistor according to the present invention.
본 발명에 따라 제안된 니켈/알루미늄/니켈(Ni/Al/Ni) 다층을 박막 트랜지스터의 배열 공정에 응용할 경우, 그 공정 순서는 다음과 같다.When the nickel / aluminum / nickel (Ni / Al / Ni) multilayer proposed according to the present invention is applied to an array process of a thin film transistor, the process sequence is as follows.
도 3에 도시된 바대로, 본 발명에 따른 박막 트랜지스터의 제조 방법은 유리기판(11) 상에 게이트 금속을 퇴적하고 습식 또는 건식 에칭을 포함하는 포토리쏘그래피 방법으로 패터닝하여 게이트전극(21)을 형성하는 단계(S10), 상기 유리기판(11) 상에 게이트전극(21)을 덮도록 게이트절연막(31), 식각 보호막(41), 채널용 비정질 실리콘층(61) 및 도핑된 비정질 실리콘층(81)을 순차적으로 적층하고 게이트전극(21)과 대응하는 부분에 잔류되게 게이트절연막(31)이 노출되도록 포토리쏘그래피 방법으로 패터닝하여 박막 트랜지스터의 활성 영역을 한정하는 단계(S20), 상기 게이트절연막(31) 상에 도핑된 비정질 실리콘층(81)과 접촉되는 소스 및 드레인용 금속막을 증착하고 게이트 전극(21)과 대응하는 부분이 이격되게 패터닝하여 소스 및 드레인전극(71)을 형성하면서 이 소스 및 드레인 전극(71)을 마스크로 하여 노출된 도핑된 비정질 실리콘층(81)을 식각하는 단계(S30), 게이트 절연막(31) 상에 소스 및 드레인전극(71)을 덮는 패시베이션막(91)을 증착하고 드레인 전극(71)의 소정 부분이 노출되도록 포토리쏘그래피 방법으로 패터닝하여 비어홀을 형성하는 단계(S40), 상기 패시베이션막(91) 상에 비어홀에 의해 노출된 드레인 전극(71)과 콘택되도록 투명 도전 물질을 증착하고 포토리쏘그래피 방법으로 패터닝하여 화소 전극(51)을 형성하는 단계(S30), 최종 어닐링을 수행하는 단계(S60)를 포함한다.As shown in FIG. 3, in the method of manufacturing the thin film transistor according to the present invention, the
상기한 바와 같이 구성되는 본 발명의 작용을 상세히 설명하면 다음과 같다.Referring to the operation of the present invention configured as described in detail as follows.
먼저, 단계(S10)을 참조하면, 유리기판(11) 상에 게이트 금속을 퇴적하고 습식 또는 건식 에칭을 포함하는 포토리쏘그래피 방법으로 패터닝하여 게이트 전극(21)을 형성한다. 이 경우, 게이트 금속으로 니켈/알루미늄/니켈(Ni/Al/Ni) 또는 알루미늄/니켈(Al/Ni) 을 사용할 수 있다.First, referring to step S10, the gate metal is deposited on the
그 다음으로, 단계(S20)을 참조하면, 유리기판(11) 상에 게이트전극(21)을 덮도록 산화막 및 질화막을 연속 증착하여 게이트절연막(31) 및 식각 보호막(41)을 형성한다. 그리고, 식각 보호막(41) 상에 채널로 사용되는 비정질 실리콘층(61)과 오믹접촉층으로 사용되는 도핑된 비정질 실리콘층(81)을 순차적으로 적층하고 게이트전극(21)과 대응하는 부분에 잔류되게 게이트절연막(31)이 노출되도록 식각 보호막(41)과 함께 포토리쏘그래피 방법으로 패터닝하여 박막 트랜지스터 영역을 한정한다.Next, referring to step S20, an oxide film and a nitride film are continuously deposited on the
단계(S30)을 참조하면 게이트 절연막(31) 상에 도핑된 비정질 실리콘층(81)을 덮도록 소스 및 드레인 금속을 증착하고 패터닝하여 비정질 실리콘층(81)과 오믹 접촉을 이루는 소스 및 드레인전극(71)을 형성한다. 이 때, 소스 및 드레인전극(71)은 게이트 전극(21)과 대응하는 부분이 이격되게 패터닝하면서 이 부분의 도핑된 비정질 실리콘층(81)도 식각한다.
상기에서 소스 및 드레인 금속으로 Ni/Al/Ni를 사용한다. 여기서, 소스 및 드레인 전극(71)을 형성하기 위한 에칭 공정은 상온 50℃ 에서 습식 에칭 공정이나 Cl 계열의 가스를 사용한 건식 에칭 공정이 모두 가능하다.Referring to step S30, the source and drain electrodes are deposited and patterned to cover the doped
Ni / Al / Ni is used as the source and drain metal. Here, the etching process for forming the source and
단계(S40)을 참조하면, 게이트 절연막(31) 상에 소스 및 드레인전극(71)을 덮는 패시베이션막(91)을 증착하고 드레인 전극(71)의 소정 부분이 노출되도록 건식 에칭을 포함하는 포토리쏘그래피 방법으로 패터닝하여 비어홀을 형성한다. 이때, 비어홀을 형성하기 위한 패시베이션막(91)의 건식 에칭시 소스 가스로는 주로 SF6를 사용하는데, 소스 및 드레인전극(71)을 이루는 니켈은 SF6 가스에 에칭 또는 어택(attack)을 받지 않으므로 우수한 건식 에칭 선택도를 얻게 되어 충분한 공정 마진을 얻을 수 있다.Referring to step S40, a photolithography comprising a
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단계(S50)를 참조하면, 상기 패시베이션막(91) 상에 비어홀에 의해 노출된 드레인 전극(71)과 콘택되도록 ITO 등의 투명 도전 물질을 증착하고 포토리쏘그래피 방법으로 패터닝하여 화소 전극(51)을 형성한다. 이 때, 드레인 전극(71)을 구성하는 니켈은 투명 도전 물질인 ITO의 식각액에 대한 화학적 내구성이 높으므로 ITO 에칭시 어택에 기인하는 데이터 개방 등의 결함을 방지할 수 있다.Referring to step S50, a transparent conductive material such as ITO is deposited on the
그후, 단계(S60)을 참조하면, 최종 어닐링을 수행한다. 그 결과, 소스 및 드레인 전극(71)의 하층인 니켈과 도핑된 비정질 실리콘층(81)의 계면의 오믹 특성을 향상시킨다. 상기에서 최종 어닐링 공정시 온도가 300℃ 정도로 수행할 수 있는 데, 이 경우, 소스 및 드레인 전극(71)의 하층인 니켈과 도핑된 비정질 실리콘층(81)의 계면에 매우 낮은 오옴 접촉 저항을 갖는 니켈-실리사이드(Ni-siliClde)가 형성된다.Thereafter, referring to step S60, final annealing is performed. As a result, the ohmic characteristics of the interface between the nickel, which is the lower layer of the source and
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본 발명의 다른 실시예를 간략하게 설명하면 다음과 같다.Briefly described another embodiment of the present invention.
F 계열의 가스를 에칭 가스로 사용하는 건식 에칭 공정에서, SiNx, Si, SiON 등과 금속 전극의 우수한 선택도의 구현을 위해 니켈(Ni) 박막 전극을 사용한다.In a dry etching process using an F-based gas as an etching gas, a nickel (Ni) thin film electrode is used to realize excellent selectivity of SiNx, Si, SiON and the like.
그리고, 데이터 라인 건식 에칭, 건식 에칭시 우수한 선택도를 이용하여 4 마스크 공정에 적용될 수 있다. 또한, TFT 또는 반도체 공정에서 우수한 전기 전도도와 오옴 접촉, 우수한 선택도를 갖는 대체 전극 물질로 사용될 수 있다. In addition, the data line may be applied to a four mask process using excellent selectivity in dry etching and dry etching. It can also be used as a substitute electrode material with good electrical conductivity, ohmic contact, and good selectivity in TFT or semiconductor processes.
상기한 바와 같이, 본 발명은 건식 에칭시 에칭 마진과 최적의 에칭 비법을 확보함으로써, 공정 기술의 축적, 생산율등 다양한 효과를 얻을 수 있고, 4 마스크 공정에서 우수한 에칭 공정 마진의 확보가 가능한 효과가 있다.As described above, according to the present invention, by securing the etching margin and the optimal etching method in dry etching, various effects such as accumulation and production rate of the process technology can be obtained, and the effect of securing excellent etching process margin in the four mask process is obtained. have.
그리고, 본 발명은 반도체 공정에서 SF6 를 에칭 가스로 사용하는 공정에서 Ni/Al/Ni 박막 전극을 사용함으로써 매우 우수한 선택도와 전기 전도도를 얻을 수 있고, 반도체 공정에서 실리콘/금속 전극의 계면 특성의 향상과 저저항의 전극의 구현을 위하여 사용될 수 있는 효과가 있다.In addition, the present invention can obtain very good selectivity and electrical conductivity by using Ni / Al / Ni thin film electrode in the process using SF 6 as the etching gas in the semiconductor process, and the interface characteristics of the silicon / metal electrode in the semiconductor process There is an effect that can be used for the improvement and implementation of low resistance electrodes.
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| JPH01217422A (en) * | 1988-02-26 | 1989-08-31 | Seikosha Co Ltd | Amorphous silicon thin film transistor array substrate |
| JP2740813B2 (en) * | 1988-02-26 | 1998-04-15 | セイコープレシジョン株式会社 | Amorphous silicon thin film transistor array substrate |
| JPH0456136A (en) * | 1990-06-22 | 1992-02-24 | Nippon Telegr & Teleph Corp <Ntt> | Forming method of thin film for wiring |
| JP2000101091A (en) * | 1998-09-28 | 2000-04-07 | Sharp Corp | Thin film transistor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100927585B1 (en) * | 2008-03-05 | 2009-11-23 | 삼성모바일디스플레이주식회사 | Organic light emitting display |
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| Publication number | Publication date |
|---|---|
| KR20010108833A (en) | 2001-12-08 |
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