KR20020055787A - Array Panel used for a Liquid Crystal Display and method for fabricating the same - Google Patents

Abstract

PURPOSE: An array substrate of a liquid crystal display and a method of fabricating the array substrate are provided to form a channel of the array substrate through one-time etching process so as to reduce the number of fabrication processing steps. CONSTITUTION: A gate electrode is formed on a transparent substrate(1). A gate insulating layer, an amorphous silicon layer(144a), an impurity-doped amorphous silicon layer and a metal layer strongly combined with fluorine are sequentially formed on the gate electrode. The impurity-doped amorphous silicon layer and the metal layer are patterned through photolithography, to form source and drain electrodes, a data line and a channel exposing a predetermined portion of the amorphous silicon layer. A passivation layer is formed on the substrate including the source and drain electrodes, and an active layer is formed on the passivation layer. A pixel electrode is formed on the substrate including the passivation layer. The channel is formed in a manner that a portion of the metal layer, placed between the source and drain electrodes, is etched using a mixture of gases containing F, Cl and oxygen and a portion of the impurity-doped amorphous silicon layer, placed between the source and drain electrodes, is etched using a mixture of gases containing F and Cl.

Description

Array substrate for liquid crystal display device and manufacturing method thereof {Array Panel used for a Liquid Crystal Display and method for fabricating the same}

The present invention relates to an array substrate for a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device having a four mask structure and a manufacturing method thereof.

The driving principle of the liquid crystal display device is to use the optical anisotropy and polarization property of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

In the current flat panel display field, active matrix liquid crystal display (AMLCD) is the mainstream. In an AMLCD, a thin film transistor (TFT) is used as a switching element to change the transmittance of a pixel by adjusting a voltage applied to a liquid crystal of one pixel.

Hydrogenated amorphous silicon (Amorphous-Silicon: H; hereinafter abbreviated as amorphous silicon (a-Si)) is mainly used as the switching device, which is easy to manufacture in large areas, high in productivity, and low in 350 ° C or lower. This is because it is possible to use a low-cost glass substrate because it can be deposited at a substrate temperature.

The following description will be made of an array substrate for a liquid crystal display device including such an amorphous silicon thin film transistor element.

The array substrate for the liquid crystal display device is formed through a mask process.

The mask process refers to a series of processes for fabricating a separate mask and patterning each layer (insulating layer, active layer, metal layer) in an arbitrary form through etching by a photolithography process.

Recently, research has been actively conducted on a method of manufacturing an array substrate for a liquid crystal display device by a four mask process.

Conventionally, the 5 mask process is mainly used, but if the mask process is reduced, the process cost can be considerably reduced and the process time can be shortened, thereby reducing the incidence of defects.

1 is a schematic flowchart of a manufacturing process of an array substrate for a general four mask liquid crystal display.

ST1 is a gate process, in which a metal material suitable for low resistance wiring is deposited on a transparent substrate, and then patterned by a photolithography process using a first mask to form a gate wiring including a gate electrode and a capacitor electrode. Step.

The metal material is made of any one metal of aluminum, an aluminum alloy, or a double metal layer including aluminum.

ST2 is a channel and data process, in which a gate insulating film, an amorphous silicon (a-Si), an impurity amorphous silicon (n + a-Si), and a metal layer are sequentially deposited on a substrate on which the gate wiring is formed, and then a second mask is used. Thereby forming a channel on which the source and drain electrodes, the data wiring ohmic contact layer, and the thin film transistor are turned on and off.

The ohmic contact layer is a pattern of impurity amorphous silicon, and is an ion doped amorphous silicon to increase electron mobility, and serves to lower contact resistance between amorphous silicon and the metal layer.

As the metal material, molybdenum (Mo), chromium (Cr), tungsten (W), nickel (Ni), etc., which have high chemical corrosion resistance and high mechanical strength, are mainly used.

On the other hand, the step of forming a secondary capacitor electrode forming a storage capacitance (C _ST ) with the capacitor electrode with the data wiring metal.

In this case, the auxiliary capacitor electrode is connected to the pixel electrode to be formed later and is driven by applying a voltage.

ST3 is a protective layer and an active layer process. In this step, an active layer is formed using a third mask, and in other portions, the active layer is etched from the protective layer to the active layer.

In this step, the step of forming a separate contact hole on the protective layer is omitted, and in the subsequent process, the pixel electrode is characterized in that the side contact with the source electrode and the auxiliary capacitor electrode, respectively.

The protective layer is formed to prevent damage or deterioration of the thin film transistor caused by rubbing and moisture infiltration during the rubbing or conveyance in the liquid crystal cell process of the liquid crystal display device which is performed after the array process. It is made of BCB (BenzoCycloButene), which is an insulating film.

ST4 is a pixel process, in which a transparent conductive material is deposited on a substrate having undergone the ST3 step, and then a pixel electrode is formed using a fourth mask.

As the transparent conductive material, indium tin oxide (ITO) having low resistance at the time of tap bonding (TAB) for connection with an external circuit in a later process or a metal is mainly used.

FIG. 2 is a plan view of a portion of an array substrate for a general four mask liquid crystal display. FIG.

As illustrated, the liquid crystal display array substrate 35 includes a gate wiring 44 including a gate electrode 40 and a capacitor electrode 54 and a data wiring 48 including a drain electrode 46. The pixel electrode is formed to cross each other, and the source electrode 50 is formed to be spaced apart from the drain electrode 46 by a predetermined distance, and connected to the source electrode 50, and partially overlapped with the capacitor electrode 54. 52 is formed.

An auxiliary capacitor electrode 56 connected to the pixel electrode 52 is further included between the capacitor electrode 54 and the pixel electrode 52.

In this case, the pixel electrode 52 is in side contact with the source electrode 50 and the auxiliary capacitor electrode 56 without a separate contact hole.

Meanwhile, the source and drain electrodes 50 and 46 and the gate electrode 50 are included to form a thin film transistor T, and the thin film transistor T region is disposed between the source electrode 50 and the drain electrode 46. The channel ch exposing the active layer, not shown, is formed in the section.

Since the channel (ch) plays a role of switching on / off voltage, the etching process for forming the channel (ch) is the most important process that determines the electrical characteristics of the thin film transistor.

The present specification relates to an etching method accompanying a channel forming step in an array substrate for a liquid crystal display device having such a four mask structure.

Hereinafter, an etching method of the array substrate for the liquid crystal display device will be described in detail.

The etching method may be largely classified into wet etching and dry etching.

Wet etching is inexpensive and has high productivity, but has the disadvantage of lowering the precision of etching compared to dry etching.Wet etching is faster than the wet etching and can etch fine shapes. The reaction takes place at, so it has a safe advantage.

For dry etching, a dry etching method using plasma is mainly used. In order to proceed with the etching process, first, a reaction gas is injected into the dry etching apparatus, and high frequency power is applied to the upper and lower electrodes in the dry etching apparatus from the outside. The electrons accelerated by the high frequency electric field formed between the upper and lower electrodes undergo high collisions with the reaction gas molecules to obtain high energy, and then inelastic collision with the reaction gas molecules to ionize and excite the reaction gas molecules to generate plasma. . Among these plasma gases, the plasma gas having a negative characteristic moves to the lower electrode by the potential difference between the upper and lower electrodes, and reacts with the dry etching member loaded on the lower electrode, and has a high vapor pressure. The etching process proceeds by producing volatiles.

As such, the liquid crystal display device material patterned by dry etching is mainly a semiconductor film, an insulating film, a metal film, or the like, and a separate mask is fabricated in each step, and after the photolithography process, any one of the aforementioned etching methods is used. By selecting a method, each layer (insulating layer, semiconductor layer, conductive metal layer, etc.) is patterned in an arbitrary form.

3A to 3D are cross-sectional views illustrating the cross-section taken along the cutting line A-A of FIG. 2 in stages of the manufacturing process, and in particular, the channel forming process.

In FIG. 3A, a step before forming the channel layer is illustrated. A gate electrode 40 is formed on the transparent substrate 1, and the gate insulating layer 42 and the amorphous silicon layer a are formed on the gate electrode 40. -Si) 44a, impurity amorphous silicon (n + a-Si; hereafter abbreviated as n + layer) layer 44b, and metal layer 45 are deposited in this order.

In this case, aluminum neodium (AlNd) / molybdenum (Mo) is mainly used as the gate electrode 40, and at this time, aluminum neodium is used as the lower layer in contact with the transparent substrate 1.

In FIG. 3B, as a first etching step of forming a channel through the process of FIG. 3A, the metal for source and drain electrodes of the channel part I is etched.

Wet etching is mainly used as an etching method of the metal layer 45. Since the wet etching etchant can selectively etch according to the properties of the material, the n + layer 44b forming the lower layer is not etched. Will remain.

That is, in this step, only the metal layer 45 is etched in the channel portion I through wet etching, and the source and drain electrodes 50 and 46 and the data line 48 are formed at the same time.

3C is a step of forming a channel ch by etching the n + layer 44b of the channel part (I of FIG. 3B) through the step of FIG. 3B.

In this step, the n + layer 44b is etched using a dry etching method suitable for forming a fine pattern compared to wet etching.

The reason why the n + layer 44b is etched in the channel ch is because the channel ch switches on / off of the voltage. When the n + layer 44b is not etched because the electron mobility is high, This is because it prevents the switching of the channel ch.

The main reaction gas for etching the n + layer 44b may be SF ₆ , and F (fluorine) ions in the reaction gas react with the silicide of the n + layer 44 b to react with the n + layer 44 b. ) Is etched.

At this time, in order to completely etch the n + layer 44b, there is no selective etching ratio between the n + layer 44b and the amorphous silicon 44a, and thus overetches a part of the amorphous silicon layer 44a.

FIG. 3D illustrates an amorphous silicon layer (44a of FIG. 3A) formed through a protective layer and an active layer process, which is a third mask process, to form an active layer after the process of FIG. 3C, and a pixel process, which is a fourth mask process. Together, the steps of forming the pixel electrode are illustrated.

At this time, the protective layer 51 and the active layer 47a are collectively etched except for the region where the active layer 47a is formed in the passivation layer 51 and the active layer 47a process. It is connected to the source electrode 50 by the side contact method, characterized in that formed on the gate insulating film 42.

Up to now, the manufacturing process of the array substrate for a four-mask liquid crystal display device has been examined. As a result, the process is performed twice using different etching methods to form the channel in the channel and data forming process, which are the second mask process. There is a problem that the process time is long.

In particular, it is very important to simplify the process because a long etching process is likely to cause defects in the thin film transistor (T) device.

In order to solve the above problems, an object of the present invention is to form a channel of an array substrate for a liquid crystal display device according to the four mask process in one etching process, thereby reducing the number of processes to reduce the defective rate.

1 is a schematic flowchart of a manufacturing process of an array substrate for a general four mask liquid crystal display;

FIG. 2 is a plan view of a portion of an array substrate for a general four mask liquid crystal display; FIG.

3A to 3D are cross-sectional views illustrating the cross section taken along the cutting line A-A of FIG.

4 is a schematic plan view of a portion of an array substrate for a four mask liquid crystal display according to the present invention;

Figures 5a to 5d is a cross-sectional view showing a cross-section cut along the cutting line B-B of Figure 4 step by step manufacturing process.

<Description of Symbols for Main Parts of Drawings>

144a: amorphous silicon layer 144b: impurity amorphous silicon layer

146: drain electrode 148: data wiring

150 source electrode T thin film transistor

CH: Channel

In order to achieve the above object, the present invention comprises the steps of providing a transparent substrate; Forming a gate electrode on the substrate; Depositing a gate insulating film, an amorphous silicon layer, an impurity amorphous silicon layer, and a metal layer having strong bonding force with F (Fluorine) on the gate electrode in order; Patterning the impurity amorphous silicon layer and the metal layer by a photolithography process to form a source and drain electrode, a data line, and a channel partially exposing the amorphous silicon layer; Depositing a protective layer on the substrate on which the source and drain electrodes are formed, and forming an active layer; Forming a pixel electrode on the substrate on which the active layer is formed, and in the forming of the channel, by mixing gases including F, Cl, and oxygen (O ₂ ), the source and drain electrodes Etching the metal layer between the sections; A method of manufacturing an array substrate for a liquid crystal display device comprising mixing a gas including F and Cl to etch an impurity amorphous silicon layer in a section between the source and drain electrodes.

The reaction gas in the etching of the metal material is a mixture of gases including SF ₆ , 0 ₂ , He, HCl, respectively, and the reaction gas in the etching of the impurity amorphous silicon layer is SF ₆ , HCl, He, respectively. It will mix the gas containing.

The metal material is formed of any one of molybdenum (Mo), chromium (Cr), nickel (Ni), tungsten (W), and titanium (Ti), and etching the impurity amorphous silicon in the step of etching the impurity amorphous silicon layer. The thickness is 350 to 900 kPa including a part of the amorphous silicon.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

4 is a schematic plan view of a portion of an array substrate for a four mask liquid crystal display according to the present invention.

As shown in the drawing, the gate substrate 144 including the gate electrode 140 and the capacitor electrode 154 is formed in the array substrate 130 of the liquid crystal display device in a first direction, and is perpendicular to the first direction. The data line 148 including the drain electrode 146 is formed in the second direction, and the source electrode 150 is formed to be spaced apart from the drain electrode 146 by a predetermined distance, and the source electrode 150 is formed. And a pixel electrode 152 overlapping the capacitor electrode 154 by a predetermined interval.

In addition, an auxiliary capacitor electrode 154 connected to the pixel electrode 152 is included between the capacitor electrode 154 and the pixel electrode 152.

In addition, the gate electrode 140, the source electrode 150, and the drain electrode 146 are included in the thin film transistor T, and the thin film transistor T includes a channel CH for switching voltage on / off. ) Is characterized in that the channel (CH) is made by a single dry etching process.

That is, the present invention is characterized by providing an array substrate for a liquid crystal display device with a simplified channel forming process.

5A to 5D are cross-sectional views illustrating the cross-section cut along the cutting line B-B of FIG. 4 in stages of the manufacturing process, in particular, focusing on the channel forming process.

In FIG. 5A, a gate electrode 140 is formed on the transparent substrate 1, and as shown in FIG. 5A, the gate insulating layer 142 and the amorphous layer are formed on the gate electrode 140. The silicon layer 144a (a-Si), the impurity amorphous silicon layer 144b (n + a-Si or less, abbreviated as n + layer), and the metal layer 145 are deposited in this order.

The material forming the metal layer 145 is characterized in that the metal (F) with a strong bonding force.

That is, when the metal layer is etched by the dry etching process, the metal having the above characteristics may be used to easily form a desired pattern.

Representative metals having the above properties include molybdenum (Mo), nickel (Ni), chromium (Cr), titanium (Ti), tungsten (W) and the like.

In FIG. 5B, the source and drain electrodes 150 and 146, the data line 148, and the metal layer 145 of the channel part II (145 of FIG. 5A) are removed by using the dry etching apparatus through FIG. 5A. .

That is, in this step, the substrate having passed through the step of FIG. 5A is seated in a dry etching apparatus having a gas injection hole (not _shown ), followed by mixing and injecting a gas including each of F, Cl, and oxygen (O ₂ ). The metal layer 145 of the portion (II) is etched.

In this case, as the mixed gas, it is preferable that the gas containing SF ₆ , O ₂ , He, and HCl is mixed in more detail.

The reaction gases in the mixed gas will be described in more detail as follows.

The ratio of SF ₆ and O ₂ is equal to or greater than 1: 4, while the metal atoms of the metal layer and the F ions react with each other, the O ₂ gas serves to etch a photoresist layer for a photolithography process, which is not shown. It lowers the amount of etching.

The He gas is a carrier gas, and the reaction gases ionized in the dry etching apparatus have a uniform density, and the HCl gas is formed in the pixel electrode part P during the etching process of the channel part II. The gate insulating layer 142 serves to prevent the etching.

In the process of etching the metal layer 145 in this step, the n + layer 144b constituting the lower layer may be partially etched from 0 to 200Å.

That is, in this step, the metal layer 145 must be completely removed to prevent etching defects due to metal foreign matter in the process of etching the n + layer 144b.

In FIG. 5C, after the etching process of FIG. 5B, the n + layer (144b of FIG. 5B) is etched in the same dry etching apparatus to form the channel CH and the ohmic contact layer 147b.

That is, in this step, after passing through the step of FIG. 5B, a gas including F and Cl, respectively, as a reaction gas of the n + layer (144b of FIG. 5B) is mixed and injected.

At this time, the mixed gas is preferably SF ₆ , HCl, He.

The F ion gas in the reaction gas reacts with the silicide of the n + layer (144b of FIG. 5B) to etch the n + layer (144b of FIG. 5B), and other gases are as described above.

In this step, it is important to completely remove the n + layer (144b in FIG. 5B) to expose the amorphous silicon layer 144a located below the n + layer (144b in FIG. 5B), so that this layer of amorphous silicon 144a is partially overeated. You are awesome.

That is, when the amorphous silicon layer 144a layer and the n + layer (144b of FIG. 5B) are deposited at 1500 to 1700 Å and about 300 Å in the initial deposition process, the etching thickness is preferably about 350 to 900 Å.

FIG. 5D illustrates the steps of forming the active layer 147a and the pixel electrode 152 through the above steps 3 and 4 of FIG. 1 after the step of FIG. 5C.

The pixel electrode 152 is formed on the gate insulating layer 142 and is in side contact with the source electrode 150.

That is, in the manufacturing process of the array substrate for a liquid crystal display device according to the present invention, a channel is formed by continuously etching the metal layer and the semiconductor layer of the channel part by a dry etching process.

Hereinafter, the etching method of the channel according to the present invention is not limited to the above embodiments, and various modifications may be made without departing from the spirit of the present invention.

As described above, according to the present invention, by simplifying the etching process associated with the channel that determines the electrical characteristics of the thin film transistor, it is possible to reduce the process time and lower the failure rate, it is possible to provide a liquid crystal display device with improved productivity.

Claims (5)

Providing a transparent substrate; Forming a gate electrode on the substrate; Depositing a gate insulating film, an amorphous silicon layer, an impurity amorphous silicon layer, and a metal layer having strong bonding force with F (Fluorine) on the gate electrode in order; Patterning the impurity amorphous silicon layer and the metal layer by a photolithography process to form a source and drain electrode, a data line, and a channel partially exposing the amorphous silicon layer; Depositing a protective layer on the substrate on which the source and drain electrodes are formed, and forming an active layer; In the step of forming a pixel electrode on the substrate on which the active layer is formed, In the forming of the channel, mixing a gas including F, Cl, and oxygen (O ₂ ) to etch a metal layer in a section between the source and drain electrodes; Etching the impurity amorphous silicon layer in the section between the source and drain electrodes by mixing a gas including each of F and Cl Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 1, The reaction gas in the step of etching the metal material is a manufacturing method of an array substrate for a liquid crystal display device which is a mixture of gases including SF ₆ , 0 ₂ , He, HCl. The method of claim 1, The reaction gas in the step of etching the impurity amorphous silicon layer is a method of manufacturing an array substrate for a liquid crystal display device comprising a mixture of gases including SF ₆ , HCl, He each. The method of claim 1, The metal material is molybdenum (Mo), chromium (Cr), nickel (Ni), tungsten (W), titanium (Ti) of any one of the array substrate manufacturing method for a liquid crystal display device. The method of claim 1, The etching thickness of the impurity amorphous silicon in the etching of the impurity amorphous silicon layer is 350 ~ 900 하여 including a portion of the amorphous silicon manufacturing method of an array substrate for a liquid crystal display device.