JPH11307780A - Manufacture for thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To raise reliability and considerably enhance productivity by a method wherein a metal conductive film is deposited on the entire face to be dry-etched and a source electrode and a drain electrode connected to an ohmic contact layer are formed. SOLUTION: By using a first resist mask 11 formed on an n<+> amorphous silicon film 5, the n<+> amorphous silicon film 5 and an amorphous silicon film 4 are sequently processed to form an insular amorphous silicon layer 13 and an n<+> amorphous silicon layer 14. The first resist mask 11 is changed to a second resist mask which is to be used as an etching mask, and a region where the n<+> amorphous silicon layer 14 is exposed is dry-etched to form an ohmic contact layer. Further, a surface of the amorphous silicon layer 13 is etched to form a channel excavation part. Next, the resist mask is removed, and a metal conductive film is deposited. The metal conductive film is processed to be in a predetermined shape to form a source electrode and a drain electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (TFT), and more particularly, to a thin film transistor (TF) used for a liquid crystal panel or the like.
The present invention relates to a method for manufacturing T.

[0002]

2. Description of the Related Art In the manufacture of TFTs used for liquid crystal panels and the like, in particular, inverted staggered type TFTs, a method of forming source and drain electrodes of the TFT is difficult and important from the viewpoint of mass production. Usually, this inverted stagger type TFT
Then, a channel dug-type TFT is formed. Such a technique is disclosed in, for example, Japanese Patent Application Laid-Open No. 5-33533.
No. 6 is described. Hereinafter, a method of manufacturing such a channel dug-type TFT will be described with reference to FIG. 7 as a conventional technique. FIG. 7 shows a conventional T of this kind.
It is sectional drawing of the FT manufacturing process order.

As shown in FIG. 7A, a gate electrode 102 is formed by patterning a metal such as chromium on an insulating substrate 101 which is a transparent insulating substrate. Then, a gate insulating film 103 is formed so as to cover the gate electrode 102. Thus, the amorphous silicon film 104 and the n ⁺ amorphous silicon film 105 are stacked and deposited.

[0004] Next, the n ⁺ amorphous silicon film 105 and the amorphous silicon film 104 are finely processed by photolithography and dry etching. Then, as shown in FIG. 7B, an island-shaped amorphous silicon layer 106 and an island-shaped n ⁺ amorphous silicon layer 107 are formed.

Next, as shown in FIG. 7C, a metal conductive film 108 is deposited by a sputtering method. Here, the metal conductive film 108 is formed on the gate insulating film 103, the amorphous silicon layer 106 and the n ⁺ amorphous silicon layer 107.
Formed on top. When chromium is used as the metal conductive film 108, the temperature at the time of sputtering is set to be about 200 ° C.

Next, the metal conductive film 108 is processed into a predetermined shape by a photolithography technique and a dry etching technique. Thus, the source electrode 109 and the drain electrode 110 are formed as shown in FIG. By processing the metal conductive film 108, the surface of the n ⁺ amorphous silicon layer 107 is exposed.

Next, using the source electrode 109 and the drain electrode 110 formed as described above as an etching mask, the exposed n ⁺ amorphous silicon layer 107 is dry-etched. Is dry-etched to form a channel dug portion 111.

In this way, as shown in FIG. 7E, the ohmic contact layer 109a on the source side and the ohmic contact layer 110a on the drain side are formed. Then, the gate electrode 102, the gate insulating film 103, the channel region formed in the amorphous silicon layer 106, the source electrode 109, and the drain electrode 1
The inverted staggered TFT having the number 10 is formed on the insulating substrate 101.

Further, although not shown, a passivation film is formed so as to cover the whole, and an inverted stagger type T
The manufacture of the FT ends.

[0010]

In the conventional technique described above, the conventional method of manufacturing an inverted staggered TFT has the following major problems. That is, FIG.
As described with reference to (d) and FIG. 7 (e), when dry etching the n ⁺ amorphous silicon layer 107 using the source electrode 109 and the drain electrode 110 as an etching mask, it is extremely difficult to control this etching. This is because, under the influence of the metal conductive film 108 formed over n ⁺ amorphous silicon layer 107, the interface between the n ⁺ amorphous silicon layer 107 and the metal conductive film 108 because the silicide layer is formed. Due to the silicide layer, the etching of the n ⁺ amorphous silicon layer 107 does not progress in the dry etching using a fluorine-based compound such as CF ₄ as a reaction gas. Thus, in the channel digging, the surface of the amorphous silicon layer 106 is roughened as shown in FIG.
The roughened channel dug portion 111 is formed.

[0011] Such a rough channel digging portion 11
When 1 is formed, band bending on the rough channel-shaped portion 111 is likely to occur at the interface between the passivation film and the amorphous silicon layer 106 described above. For this reason, the leak current between the source and the drain in the off state (non-operating state) of the TFT increases. That is, the off current increases.

A method for avoiding the above-described problem of the channel dug-in type TFT is disclosed in Japanese Patent Application Laid-Open No. 5-267341. However, the manufacturing method of this TFT is complicated, and the manufacturing cost is increased.

An object of the present invention is to provide a channel digging type TF.
An object of the present invention is to provide a highly reliable TFT by solving the above problems in the manufacture of T. Another object of the present invention is to provide a simple method of manufacturing a channel dug-in type TFT, and to greatly improve the productivity of an inverted stagger type TFT.

[0014]

SUMMARY OF THE INVENTION For this purpose, the T
The method of manufacturing an FT includes forming a gate electrode on an insulating substrate, covering the gate electrode, sequentially stacking and depositing a gate insulating film, a semiconductor thin film, and a semiconductor thin film containing high-concentration impurities; Etching the semiconductor thin film containing the high concentration impurity and the semiconductor thin film with the resist mask to form an island-shaped semiconductor layer; and processing the first resist mask to form a second resist mask Etching the surface of the island-shaped semiconductor layer with the second resist mask to form an ohmic contact layer and a channel dug portion; and removing the second resist mask and forming a metal conductive film over the entire surface. And performing dry etching to form a source electrode and a drain electrode connected to the ohmic contact layer. Here, the semiconductor thin film is an amorphous silicon film.

[0015] Then, the first film is formed of a resist film.
The cross-sectional shape of the resist mask is concave, and the resist film is formed so as to be thicker above the ohmic contact layer and thinner at the channel dug portion. Then, after forming the island-shaped semiconductor layer, anisotropic dry etching is performed on the first resist mask to form the second resist mask in which a resist film remains only above the ohmic contact layer. .

Alternatively, the first resist mask is composed of a resist film formed by laminating a first resist film and a second resist film in this order, and the second resist film is formed only on the ohmic contact layer. After the island-shaped semiconductor layer is formed, silicon is contained in the second resist film by a silylation process, and the silicon-containing second resist film is converted into a silicon oxide film by dry etching in oxygen gas. At the same time, the first resist film not covered with the second resist film is removed by etching to form the second resist mask in which the resist film remains only on the ohmic contact layer.

Further, a light-shielding portion and a semi-light-transmitting portion are formed in a mask pattern of a reticle used in the photolithography step, and the light-shielding portion and the semi-light-transmitting portion are transferred to a resist film to form the first resist A mask is formed.
The semi-transmissive portion is formed of a light-shielding pattern having a size equal to or smaller than the resolution limit.

As described above, in forming the inverted stagger type TFT, the channel dug portion is formed by using the resist mask as a dry etching mask instead of the metal conductive film. improves.

Further, the first resist mask is used to form TF
After forming the island-shaped semiconductor layer of T, the first resist mask is processed and converted into a second resist mask, and the channel excavation portion is formed using the second resist mask as a dry etching mask. Therefore, the manufacturing process is greatly simplified, and the productivity of the TFT is improved.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the present invention will be described with reference to FIG. 1, FIG. 2 or FIG. Here, FIGS. 1 and 2 are cross-sectional views in the order of manufacturing steps of the inverted staggered TFT of the present invention. FIG. 3 is a sectional view of a reticle used in the photolithography process of the present invention.

As shown in FIG. 1A, a gate electrode 2 is formed of a metal such as chromium on an insulating substrate 1 as described in the prior art. Then, a gate insulating film 3 is formed on the gate electrode 2. Thus, the amorphous silicon film 4 having a thickness of about 200 nm
And n ⁺ amorphous silicon film 5 having a thickness of about 60 nm
Are deposited and deposited.

Next, a positive resist film 6 is formed on the entire surface by a known photolithography technique. Here, the thickness of the resist film 6 is about 1 μm. Then, FIG.
A reticle 7 having a light shielding part 8 and a semi-light transmitting part 9 as shown in FIG.
The resist film 6 is exposed with the exposure light 10 using the mask as a mask. After this exposure, the resist film 6 is developed by an ordinary method.

An example of a reticle having such a light shielding portion and a semi-transparent portion will be described with reference to FIG. In FIG.
Three examples of such a reticle are shown in cross-section. In the example shown in FIG. 3A, a light-shielding portion 8 is formed in a predetermined pattern with, for example, chromium metal on a reticle substrate 7a, and a semi-transparent portion 9 is formed. Here, the semi-transmissive portion 9 is configured with a chromium metal pattern that is equal to or less than the exposure resolution limit. For example, rectangular patterns having a pattern width dimension equal to or smaller than the exposure wavelength are arranged at a predetermined pitch.
Alternatively, such a rectangular pattern is formed in a lattice shape. In this case, the transmission amount of the exposure irradiation light is set to be 20 to 80% in the area where the chromium metal pattern below the exposure resolution limit is formed. In this way, the semi-transparent portion 9 is formed.

In the example shown in FIG. 3B, the reticle substrate 7
A light-shielding portion 8 is formed in a predetermined pattern, for example, of chromium metal on a. Then, the chromium metal in the region to be the semi-transparent portion is etched to form the thin film portion 8a. In this case, the setting is made such that about half of the exposure irradiation light is transmitted in the region where the chromium metal thin film portion 8a is formed. In this way, a semi-transparent portion is formed.

In the example shown in FIG. 3C, the reticle substrate 7
A light shielding portion 8 is formed in a predetermined pattern, for example, of chromium metal on a. Then, the semi-transparent portion is formed by the halftone portion 9a. Here, the halftone section 9
a is formed of, for example, tungsten silicide.
In this way, a semi-transparent portion is formed.

As described above, a first resist mask, ie, a resist mask 11 is formed on the n ⁺ amorphous silicon film 5 as shown in FIG. Here, a resist concave portion 12 is formed in the resist mask 11. Note that the depth of the resist concave portion 12 is 700 nm.
Set to about. In the step shown in FIG.
2 is formed because the amount of light applied to the resist film 6 in the exposure / irradiation step is reduced because the above-described reticle is used.

Next, the above-mentioned n ⁺ amorphous silicon film 5 and amorphous silicon film 4 are formed using a resist mask 11 by a reactive ion etching (RIE) technique using a mixed gas of Cl ₂ and HBr as a reaction gas. Process sequentially. Then, as shown in FIG. 1C, an island-shaped semiconductor layer, that is, an island-shaped amorphous silicon layer 13 and an island-shaped n ⁺ amorphous silicon layer 14 are formed.

[0028] Next, S traces to O ₂ in the state of FIG. 1 (c)
RIE is performed in a reaction gas to which F ₆ has been added. Thus, the surface of the resist mask 11 is removed by anisotropic etching. Then, as shown in FIG.
The resist film in the resist concave portion 12 is eliminated, and n
⁺ Expose the amorphous silicon layer 14. here,
The resist mask 11 shown in FIG. 1C is converted into a resist mask 11a shown in FIG. 2A, that is, a second resist mask.

Next, the n ⁺ amorphous silicon layer 1 is subjected to RIE using the above resist mask 11a as an etching mask and a mixed gas of SF ₆ , HCl and He as a reaction gas.
4 is dry etched. Thus, the ohmic contact layer 15 is formed. Further, the surface of the amorphous silicon layer 13 is etched by the same RIE to form a channel dug portion 16 as shown in FIG. Here, the channel digging section 16
Has a very smooth surface shape and is close to a mirror surface.
The depth of the channel dug portion 16 is about 50 nm.

Next, the resist mask 11a used as the RIE mask is removed by known ashing. In this way, as shown in FIG. 2C, an amorphous silicon layer 13 having an ohmic contact layer 15 in a predetermined region on the surface thereof and having a very smooth channel dug portion 16 is formed.

Next, as shown in FIG. 2D, a metal conductive film 17 of chromium or the like is deposited by a sputtering method. here,
The metal conductive film 17 is formed so as to cover the gate insulating film 3, the amorphous silicon layer 13, the ohmic contact layer 15, and the channel dug portion 16.

Next, the metal conductive film 17 is processed into a predetermined shape by photolithography and dry etching. Thus, the source electrode 18 and the drain electrode 19 are formed as shown in FIG.

In this manner, the gate electrode 2 on the insulating substrate 1, the gate insulating film 3, the amorphous silicon layer 13 having the very smooth channel dug portion 16, the source electrode 18 connected to the ohmic contact layer 15, and the drain An inverted staggered TFT having the electrode 19 is formed.

Further, although not shown, a passivation film is formed so as to cover the whole, and an inverted staggered T
The manufacture of the FT ends.

In the method of manufacturing a TFT according to the present invention, the surface of the channel dug portion becomes very smooth as described above. Further, the present invention has the following effects. Hereinafter, this effect will be described with reference to FIG.

FIG. 4 shows the relationship between the amount of etching variation after RIE for forming a channel dug portion and the channel etching time of the RIE in comparison with the prior art. Here, the reaction gas in the RIE is the mixed gas of SF ₆ , HCl and He described in the above embodiment also in the case of the conventional technique. Further, the depth of the channel dug portion is set to be the same in the present invention and the prior art.

As can be seen from FIG. 4, in the method of the present invention, the etching time is reduced to less than half of the conventional one. Furthermore, the variation in the depth of the channel dug portion in the wafer plane, that is, the variation in the etching, is reduced by the method of the present invention to 1/3 or less of that in the conventional technique.

The effect of the present invention is as follows.
At the time of the RIE process for forming the channel trench,
This is caused by the fact that a silicide layer formed by the reaction between chromium metal and silicon is hardly formed on the surface of the n ⁺ amorphous silicon layer 14.

On the other hand, in the case of the conventional technique, since the silicide layer is formed without control at the time of the RIE process for forming the channel dug portion, the control of the RIE is performed. Becomes very difficult.

Next, a second embodiment of the present invention will be described with reference to FIGS. 5 and 6 are cross-sectional views of a reverse staggered TFT according to the present invention in the order of manufacturing steps. In this embodiment, a method of forming a resist mask having a resist concave portion is different from that of the first embodiment. Hereinafter, the same components as those of the first embodiment are denoted by the same reference numerals.

As shown in FIG. 5A, a gate electrode 2 and a gate insulating film 3 are formed on an insulating substrate 1 by lamination. Further, an amorphous silicon film 4 having a thickness of about 400 nm and an n ⁺ amorphous silicon film 5 having a thickness of about 80 nm are stacked and deposited.

Next, a first positive type film having a thickness of about 500 nm is formed.
A resist film 20 is formed by a known photolithography technique. Further, a second resist film 21 is formed on the first resist film 20. Here, the second resist film 21 is a positive silylatable resist film having a thickness of about 300 nm. Then, as shown in FIG. 5A, the resist film 6 is exposed with exposure light 10 using the reticle 7 having the light shielding portion 8 and the semi-transparent portion 9 as a mask. Then, development is performed after this exposure. Here, the reticle is shown in FIG.
What was explained in is used.

In this manner, as shown in FIG. 5B, the first resist film is patterned to form a resist mask 11. Here, a resist concave portion 12 is formed in the resist mask 11. Then, the second resist film 21 is patterned to form a second resist film pattern 2.
1a is formed.

Next, the n ⁺ amorphous silicon film 5 and the amorphous silicon film 4 are sequentially processed by RIE using a mixed gas of Cl ₂ and HBr as a reaction gas. And
As shown in FIG. 5C, an island-shaped amorphous silicon layer 13 and an island-shaped n ⁺ amorphous silicon layer 14 are formed.

Next, it is immersed in a silylating agent such as silazane to silylate only the second resist film pattern 21a to form a silylated film 22. This silylated film 22 contains a large amount of silicon atoms. Here, the resist mask 1
One surface is not silylated. This is because the first resist film 19 is a resist film that is not silylated.

Next, anisotropic RIE in O ₂ gas is performed in the state of FIG. In this RIE, as shown in FIG. 6A, the silylated film 22 is oxidized and converted into a silica film 23. The silica film 23 is formed by reacting silicon contained in the silylated film 22 with oxygen to form a silicon oxide film. Then, the resist film in the resist concave portion 12 is eliminated, and the n ⁺ amorphous silicon layer 14 is exposed. Here, the resist mask 11 shown in FIG.
It changes to a resist mask 11a as shown in FIG.

Next, the silica film 23 and the resist mask 11
Using a as an etching mask, the exposed region of the n ⁺ amorphous silicon layer 14 is dry-etched by RIE using a mixed gas of SF ₆ , HCl and He as a reaction gas. Then, as shown in FIG. 6B, an ohmic contact layer 15 is formed. Further, by the same RIE, the surface of the amorphous silicon layer 13 is etched to form the channel dug portion 16. Here, the surface shape of the channel dug portion 16 is extremely smooth, and becomes a state close to a mirror surface. The depth of the channel dug portion 16 is about 90 nm.

Next, the silica film 23 and the resist mask 11
a is removed by the method. In this way, as shown in FIG. 6C, the amorphous silicon layer 13 having the ohmic contact layer 15 and the extremely smooth channel dug portion 16 is formed.

After that, by performing the same steps as those in FIG. 2D of the first embodiment, an inverted stagger type TFT is completed.

In the second embodiment, the formation of the resist mask 11a is easier and the controllability thereof is improved as compared with the first embodiment. In addition, the same effect as that described in the first embodiment also occurs.

In the second embodiment, a silylatable resist film is used. In this case, it is not always necessary to form the resist recess 12. Resist recess 12
Is formed, and the resist mask 11 is formed by RIE using O2 gas using the silylated film 22 as a mask.
a can be formed. In this case, the reticle 7 does not require the translucent portion 9.

[0052]

As described above, in the method of manufacturing a TFT according to the present invention, a gate electrode, a gate insulating film, a semiconductor thin film, and a semiconductor thin film containing high-concentration impurities are sequentially laminated on an insulating substrate. The semiconductor thin film containing the high concentration impurity and the semiconductor thin film are etched with the first resist mask to form an island-shaped semiconductor layer. Then, the first resist mask is processed into a second resist mask. I do. Then, the surface of the island-shaped semiconductor layer is etched with the second resist mask to form an ohmic contact layer and a channel dug portion. After this, the second resist mask is removed, a metal conductive film is deposited on the entire surface, and dry etching is performed to form a source electrode and a drain electrode connected to the ohmic contact layer.

Here, the cross-sectional shape of the first resist mask formed of the resist film is concave, and the resist film is formed so as to be thick above the ohmic contact layer and thin at the channel dug portion. Then, after forming the island-shaped semiconductor layer, anisotropic dry etching is performed on the first resist mask to form a second resist mask in which the resist film remains only above the ohmic contact layer.

Alternatively, the first resist mask is composed of a resist film formed by laminating a first resist film and a second resist film in this order, and the second resist film is formed only on the ohmic contact layer. Then, after the island-shaped semiconductor layer is formed, silicon is contained in the second resist film by a silylation process, and the silicon-containing second resist film is converted into a silicon oxide film by dry etching in oxygen gas. The first resist film that is not covered with the second resist film is removed by etching to form a second resist mask in which the resist film remains only above the ohmic contact layer.

For this reason, in manufacturing the TFT of the present invention, R
The control of the channel engraving portion by the IE and the planar shape after the etching are greatly improved. And
In the prior art, the surface of the channel dug portion was roughened in a rough surface, whereas in the present invention, the surface became a mirror surface.

Then, the leak current between the source and the drain when the TFT is off is greatly reduced due to the formation of the rough channel digging portion as occurs in the prior art.

Further, a simple manufacturing method of the channel dug-in type TFT becomes possible, and the productivity of the inverted stagger type TFT is greatly improved. Further, in the manufacture of an inverted staggered TFT, a TFT having high performance and high reliability can be formed.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a T for explaining a first embodiment of the present invention.
It is sectional drawing of the FT manufacturing process order.

FIG. 2 is a diagram showing T for explaining the first embodiment of the present invention;
It is sectional drawing of the FT manufacturing process order.

FIG. 3 is a sectional view of a reticle used in the embodiment of the present invention.

FIG. 4 is a graph for explaining the effect of the present invention.

FIG. 5 is a diagram showing T for explaining a second embodiment of the present invention;
It is sectional drawing of the FT manufacturing process order.

FIG. 6 is a diagram showing T for explaining a second embodiment of the present invention;
It is sectional drawing of the FT manufacturing process order.

FIG. 7 is a cross-sectional view illustrating a related art in the order of manufacturing steps of a TFT.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1,101 Insulating substrate 2,102 Gate electrode 3,103 Gate insulating film 4,104 Amorphous silicon film 5,105 n ⁺ Amorphous silicon film 6 Resist film 7 Reticle 7a Reticle substrate 8 Light shielding part 8a Thin film part 9 Semi-transmissive part 9a Halftone part 10 Exposure irradiation light 11, 11a Resist mask 12 Resist concave part 13, 106 Amorphous silicon layer 14, 107n ⁺ amorphous silicon layer 15, 109a, 110a Ohmic contact layer 16, 111 Channel dug part 17, 108 Metal conductive film 18, 109 Source electrode 19, 110 Drain electrode 20 First resist film 21 Second resist film 21a Second resist film pattern 22 Silylation film 23 Silica film

Claims (8)

[Claims] A first step of forming a gate electrode on an insulating substrate, covering the gate electrode, sequentially stacking and depositing a gate insulating film, a semiconductor thin film and a semiconductor thin film containing a high concentration impurity; Etching the semiconductor thin film containing the high concentration impurity and the semiconductor thin film with a resist mask to form an island-shaped semiconductor layer;
Processing the resist mask to form a second resist mask; etching the surface of the island-shaped semiconductor layer with the second resist mask to form an ohmic contact layer and a channel dug portion; Forming a source electrode and a drain electrode connected to the ohmic contact layer by depositing a metal conductive film on the entire surface and performing dry etching after removing the second resist mask. Production method. 2. The method according to claim 1, wherein the semiconductor thin film is an amorphous silicon film. 3. The first resist mask formed of a resist film has a concave cross-sectional shape, and is formed such that the resist film is thicker above the ohmic contact layer and thinner at the channel dug portion. 3. The method of manufacturing a thin film transistor according to claim 1, wherein: 4. After forming the island-shaped semiconductor layer, the first resist mask is subjected to anisotropic dry etching to leave a resist film only on the ohmic contact layer. 4. The method for manufacturing a thin film transistor according to claim 3, wherein 5. The method according to claim 1, wherein the first resist mask is formed of a resist film formed by laminating a first resist film and a second resist film in this order, and the second resist film is formed only on the ohmic contact layer. The method for manufacturing a thin film transistor according to claim 1 or 2, wherein: 6. After forming the island-shaped semiconductor layer, silicon is contained in the second resist film by a silylation process, and the silicon-containing second resist film is formed by dry etching in oxygen gas. Converting the oxide film into an oxide film and removing the first resist film that is not covered by the second resist film by etching to form the second resist mask in which the resist film remains only above the ohmic contact layer. A method for manufacturing a thin film transistor according to claim 5. 7. A light-shielding portion and a semi-light-transmitting portion are formed in a mask pattern of a reticle used in a photolithography step, and the light-shielding portion and the semi-light-transmitting portion are transferred to a resist film to form the first resist. 6. The method according to claim 3, wherein a mask is formed. 8. The thin film transistor according to claim 7, wherein, in the mask pattern of the reticle, the semi-light-transmitting portion is formed of a light-shielding pattern having a size smaller than a resolution limit.