JP2007059926A - Pattern-forming method and thin-film transistor manufacturing method - Google Patents

Pattern-forming method and thin-film transistor manufacturing method Download PDF

Info

Publication number
JP2007059926A
JP2007059926A JP2006263631A JP2006263631A JP2007059926A JP 2007059926 A JP2007059926 A JP 2007059926A JP 2006263631 A JP2006263631 A JP 2006263631A JP 2006263631 A JP2006263631 A JP 2006263631A JP 2007059926 A JP2007059926 A JP 2007059926A
Authority
JP
Japan
Prior art keywords
portion
film
electrode
resist mask
formed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006263631A
Other languages
Japanese (ja)
Inventor
Shusaku Kido
秀作 城戸
Original Assignee
Nec Kagoshima Ltd
鹿児島日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Kagoshima Ltd, 鹿児島日本電気株式会社 filed Critical Nec Kagoshima Ltd
Priority to JP2006263631A priority Critical patent/JP2007059926A/en
Publication of JP2007059926A publication Critical patent/JP2007059926A/en
Application status is Pending legal-status Critical

Links

Images

Abstract

<P>PROBLEM TO BE SOLVED: To provide a new manufacturing method of a TFT by devising a pattern forming method, where photolithographic processes can be reduced easily and conveniently, and the production process of a liquid crystal display device is remarkably reduced. <P>SOLUTION: A material film constituting a TFT is laminated and formed on an insulating film substrate, and then a resist mask, having a plurality of regions whose thickness of the film is different to one another, is formed at the uppermost layer of the material film by conducting patterning. Then, a pattern forming of a conductive body film is conducted by a lift-off method by using this resist mask. Or a plurality of material films among the material films, where a resist mask having a plurality of regions whose film thickness is different to one another formed separately, is made as an etching mask and laminated are processed sequentially. By these new pattern forming method and process method, a liquid crystal display device manufactured in five photolithographic processes in the conventional technique is manufactured in two or three photolithographic processes. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a thin film transistor (TFT) used in a liquid crystal display device and a method of forming a pattern thereof.

  In an active matrix substrate for a liquid crystal display device, a TFT, particularly an inverted staggered TFT is generally used. In manufacturing an active matrix substrate for a liquid crystal display device, five photolithography processes (hereinafter referred to as a photolithography process) are currently required.

  The element structure (for example, TFT structure) constituting the active matrix substrate for the liquid crystal display device is much simpler than that of a semiconductor integrated circuit, and shortening of the manufacturing process has become an urgent task.

  In order to shorten the manufacturing process, it is effective to reduce the photolithography process. The inventor has studied the reduction and simplification of this photolithography process for many years. And (patent document 1) etc. propose the method of forming the resist mask which has several area | regions from which a film thickness mutually differs with the device of the exposure method in photolithography technique, and utilizes such a resist mask. Thus, a technique for manufacturing a TFT is disclosed.

  The present invention further shortens the manufacturing process of the active matrix substrate for a liquid crystal display device. Therefore, the present inventor has devised a novel pattern forming method using a resist mask having a plurality of regions having different film thicknesses, and by making full use of this pattern forming method, the TFT constituting the active matrix substrate The manufacturing process can be greatly reduced. This pattern forming method basically includes a resist mask forming technique having a plurality of regions having different film thicknesses and a lift-off technique.

  This lift-off technique has often been used in the formation of semiconductor integrated circuit wiring. Therefore, as a conventional technique, wiring formation using this lift-off technique will be described with reference to FIGS. 12 and 13 with reference to the prior art described in (Patent Document 2).

  As shown in FIG. 12A, a lower layer electrode 202 such as a TFT gate electrode is formed on a glass substrate 201, which is a transparent insulating substrate, by patterning a metal such as chromium. Then, an insulating film 203 such as a TFT gate insulating film is formed so as to cover the lower electrode 202. Then, a first resist mask 205 having a first opening 204 is formed by a known photolithography technique, and a contact hole 206 reaching the surface of the lower layer electrode 202 is formed in the insulating film 203 using the first resist mask 205 as an etching mask. .

  Next, the first resist mask 205 is exposed again with the exposure irradiation light 210 using the photomask 209 having the light shielding portion 207 and the light transmitting portion 208 as shown in FIG. After this exposure, the laminated resist film is developed by a normal method.

  Thus, as shown in FIG. 12C, a second resist mask 212 having a second opening 211 having a larger opening than the contact hole 206 is formed.

  Next, a metal film 213 is deposited on the entire surface by sputtering. In this way, as shown in FIG. 13A, a metal film 213 is formed which is deposited on the surface of the insulating film 203 and the second resist mask through the second opening 211 and is connected to the lower layer electrode 202.

  Next, the second resist mask 212 is removed by a normal lift-off technique. In the step of removing the second resist mask 212, the metal film 213 deposited on the second resist mask 212 is simultaneously removed, and the metal film 213 is patterned. Subsequently, the second resist mask 212 is peeled and removed.

  In this way, as shown in FIG. 13B, the upper layer electrode 214 connected to the lower layer electrode 202 through the contact hole 206 provided in the insulating film 203 is formed.

JP-A-11-307780 JP-A-7-240535

  As described above, in the conventional technique for forming two layers of interconnects connected to each other, even if the method is based on the lift-off technique or the etching technique, the lower layer electrode, the contact hole, the upper layer At least three photolithography steps are required for the electrodes.

  The above-described conventional technique attempts to shorten the photolithography process of the lift-off technique. However, in the conventional technique, in the etching of the insulating film 203, for example, in dry etching, the first resist mask 205 is irradiated with light or ions and the surface thereof is changed. Even if an attempt is made to transfer the pattern to the first resist mask 205 thus altered with the exposure light 210 described with reference to FIG. For this reason, this method cannot be applied to the formation of electrodes or wirings in the production of an active matrix substrate.

  At present, it is essential to reduce the manufacturing cost of liquid crystal display devices. However, in order to manufacture such an active matrix substrate for a liquid crystal display device, the conventional technique uses at least five photolithography processes. Therefore, it has become essential to reduce the number of photolithography processes for manufacturing an active matrix substrate for a liquid crystal display device, and technical development therefor is strongly desired.

  Such a reduction in the number of photolithography processes inevitably increases the manufacturing yield of the liquid crystal display device and improves the productivity. And the reliability is also improved.

  An object of the present invention is to provide a novel putter formation method capable of easily reducing the number of photolithography processes. Another object of the present invention is to provide a new method for manufacturing a TFT, which can greatly shorten the manufacturing process of a liquid crystal display device.

  A step of forming a lower layer electrode on an insulating substrate and covering the lower layer electrode to form an insulating film; and a resist mask patterned to have a plurality of thicknesses, and a thin region as a first portion Forming a resist mask having an opening formed in the first portion on the surface of the insulating film as a second portion having a film thickness less than that of the first portion, and using the resist mask as an etching mask; Etching the insulating film to form a contact hole reaching the surface of the lower electrode in the opening, followed by removing the first portion by etching and covering the remaining second portion to conduct the entire surface. Forming a body film, and patterning the conductor film by lift-off by removing the second portion after the conductor film is formed.

  Here, a process of forming a first lower layer electrode or wiring on an insulating substrate and covering the first lower layer electrode or wiring to form a first insulating film; and from the first insulating film, Forming at least a second lower layer electrode or wiring, forming a second insulating film by covering the second lower layer electrode or wiring, and patterning to have a plurality of thicknesses A resist mask having a thin film thickness as a first part and a thick film area as a second part having at least less film slipping than the first part is defined as the resist mask having an opening formed in the first part. And forming the first insulating film on the surface of the first lower electrode in the opening by etching the first insulating film and the second insulating film using the resist mask as an etching mask. The contact hole reaching the Etching the insulating film to form a contact hole reaching the surface of the second lower electrode in the opening, and subsequently covering the second portion remaining after etching away the first portion Then, a step of forming a conductor film on the entire surface and a step of patterning the conductor film by lift-off by removing the second portion after the formation of the conductor film are included.

  Here, it is characterized in that the film removal of the second portion is small in the etching removal step of the first portion. Alternatively, a step of forming a lower layer electrode on an insulating substrate and covering the lower layer electrode to form an insulating film, and a resist mask patterned to have a plurality of thicknesses, wherein a thin region is first Forming a resist mask having an opening formed in the first portion as a second portion whose surface is silylated at least as a portion and a region having a large film thickness on the surface of the insulating film; and using the resist mask as an etching mask Etching the insulating film to form a contact hole reaching the surface of the lower electrode in the opening, followed by removing the first portion by etching and covering the remaining second portion to conduct the entire surface. Forming a body film; and patterning the conductor film by lift-off by removing the second portion after the conductor film is formed. .

  Alternatively, a step of forming a first insulating film by forming a first lower layer electrode or wiring on an insulating substrate and covering the first lower layer electrode or wiring, and at least from the first insulating film A step of forming a second lower layer electrode or wiring above, forming a second insulating film by covering the second lower layer electrode or wiring, and a resist patterned to have a plurality of thicknesses A mask having a thin region as a first portion and a thick region as a second portion having at least a surface silylated, and the resist mask having an opening formed in the first portion as the second insulation. A step of forming on the film surface, and a contact reaching the surface of the first lower electrode in the opening by etching the first insulating film and the second insulating film using the resist mask as an etching mask. A hole and the second Etching the edge film to form a contact hole reaching the surface of the second lower electrode in the opening, and subsequently covering the second portion remaining after etching away the first portion. Forming a conductive film over the entire surface, and patterning the conductive film by lift-off by removing the second portion after the conductive film is formed.

  Alternatively, etching removal of the first portion is performed by dry etching using active species obtained by plasma excitation of a halogen compound gas and an oxygen gas. Alternatively, the first and second insulating films, or the gate insulating film and the passivation film are dry etching, and the surface modification of the second portion is performed by the dry etching, and the dry etching of the first portion is performed. The sectional shape of the second portion is reversely tapered.

  Alternatively, in the mask pattern of the photomask used in the photolithography process, the light shielding portion, the semi-translucent portion, and the translucent portion are formed, and the light shielding portion pattern, the semi-transparent portion pattern, and the translucent portion pattern are formed by one exposure. And the resist mask (photosensitive organic film) is transferred and irradiated, and then the resist mask is formed through development.

  Alternatively, the resist mask is formed through development after continuous exposure irradiation to a predetermined region of a resist film using two or more kinds of photomasks having different mask patterns in exposure in a photolithography process. Alternatively, the resist film is composed of two layers of resist films having different exposure sensitivities.

  Alternatively, in the manufacturing process of the active matrix substrate for a liquid crystal display device, contact holes are formed in the passivation film on the source / drain electrodes of the thin film transistor and the gate insulating film on the gate electrode, and the source / drain electrodes are formed through the contact holes. Alternatively, a resist mask obtained by patterning an electrode and a wiring connected to the gate electrode and a pixel electrode on the passivation film so as to have a plurality of thicknesses. Is formed using a resist mask having at least a second portion with less film slippage than the first portion.

  Alternatively, in the manufacturing process of the active matrix substrate having a thin film transistor, formation of a contact hole in the gate insulating film on the gate electrode of the thin film transistor, an electrode connected to the gate electrode through the contact hole, a terminal electrode, and a wiring; A resist mask obtained by patterning a source / drain electrode on a gate insulating film so as to have a plurality of thicknesses, wherein a thin region is a first portion and a thick region is at least thinner than the first portion. And a step of forming using a resist mask having a small second portion. Alternatively, in a manufacturing process of an active matrix substrate for a liquid crystal display device, contact holes are formed in a passivation film on a source / drain electrode of a thin film transistor and a gate insulating film on a gate electrode, and the source / drain electrode is formed through the contact hole. Alternatively, a resist mask obtained by patterning an electrode and a wiring connected to the gate electrode and a pixel electrode on the passivation film so as to have a plurality of thicknesses. Using a resist mask having at least a second portion having a silylated surface.

  Alternatively, in the manufacturing process of the active matrix substrate having a thin film transistor, formation of a contact hole in the gate insulating film on the gate electrode of the thin film transistor, an electrode connected to the gate electrode through the contact hole, a terminal electrode, and a wiring; A resist mask obtained by patterning a source / drain electrode on a gate insulating film so as to have a plurality of thicknesses, wherein a thin region is a first portion and a thick region is silylated at least on the surface. Forming using a resist mask having two parts. Alternatively, the resist mask is a resist film (photosensitive organic film) pattern having a plurality of thicknesses, and the resist film (photosensitive organic film) has a thick first portion and a thin second portion. And etching of the lower layer film using the first part and the second part as a mask, and patterning by lift-off of the film formed after removing the second part by etching. Alternatively, the first and second insulating films, or the gate insulating film and the passivation film are dry etching, and the surface modification of the second portion is performed by the dry etching, and the dry etching of the first portion is performed. The sectional shape of the second portion is reversely tapered. Alternatively, in the mask pattern of the photomask used in the photolithography process, the light shielding portion, the semi-translucent portion, and the translucent portion are formed, and the light shielding portion pattern, the semi-transparent portion pattern, and the translucent portion pattern are formed by one exposure. And the resist mask (photosensitive organic film) is transferred and irradiated, and then the resist mask is formed through development. Alternatively, the resist mask is formed through development after continuous exposure irradiation to a predetermined region of a resist film using two or more kinds of photomasks having different mask patterns in exposure in a photolithography process. Alternatively, the resist film is composed of two layers of resist films having different exposure sensitivities.

  In the main part of the present invention described above, after a material film constituting a TFT is stacked on an insulating film substrate, a resist mask having a plurality of regions having different film thicknesses is formed on the top of the material film. It is formed by patterning on the upper layer. Then, the pattern of the conductor film is formed by a lift-off method using this resist mask. Alternatively, a plurality of material films among the stacked material films are sequentially processed using a resist mask having a plurality of regions having different thicknesses formed separately as an etching mask.

  With the novel pattern forming method and processing method as described above, the liquid crystal display device manufactured by the conventional technique in five photolithography processes can be manufactured in two or three photolithography processes.

  By shortening the process, the manufacturing yield of the liquid crystal display device is improved, the productivity is increased, and the manufacturing cost of the liquid crystal display device is greatly reduced. Furthermore, the reliability is greatly improved.

  Next, a novel pattern forming method of the present invention will be described as a first embodiment with reference to FIG. Here, FIG. 1 is a cross-sectional view in order of manufacturing steps of a two-layer electrode showing the features of the present invention.

  As shown in FIG. 1A, in the same manner as described in the prior art, a lower layer electrode 2 such as a TFT gate electrode is formed on a glass substrate 101 by patterning a metal such as chromium. Then, an insulating film 3 that covers the lower electrode 2 is formed.

  Next, a resist mask 6 composed of a first portion 4 that is a thin region and a second portion 5 that is a thick region is formed by the method described in Japanese Patent Application Laid-Open No. 11-307780. . Here, the film thickness of the first portion 4 is about 0.5 μm, and the first opening 7 is formed by patterning. The film thickness of the second portion 5 is about 2.5 μm, and the second opening 8 is formed by patterning. Such a resist mask is formed by a single photolithography process.

  Next, the insulating film 3 is dry-etched by reactive ion etching (RIE) using the resist mask 6 as described above as an etching mask. In this way, the contact hole 9 reaching the surface of the lower electrode 2 is formed. In the dry etching step, ions in the plasma irradiate the surface of the resist mask 6 to cure and modify the surface.

Next, a mixed gas of O 2 and CF 4 is plasma-excited to form these ions or radicals, that is, active species, and the resist mask 6 is etched back by dry etching. By this etch back, only the first portion 4 of the resist mask 6 is removed. In this dry etching, the second portion 5 of the resist mask 6 is also etched to cause side etching. In this way, the second portion 5a of the resist mask 6 having the inversely tapered second opening 8a as shown in FIG. 1B is left. Here, the film thickness of the remaining second portion 5a is about 1.5 μm.

  Next, as described in the prior art, the metal film 10 having a film thickness of about 0.8 μm is deposited on the entire surface by the rectilinear sputtering method. In this way, as shown in FIG. 1C, the metal film 10 is formed on the surface of the insulating film 3 and the second portion 5a in the second opening 8a region and connected to the lower electrode 2. In this sputtering step, as described above, the second opening 8a has an inversely tapered shape, so that the metal film 10 is prevented from being deposited on the side wall of the second opening 8a.

  Next, the second portion 5a of the resist mask is removed by a normal lift-off technique. In the step of removing the second portion 5a, the metal film 10 deposited on the second portion 5a is simultaneously removed and the metal film 10 is patterned. Subsequently, the second portion 5a is peeled and removed.

  In this way, as shown in FIG. 1D, the upper layer wiring 11 connected to the lower layer electrode 2 through the contact hole 9 provided in the insulating film 3 is formed.

  In the present invention, as can be seen from the above description, the lower layer electrode, the contact hole, and the upper layer electrode can be formed by two photolithography processes. That is, the number of photolithography processes is reduced.

  In the present invention, as described above, the second opening 8a having a reverse taper shape can be easily formed in the second portion 5a of the resist mask. For this reason, the patterning of the upper layer electrode by the lift-off technique is much easier than the conventional technique. Further, the reliability of the upper layer electrode is greatly improved, and the production yield and mass productivity are greatly improved.

  Next, a description will be given of a TFT manufacturing method that greatly shortens the manufacturing process of the liquid crystal display device. As a second embodiment of the present invention, a method of manufacturing a TFT and a liquid crystal display device by three photolithography processes will be described with reference to FIGS. Here, FIG. 2 is a schematic plan view of a pixel portion of the active matrix substrate for a liquid crystal display device. Here, hatching is given in the figure for easy understanding. 3 to 6 are cross-sectional views in the order of manufacturing steps of the inverted stagger type TFT constituting the active matrix substrate, that is, the TFT constituting the pixel portion or the protection circuit portion.

  As shown by a broken line in FIG. 2, a gate electrode 22 of a TFT that is a switch transistor is formed on a glass substrate 21. Then, the semiconductor layer 23 in the region indicated by the oblique lines from the upper right to the lower left in the drawing is formed. Further, a source / drain electrode 24 and a source / drain electrode 25 are formed in a region indicated by diagonal lines from upper left to lower right. Here, the source / drain electrodes 24 constitute the data wiring of the active matrix substrate.

  The gate electrode 22 is connected to the gate terminal electrode 27 through the contact hole 26. Similarly, the source / drain electrode 24 is connected to the transparent electrode wiring 30 through the contact hole 28. Further, the source / drain electrode 25 is connected to the transparent pixel electrode 31 through the contact hole 29. Although not shown, a liquid crystal is formed on the transparent pixel electrode 31. Here, the gate terminal electrode 27, the transparent electrode wiring 30, and the transparent pixel electrode 31 are made of ITO which is a transparent conductor.

  Next, a manufacturing method of the inverted stagger type TFT will be described. As shown in FIG. 3A, a gate electrode 22 is formed on a glass substrate 21 by patterning a chromium (Cr) conductive film. Here, the thickness of the gate electrode 22 is about 200 nm. Then, a gate insulating film 32 is formed on the gate electrode 22. Here, the gate insulating film 32 is formed of a silicon nitride film having a thickness of 500 nm.

Next, an amorphous silicon film 33 having a thickness of about 300 nm, which is a semiconductor thin film, an n + amorphous silicon film 34 having a thickness of about 50 nm, which is a semiconductor thin film for ohmic contact, and a source / drain conductive film such as chromium. A metal conductive film 35 is stacked and deposited.

  Next, in the photolithography process, as shown in FIG. 3B, a resist film 36 is formed on the surface of the metal conductive film 35. Here, the resist film 36 is a positive resist, and each film thickness is 2.0 μm. Then, the resist film 36 is exposed with exposure irradiation light 41 using a photomask 40 having a light shielding portion 37, a semi-translucent portion 38 and a translucent portion 39 as shown in FIG. After this exposure, the resist film 36 is developed by a normal method.

  An example of such a light shielding part, a semi-transparent part, and a photomask having transmitted light will be described. In the example shown in FIG. 3B, the light shielding portion 37 is formed in a predetermined pattern on the photomask 40 by using, for example, chromium metal. The semi-transparent portion 38 is formed with a halftone material. Here, the halftone material is, for example, tungsten silicide. In this way, a semi-translucent part is formed. The transmission part 39 is an area where the chromium metal and the halftone material do not exist.

  In addition, as an example of a photomask having a light shielding part, a semi-transparent part, and a transmitted light, a light shielding part is formed in a predetermined pattern on a photomask substrate, for example, with chromium metal. The semi-translucent portion is formed by thinning the chromium metal. In this case, it is set so that about half of the exposure light is transmitted in the region where the chromium metal thin film portion is formed. In this way, a semi-translucent part is formed.

  As described above, a resist mask 44 composed of the first thin portion 42 and the thick second portion 43 as shown in FIG. To form. Here, the transfer pattern of the light shielding portion 37 of the photomask 40 described above becomes the second portion 43 of the resist mask 44, and the transfer pattern of the semi-transparent portion 38 becomes the first portion 42 of the resist mask 44.

Next, as shown in FIG. 4A, the metal conductive film 35, the n + amorphous silicon film 34, and the amorphous silicon film 33 are sequentially etched using the resist mask 44 described above as an etching mask. In this way, as shown in FIG. 4A, the semiconductor layer 23 which is an island-shaped amorphous silicon layer, the island-shaped n + amorphous silicon layer 45 and the metal conductive layer 46 are formed.

Here, the metal conductive film 35 is etched by wet etching using a chemical solution in which ceric ammonium nitrate and perchloric acid are mixed as an etchant. Then, the n + amorphous silicon film 34 and the amorphous silicon film 33 are dry-etched by RIE using a mixed gas of Cl 2 and HBr plasma-excited as a reaction gas. In this dry etching process, the gate insulating film 32 made of the silicon nitride film is hardly etched.

Next, a mixed gas of O 2 and CF 4 is plasma-excited to form active species such as ions or radicals, and the resist mask 44 is etched back by anisotropic dry etching. In this etch-back process, the first portion 42 of the resist mask 44 is removed without much side etching. In this way, as shown in FIG. 4B, the second portion 43a remaining on the metal conductive layer 46 is formed.

Next, as shown in FIG. 4C, the metal conductive layer 46 and the n + amorphous silicon layer 45 are sequentially etched using the second portion 43a of the resist mask as an etching mask. In this manner, source / drain electrodes 24 and 25 are formed, and ohmic layers 47 and 48 are further formed.

  Next, the second portion 43a is removed, and a passivation film 49 is formed on the entire surface as shown in FIG. Here, the passivation film 49 is formed of a silicon nitride film having a thickness of about 500 nm.

  Next, a resist mask 50 composed of a first portion that is a thin region and a second portion that is a thick region is formed by a method similar to that described with reference to FIG. Here, a first opening 51 is formed in the first portion, and a second opening 52 is formed in the second portion.

Next, the passivation film 49 or the gate insulating film 32 is dry etched by RIE using the resist mask 50 as an etching mask. Here, the reactive gas is obtained by plasma-exciting a mixed gas of SF 6 and He. In this way, contact holes 26, 28, and 29 are formed on the gate electrode 22 and the source / drain electrodes 24 and 25, as shown in FIG.

Next, as described with reference to FIG. 1, a mixed gas of O 2 and CF 4 is plasma-excited, and the resist mask 50 is etched back. The first portion of the resist mask 50 is removed by this etch back. By this dry etching, as shown in FIG. 6A, a resist mask 50a having an inversely tapered opening is left. Then, a transparent electrode film 53 having a film thickness of about 0.8 μm is deposited on the entire surface by a straight sputtering method so as to be connected to the gate electrode 22 and the source / drain electrodes 24 and 25. Then, the resist mask 50a is removed by a normal lift-off technique.

  In this manner, the gate terminal electrode 27 connected to the gate electrode 22 is formed and the transparent electrode wiring 30 connected to the source / drain electrode 24 is formed as shown in FIG. A transparent pixel electrode 31 connected to the source / drain electrode 25 is formed. As described above, the TFT of the pixel portion is formed.

  In the present invention, as can be seen from the above description, a TFT can be manufactured by three photolithography processes where the conventional technique requires five photolithography processes. For this reason, the manufacturing process of the liquid crystal display device composed of TFTs is significantly shortened. In addition, the manufacturing yield of the liquid crystal display device is improved and the productivity is increased. Furthermore, the manufacturing cost of the liquid crystal display device is greatly reduced and the manufacture of a highly reliable TFT is facilitated.

  Next, a third embodiment of the present invention will be described with reference to FIGS. In this embodiment mode, a method for manufacturing a TFT and a liquid crystal display device by two photolithography steps will be described. Here, FIG. 7 and FIG. 8 are cross-sectional views in the order of main manufacturing steps of the inverted stagger type TFT constituting the active matrix substrate, that is, the TFT constituting the pixel portion or the protection circuit portion.

First, a chromium conductive film to be a gate electrode, a gate insulating film, an amorphous silicon film, an n + amorphous silicon film, and a metal conductive film are stacked and deposited.

  Next, in a photolithography process, as shown in FIG. 7A, a resist mask 62 is formed on the surface of the uppermost metal conductive film. Here, the resist mask 62 includes a first portion 63 that is a thin region and a second portion 64 that is a thick region. Here, the film thickness of the first portion 63 is about 1.0 μm, and the film thickness of the second portion 64 is about 3.0 μm. Such a resist mask 62 is formed by the method described with reference to FIG. 3 of the second embodiment.

Next, as shown in FIG. 7A, the metal conductive film, the n + amorphous silicon film, the amorphous silicon film, the gate insulating film, and the chromium conductive film are sequentially etched using the resist mask 62 described above as an etching mask. . In this manner, the gate electrode 65, the gate insulating film 66, the semiconductor layer 67, the n + amorphous silicon layer 68, and the metal conductive layer 69 are formed. Here, the etching method of the metal conductive film and the chromium conductive film is the same as that described in the second embodiment. Etching of the n + amorphous silicon film and the amorphous silicon film is performed by dry etching in which a mixed gas of SF 6 , HCl, and He is plasma-excited. Etching of the gate insulating film is performed by dry etching in which a mixed gas of SF 6 and He is plasma-excited.

Next, as described with reference to FIG. 4, a mixed gas of O 2 and CF 4 is plasma-excited, and the resist mask 62 is etched back by anisotropic dry etching. In this etch back process, the first portion 63 of the resist mask 62 is removed. Then, the second portion 64a remaining on the metal conductive layer 69 is formed.

Next, the metal conductive layer 69 and the n + amorphous silicon layer 68 are sequentially etched using the second portion 64a as an etching mask. In this manner, ohmic layers 70 and 71 and source / drain electrodes 72 and 73 are formed as shown in FIG.

  Next, the second portion 64a is removed, and a passivation film 74 is formed on the entire surface as shown in FIG.

  Next, as described with reference to FIG. 5, a resist mask 75 including a first portion that is a thin region and a second portion that is a thick region is formed. Then, dry etching is performed using the resist mask 75 as an etching mask. In this etching step, as shown in FIG. 8A, the passivation film 74, the semiconductor layer 67, and the gate insulating film 66 on the gate electrode 65 are sequentially dry-etched to form contact holes 76. At the same time, contact holes 77 and 78 are formed on the source / drain electrodes 72 and 73.

  Thereafter, in the same manner as described with reference to FIG. 6A, a resist mask 75a having an inversely tapered opening is formed as shown in FIG. 8B, and the transparent electrode film 79 is formed by a rectilinear sputtering method. After deposition on the entire surface, the resist mask 75a is removed by a normal lift-off technique. In this way, wirings or electrodes connected to the gate electrode 65, the source / drain electrode 72, and the source / drain electrode 73, respectively, are formed as described with reference to FIG.

  Next, a schematic plan view of a pixel portion of the active matrix substrate for a liquid crystal display device when formed as described above will be described with reference to FIG. Here, hatching is given in the figure for easy understanding.

As shown by a broken line in FIG. 9, a gate electrode 65 of a TFT that is a switch transistor is formed. Then, the semiconductor layer 67 in the region indicated by the oblique lines from the upper right to the lower left in the drawing is formed. Here, the gate electrode 65 and the semiconductor layer 67 have the same pattern. Further, a source / drain electrode 72 and a source / drain electrode 73 are formed in a region indicated by oblique lines from the upper left to the lower right. Here, the source / drain electrode 72 is divided into three. This is because the same pattern as the source / drain electrode pattern is formed as the gate electrode and the semiconductor layer.

  The gate electrode 65 is connected to the gate terminal electrode 80 through the contact hole 76. Similarly, the source / drain electrode 72 is connected to the transparent electrode wiring 81 through the contact hole 77. Further, the source / drain electrode 73 is connected to the transparent pixel electrode 82 through the contact hole 78.

  The effect of the third embodiment becomes more prominent than that described in the second embodiment.

  Next, a fourth embodiment of the present invention will be described with reference to FIGS. In the present embodiment, the feature of pattern formation of the present invention will be further described. In this case, however, the TFT is formed by four photolithography processes.

First, as shown in FIG. 10A, a chromium conductive film is patterned to form a gate electrode 92 on a glass substrate 91. Then, a gate insulating film 93 is formed, and a semiconductor layer 94 and an n + amorphous silicon layer 95 are formed.

  Next, as described in the second or third embodiment, a resist mask 96 is formed by a photolithography process as shown in FIG. 10B. Here, the resist mask 96 includes a first portion 97 that is a thin region and a second portion 98 that is a thick region. Then, a contact hole 99 is formed in the gate insulating film 93 on the gate electrode 92.

Next, a mixed gas of O 2 and CF 4 is excited with plasma, and the resist mask 96 is etched back by anisotropic dry etching. In this etch back process, the first portion 97 of the resist mask 96 is removed. Then, the remaining second portion 98a is formed as shown in FIG.

Next, as shown in FIG. 10D, a transparent electrode film 100 and a metal conductive film 101 are stacked. Here, the transparent electrode film 100 is an ITO film, and the metal conductive film 101 is a chromium film. And said 2nd part 98a is peeled. That is, lift-off is performed to form the gate terminal electrode 102 connected to the gate electrode 92 and the source / drain electrodes 103 and 104 connected to the n + amorphous silicon layer 95 as shown in FIG. Here, the gate terminal electrode 102 and the source / drain electrodes 103 and 104 are both formed of the two-layered conductor film.

Next, the n + amorphous silicon layer 95 is etched using the source / drain electrodes 103 and 104 as an etching mask. In this way, as shown in FIG. 11B, ohmic layers 105 and 106 connected to the source / drain electrodes 103 and 104, respectively, are formed at the end of the semiconductor layer 94.

  Then, a passivation film 107 is deposited on the entire surface, and an opening 108 is formed on the gate terminal electrode 102. Further, the metal conductive film 101 in the source / drain electrode 104 region is also removed to form a transparent pixel electrode 109.

  In the present invention, in manufacturing a liquid crystal display device, a material film constituting a semiconductor element such as a TFT is previously deposited as a multilayer film, and has a plurality of thicknesses as an etching mask for patterning the multilayer film. A resist mask patterned in this way is formed.

  There are various variations in the method of forming such a resist mask. This will be described below.

  In the second embodiment, a positive resist is applied and the pattern is transferred by one exposure method. In the second embodiment, a single-layer resist film is used, but a two-layer resist film can also be used. When this two-layer resist film is used, the exposure sensitivity of the lower resist film may be made lower than the exposure sensitivity of the upper resist film. Then, the first portion is formed in the lower resist film, and the second portion is formed in the upper resist film. In this way, the accuracy of the transfer pattern is greatly improved.

  Further, in the case of the one-time exposure method, a single-layer negative resist may be used as the resist film. Since negative resists generally have lower exposure sensitivity than positive resists, they can be easily handled with a single-layer resist film. Alternatively, a negative two-layer resist film may be used. However, when this negative resist is used, the photomask is different from the photomask 40 of the second embodiment. In this case, the light shielding part 37 of the photomask 40 is a light transmitting part, and the light transmitting part 39 is a light shielding part. The semi-translucent portion 38 is the same.

  In the present invention, the pattern may be transferred by continuous exposure using a plurality of photomasks. That is, the resist mask can be formed by performing overexposure on one layer of resist film and developing. In this case, a positive-type or negative-type resist film or a two-layer resist film can be used.

  In the above embodiment, the case where the gate electrode or the source / drain electrode is formed of chromium has been described. It should be noted that Ti, Mo, W, or an alloy thereof can be used as a material for a metal conductive film or a gate electrode to be a source / drain electrode.

  In the above embodiment, the case where an inverted staggered TFT is formed over an insulating substrate has been described. It should be noted that the present invention can be similarly applied even when a staggered TFT is formed.

  In the above embodiment, the thin region in the resist mask patterned to have a plurality of thicknesses is the first portion, and the thick region is the second portion. Here, the surface of the second portion may be selectively silylated. This is very effective when the base level difference is large. That is, in the process of removing the first portion by etching, even if the base step is large, the film loss of the second portion is eliminated. The inventor has disclosed the silylation application technique in detail in JP-A-11-307780.

  In addition, this invention is not limited to said embodiment, Embodiment can be changed suitably within the range of the technical idea of this invention.

It is sectional drawing of the order of the manufacturing process of the 2 layer electrode for demonstrating the 1st Embodiment of this invention. It is a top view of the pixel part of the liquid crystal display device for demonstrating the 2nd Embodiment of this invention. It is sectional drawing of the order of the manufacturing process of TFT for demonstrating the 2nd Embodiment of this invention. It is sectional drawing of the order of the manufacturing process of TFT for demonstrating the continuation of the said process. It is sectional drawing of the order of the manufacturing process of TFT for demonstrating the continuation of the said process. It is sectional drawing of the order of the manufacturing process of TFT for demonstrating the continuation of the said process. It is sectional drawing of the order of the manufacturing process of TFT for demonstrating the 3rd Embodiment of this invention. It is sectional drawing of the order of the manufacturing process of TFT for demonstrating the continuation of the said process. It is a top view of the pixel part of the liquid crystal display device for demonstrating the 3rd Embodiment of this invention. It is sectional drawing of the order of the manufacturing process of TFT for demonstrating the 4th Embodiment of this invention. It is sectional drawing of the order of the manufacturing process of TFT for demonstrating the continuation of the said process. It is sectional drawing of the order of the manufacturing process of the 2 layer electrode for demonstrating the prior art. It is sectional drawing of the order of a manufacturing process for demonstrating the continuation of the said process.

Explanation of symbols

1, 2, 61, 91 Glass substrate 2 Lower layer electrode 3 Insulating film 4, 42, 63, 97 First part 5, 5a, 43, 43a, 64, 64a, 98, 98a Second part 6, 44, 50, 50a , 62, 75, 75a, 96 Resist mask 7, 51 First opening 8, 8a, 52 Second opening 9, 26, 28, 29, 76, 77, 78, 99 Contact hole 10 Metal film 11 Upper layer electrode 22, 65 , 92 Gate electrode 23, 67, 94 Semiconductor layer 24, 25, 72, 73, 103, 104 Source / drain electrode 27, 80, 102 Gate terminal electrode 30, 81 Transparent electrode wiring 31, 82, 109 Transparent pixel electrode 32, 66,93 gate insulating film 33 amorphous silicon film 34 n + amorphous silicon film 35,101 metal conductive 36 resist film 37 shielding portion 3 Semi-light-transmitting portion 39 the translucent portion 40 photomask 41 exposing irradiating light 45,68,95 n + amorphous silicon layer 46,69,79 metal conductive layer 47,48,70,71,105,106 ohmic layer 49,74, 107 Passivation film 53, 79, 100 Transparent electrode film 108 Opening

Claims (19)

  1.   A step of forming a lower layer electrode on an insulating substrate and covering the lower layer electrode to form an insulating film; and a resist mask patterned to have a plurality of thicknesses, and a thin region as a first portion Forming a resist mask having an opening formed in the first portion on the surface of the insulating film as a second portion having a film thickness less than that of the first portion, and using the resist mask as an etching mask; Etching the insulating film to form a contact hole reaching the surface of the lower electrode in the opening, followed by removing the first portion by etching and covering the remaining second portion to conduct the entire surface. Forming a body film and patterning the conductor film by lift-off by removing the second portion after the conductor film is formed. Pattern forming method according to claim.
  2.   Forming a first lower layer electrode or wiring on an insulating substrate and covering the first lower layer electrode or wiring to form a first insulating film; and at least above the first insulating film Forming a second lower layer electrode or wiring, covering the second lower layer electrode or wiring and forming a second insulating film, and a resist mask patterned to have a plurality of thicknesses The thin insulating region is a first portion, and the thick region is at least a second portion with less film slippage than the first portion, and the resist mask having an opening in the first portion is used as the second insulation. A step of forming on the film surface, and a contact reaching the surface of the first lower electrode in the opening by etching the first insulating film and the second insulating film using the resist mask as an etching mask. Hole and said second insulation And forming a contact hole reaching the surface of the second lower electrode in the opening, and subsequently covering the second portion remaining after the first portion is removed by etching. Forming a conductive film on the substrate, and patterning the conductive film by lift-off by removing the second portion after the formation of the conductive film. Method.
  3.   2. The pattern forming method according to claim 1, wherein the second portion has less film slippage in the etching removal step of the first portion.
  4.   A step of forming a lower layer electrode on an insulating substrate and covering the lower layer electrode to form an insulating film; and a resist mask patterned to have a plurality of thicknesses, and a thin region as a first portion Forming the resist mask having an opening formed in the first portion on the surface of the insulating film as a second portion having at least a silylated surface as a thick region, and using the resist mask as an etching mask Etching the insulating film to form a contact hole reaching the surface of the lower electrode in the opening, and subsequently covering the second portion remaining after etching away the first portion to cover the entire surface of the conductor film And a step of patterning the conductive film by lift-off by removing the second portion after the conductive film is formed. Pattern forming method.
  5.   Forming a first lower layer electrode or wiring on an insulating substrate and covering the first lower layer electrode or wiring to form a first insulating film; and at least above the first insulating film Forming a second lower layer electrode or wiring, covering the second lower layer electrode or wiring and forming a second insulating film, and a resist mask patterned to have a plurality of thicknesses The resist mask having an opening formed in the first portion, wherein the thin region is the first portion, the thick region is the second portion where the surface is silylated, and the surface of the second insulating film is used as the resist mask. And a contact hole reaching the surface of the first lower electrode in the opening by etching the first insulating film and the second insulating film using the resist mask as an etching mask. The second insulating film is etched. Forming a contact hole reaching the surface of the second lower electrode in the opening, and subsequently covering the second portion remaining after the first portion is removed by etching. A pattern forming method comprising: forming a conductive film; and patterning the conductive film by lift-off by removing the second portion after the conductive film is formed. .
  6.   2. The method of forming a thin film transistor according to claim 1, wherein the etching removal of the first portion is performed by dry etching using active species obtained by plasma excitation of a halogen compound gas and an oxygen gas.
  7.   The first and second insulating films, or the gate insulating film and the passivation film are dry etching, surface modification of the second portion is performed by the dry etching, and the first etching is performed by dry etching of the first portion. 6. The pattern forming method according to claim 1, wherein the second portion has a cross-sectional shape that is inversely tapered.
  8.   In a mask pattern of a photomask used in a photolithography process, a light shielding portion, a semi-translucent portion, and a translucent portion are formed, and the light shielding portion pattern, the semi-transparent portion pattern, and the translucent portion pattern are formed by one exposure. The pattern forming method according to claim 1, wherein the resist mask is formed through development after transferring and irradiating a resist film (photosensitive organic film).
  9.   The resist mask is formed through development after continuous exposure irradiation to a predetermined region of a resist film using two or more kinds of photomasks having different mask patterns in exposure in a photolithography process. The pattern formation method as described in any one of thru | or 5.
  10.   10. The pattern forming method according to claim 8, wherein the resist film is composed of two layers of resist films having different exposure sensitivities.
  11.   In a manufacturing process of an active matrix substrate for a liquid crystal display device, a contact hole is formed in a passivation film on a source / drain electrode of a thin film transistor and a gate insulating film on a gate electrode, and the source / drain electrode or the A resist mask obtained by patterning an electrode and a wiring connected to a gate electrode and a pixel electrode on a passivation film so as to have a plurality of thicknesses, wherein a thin region is a first portion and a thick region is at least Forming a thin film transistor using a resist mask having a second portion with less film slippage than the first portion.
  12.   In a manufacturing process of an active matrix substrate having a thin film transistor, a contact hole is formed in a gate insulating film on the gate electrode of the thin film transistor, an electrode connected to the gate electrode through the contact hole, a terminal electrode and a wiring, and gate insulation A resist mask obtained by patterning a source / drain electrode on a film so as to have a plurality of thicknesses, wherein a thin region is a first portion, and a thick region is at least less than a first portion. Forming a thin film transistor using a resist mask having two portions.
  13.   In a manufacturing process of an active matrix substrate for a liquid crystal display device, a contact hole is formed in a passivation film on a source / drain electrode of a thin film transistor and a gate insulating film on a gate electrode, and the source / drain electrode or the A resist mask obtained by patterning an electrode and a wiring connected to a gate electrode and a pixel electrode on a passivation film so as to have a plurality of thicknesses, wherein a thin region is a first portion and a thick region is at least Forming a thin film transistor using a resist mask having a second portion having a silylated surface.
  14.   In a manufacturing process of an active matrix substrate having a thin film transistor, a contact hole is formed in a gate insulating film on the gate electrode of the thin film transistor, an electrode connected to the gate electrode through the contact hole, a terminal electrode and a wiring, and gate insulation A resist mask obtained by patterning a source / drain electrode on a film so as to have a plurality of thicknesses, wherein a thin region is a first portion and a thick region is silylated at least on a surface. Forming a thin film transistor using the resist mask described above.
  15.   The resist mask is a resist film (photosensitive organic film) pattern having a plurality of thicknesses, and the resist film (photosensitive organic film) has a thick first portion and a thin second portion. 12. The patterning by etching the lower layer film using the first part and the second part as a mask and lift-off of the film formed after the second part is removed by etching. 14. The method for producing a thin film transistor according to any one of 14 above.
  16.   The first and second insulating films, or the gate insulating film and the passivation film are dry etching, surface modification of the second portion is performed by the dry etching, and the first etching is performed by dry etching of the first portion. 13. The method of manufacturing a thin film transistor according to claim 11 or 12, wherein the cross-sectional shape of the second portion is a reverse taper.
  17.   In a mask pattern of a photomask used in a photolithography process, a light shielding portion, a semi-translucent portion, and a translucent portion are formed, and the light shielding portion pattern, the semi-transparent portion pattern, and the translucent portion pattern are formed by one exposure. 15. The method of manufacturing a thin film transistor according to claim 11, wherein the resist mask is formed through development after transferring and irradiating a resist film (photosensitive organic film).
  18.   12. The resist mask is formed through development after continuous exposure irradiation to a predetermined region of a resist film using two or more kinds of photomasks having different mask patterns in exposure in a photolithography process. The method for producing a thin film transistor according to any one of claims 15 to 15.
  19.   19. The method of manufacturing a transistor according to claim 17, wherein the resist film is composed of two layers of resist films having different exposure sensitivities.
JP2006263631A 2006-09-27 2006-09-27 Pattern-forming method and thin-film transistor manufacturing method Pending JP2007059926A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006263631A JP2007059926A (en) 2006-09-27 2006-09-27 Pattern-forming method and thin-film transistor manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006263631A JP2007059926A (en) 2006-09-27 2006-09-27 Pattern-forming method and thin-film transistor manufacturing method

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2003321918 Division 2003-09-12

Publications (1)

Publication Number Publication Date
JP2007059926A true JP2007059926A (en) 2007-03-08

Family

ID=37923069

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006263631A Pending JP2007059926A (en) 2006-09-27 2006-09-27 Pattern-forming method and thin-film transistor manufacturing method

Country Status (1)

Country Link
JP (1) JP2007059926A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7799621B2 (en) 2007-11-13 2010-09-21 Mitsubishi Electric Corporation Method of manufacturing thin film transistor array substrate and display device
JP2015082624A (en) * 2013-10-24 2015-04-27 独立行政法人産業技術総合研究所 Method for manufacturing mold including high contrast alignment mark
JP2017523611A (en) * 2014-07-22 2017-08-17 深▲セン▼市華星光電技術有限公司 Method for manufacturing coplanar oxide semiconductor TFT substrate

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6476723A (en) * 1987-09-18 1989-03-22 Matsushita Electronics Corp Manufacture of semiconductor device
JPH01293620A (en) * 1988-05-23 1989-11-27 Nec Corp Manufacture of semiconductor device
JPH03278432A (en) * 1990-03-28 1991-12-10 Kawasaki Steel Corp Forming method for wiring of semiconductor device
JPH10163174A (en) * 1996-11-29 1998-06-19 Sharp Corp Patterning method of thin film
JPH1164887A (en) * 1997-08-22 1999-03-05 Furontetsuku:Kk Thin film transistor type liquid crystal display device and its production
JPH11307780A (en) * 1998-04-27 1999-11-05 Nec Kagoshima Ltd Manufacture for thin film transistor

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6476723A (en) * 1987-09-18 1989-03-22 Matsushita Electronics Corp Manufacture of semiconductor device
JPH01293620A (en) * 1988-05-23 1989-11-27 Nec Corp Manufacture of semiconductor device
JPH03278432A (en) * 1990-03-28 1991-12-10 Kawasaki Steel Corp Forming method for wiring of semiconductor device
JPH10163174A (en) * 1996-11-29 1998-06-19 Sharp Corp Patterning method of thin film
JPH1164887A (en) * 1997-08-22 1999-03-05 Furontetsuku:Kk Thin film transistor type liquid crystal display device and its production
JPH11307780A (en) * 1998-04-27 1999-11-05 Nec Kagoshima Ltd Manufacture for thin film transistor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7799621B2 (en) 2007-11-13 2010-09-21 Mitsubishi Electric Corporation Method of manufacturing thin film transistor array substrate and display device
JP2015082624A (en) * 2013-10-24 2015-04-27 独立行政法人産業技術総合研究所 Method for manufacturing mold including high contrast alignment mark
JP2017523611A (en) * 2014-07-22 2017-08-17 深▲セン▼市華星光電技術有限公司 Method for manufacturing coplanar oxide semiconductor TFT substrate

Similar Documents

Publication Publication Date Title
US6642580B1 (en) Thin film transistor array substrate and manufacturing method thereof
CN100576550C (en) Thin-film transistor array base-plate and manufacture method thereof
JP4883878B2 (en) Wiring contact structure, method of manufacturing the same, thin film transistor substrate including the same, and method of manufacturing the same
JP3415602B2 (en) Pattern formation method
KR100433463B1 (en) Pattern formation method and method of manufacturing display using it
JP3616584B2 (en) Pattern forming method and display device manufacturing method using the same
CN100435015C (en) Liquid crystal display device and fabricating method thereof
JP5270873B2 (en) Multi-tone optical mask, method of manufacturing the same, and method of manufacturing thin film transistor substrate using the same
EP0249211A2 (en) Method of manufacturing a thin film transistor
JP4728292B2 (en) Array substrate structure of thin film transistor liquid crystal display and manufacturing method thereof
JP5302275B2 (en) Contact portion of semiconductor element and manufacturing method thereof, thin film transistor array panel for display device, and manufacturing method thereof
JP4004835B2 (en) Method for manufacturing thin film transistor array substrate
US8324033B2 (en) TFT array substrate and manufacturing method thereof
KR100796756B1 (en) Contact portion of semiconductor device and method for manufacturing the same, and thin film transistor array panel for display device including the contact portion and method for manufacturing the same
US8049218B2 (en) TFT LCD array substrate and manufacturing method thereof
US7504342B2 (en) Photolithography method for fabricating thin film
JP4790134B2 (en) Method for manufacturing thin film transistor substrate for liquid crystal display device
TW526393B (en) Pattern forming method and method of manufacturing thin film transistor
JP3410617B2 (en) Thin film patterning method
CN100517075C (en) Manufacturing method for array substrate of thin film transistor LCD
US7157319B2 (en) Method of patterning a thin film transistor that includes simultaneously forming a gate electrode and a pixel electrode
JP4823989B2 (en) TFT-LCD array substrate and manufacturing method thereof
US20060023138A1 (en) Array substrate for LCD and fabrication method thereof
KR20010111552A (en) Pattern formation method and method of manufacturing display using it
JP2004163933A (en) Array substrate for liquid crystal display device and method of manufacturing the same

Legal Events

Date Code Title Description
A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20070414

A131 Notification of reasons for refusal

Effective date: 20070720

Free format text: JAPANESE INTERMEDIATE CODE: A131

A521 Written amendment

Effective date: 20070918

Free format text: JAPANESE INTERMEDIATE CODE: A523

A02 Decision of refusal

Effective date: 20071212

Free format text: JAPANESE INTERMEDIATE CODE: A02

A521 Written amendment

Effective date: 20080212

Free format text: JAPANESE INTERMEDIATE CODE: A523

A911 Transfer of reconsideration by examiner before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20080226

A912 Removal of reconsideration by examiner before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A912

Effective date: 20080328