CN103367353A - Active device and active device array substrate - Google Patents
Active device and active device array substrate Download PDFInfo
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- CN103367353A CN103367353A CN2012100920974A CN201210092097A CN103367353A CN 103367353 A CN103367353 A CN 103367353A CN 2012100920974 A CN2012100920974 A CN 2012100920974A CN 201210092097 A CN201210092097 A CN 201210092097A CN 103367353 A CN103367353 A CN 103367353A
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Abstract
The invention provides an active device and an active device array substrate. The active device array substrate comprises a substrate and a plurality of active devices located on the substrate. At least one of the active devices comprises a first transistor and a second transistor, wherein the first transistor is located on the substrate and provided with a first channel layer; the second transistor is stacked on the first transistor and provided with a second channel layer; the first transistor and the second transistor share a common grid electrode; and the common grid electrode is located between the first channel layer and the second channel layer.
Description
Technical field
The invention relates to a kind of active member and active component array base board, and particularly about a kind of twin-channel active member and active component array base board.
Background technology
In recent years, along with making rapid progress of electronic technology, have that high image quality, space utilization efficient are good, the Thin Film Transistor-LCD (Thin Film Transistor Liquid Crystal Display, TFT LCD) of low consumpting power, the advantageous characteristic such as radiationless becomes the main flow in market gradually.
Along with the demand of Thin Film Transistor-LCD large tracts of land and high-res, thin-film transistor must possess the carrier of high mobility, thereby orders about thin-film transistor and shorten it and discharge and recharge the time.In general, consider high mobility (mobility), high stability (stability) and low cost, the semiconductor layer of TFT can use amorphous silicon (amorphous silicon, a-Si) to make in the drive circuit.But amorphous silicon film transistor (a-Si TFT) is subject to the ontology-driven ability in the application of high-effect circuit, makes amorphous silicon film transistor can't integrate peripheral driving circuit and control circuit at a high speed.
In order to promote the electric current of opening of amorphous silicon film transistor, and further integrated circuit layout, reach the element area reducing, promote the pixel aperture ratio texts.Prior art for example changes channel width and the length of semiconductor layer by changing structure and the configuration of channel semiconductor layer, and right the method has the limit of processing procedure, causes that to promote the effect of opening electric current limited.Or be to utilize the raising component size to open electric current with raising, yet the method can cause the aperture opening ratio (aperture ratio) of pixel to descend, so that the reduction of Thin Film Transistor-LCD overall brightness, and the phenomenon that critical voltage (threshold voltage) is offset occurs easily.In addition, for example be again to utilize bigrid (dual gate) to promote out electric current.Yet, double-grid structure need comprise prepass (front channel) and the thin-film transistor of carrying on the back passage (back channel), wherein carry on the back passage because of in the processing procedure process easily to the channel layer injury, so there is the easily factor of decay in the electric current of double-grid structure, causes out current boost effects limited.In addition, the method also can't the integrated circuit layout, reaches lifting and the high brightness texts of element area reducing, pixel aperture ratio.
Summary of the invention
The invention provides a kind of active component array base board, it utilizes single grid and the three-dimensional stacked structure of binary channels, also reaches the effect that circuit layout is integrated when electric current is opened in lifting.
The invention provides a kind of active member, it utilizes single grid and twin-channel three-dimensional stacked structure, can effectively promote out electric current.
The invention provides a kind of active component array base board, comprise a substrate and be positioned at a plurality of active members on the substrate, wherein at least one active member comprises a first transistor and a transistor seconds.The first transistor is positioned on the substrate, and wherein the first transistor has a first passage layer.Transistor seconds is stacked on the first transistor, and wherein transistor seconds has a second channel layer.The first transistor and transistor seconds share same common grid, and common grid is between first passage layer and second channel layer.
In one embodiment of this invention, aforementioned the first transistor comprises the first source electrode, the first drain electrode, the first doped amorphous silicon layer and first grid insulating barrier.The first source electrode and the first drain electrode are between common grid and substrate.The first doped amorphous silicon layer is between the first source electrode and the first passage layer and between the first drain electrode and the first passage layer.First grid insulating barrier is between common grid and first passage layer.
In one embodiment of this invention, aforementioned transistor seconds comprises second gate insulating barrier, the second source electrode, the second drain electrode and the second doped amorphous silicon layer.The second gate insulating barrier is between common grid and second channel layer.The second source electrode and the second drain electrode are positioned at the both sides of second channel layer.The second doped amorphous silicon layer is between the second source electrode and the second channel layer and between the second drain electrode and the second channel layer.
In one embodiment of this invention, aforementioned the first transistor can electrically be connected with transistor seconds.
In one embodiment of this invention, aforementioned the first transistor is for example electrically in parallel with transistor seconds.
In one embodiment of this invention, aforementioned active component array base board can also comprise a protective layer and a pixel electrode, and wherein protective layer has an opening that exposes the second drain electrode, and pixel electrode is by opening and the second drain electrode electric connection.
In one embodiment of this invention; aforementioned active component array base board can also comprise a protective layer, a first signal line and a secondary signal line; wherein first grid insulating barrier has a contact hole that exposes the first source electrode; the first signal line is electrically connected by contact hole and the first source electrode; protective layer has one and exposes the second opening that drains, and the secondary signal line is electrically connected by opening and the second drain electrode.
The present invention provides a kind of active member in addition, and it is positioned on the substrate, and this active member comprises a first transistor and a transistor seconds.The first transistor is positioned on the substrate, and wherein the first transistor has a first passage layer.Transistor seconds is stacked on the first transistor, and wherein transistor seconds has a second channel layer.The first transistor and transistor seconds share same common grid, and common grid is between first passage layer and second channel layer.
Based on above-mentioned, active member in the active component array base board of the present invention utilizes single gate configuration between binary channels, to increase the effective width of element, the charging ability of thin-film transistor by this doubles, and utilization arranged perpendicular grid on substrate, binary channels and double source and two drain electrode, the circuit layout of two dimension is integrated with three dimensional constitution, make circuit layout area less, can effectively promote pixel aperture ratio, or can effectively reduce the circuit layout space, can solve the problem that thin-film transistor driving force of the prior art under the large scale and aperture opening ratio can not get both.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate accompanying drawing to be described in detail below.
Description of drawings
Fig. 1 is the generalized section of the active component array base board of first embodiment of the invention;
Fig. 2 A～Fig. 2 F is the schematic top plan view that the active component array base board of first embodiment of the invention is made flow process;
Fig. 3 is the generalized section of the active component array base board of second embodiment of the invention;
Fig. 4 A～Fig. 4 F is the schematic top plan view that the active component array base board of second embodiment of the invention is made flow process;
Fig. 5 is the schematic top plan view as active member in the active component array base board of the comparative example of present embodiment;
Fig. 6 A is the schematic top plan view of a kind of active member in the active component array base board of the third embodiment of the present invention;
Fig. 6 B is that Fig. 6 A is along the generalized section of A-A ' hatching line;
Fig. 7 is the generalized section of a kind of active component array base board in the third embodiment of the invention;
Fig. 8 is the perimeter circuit layout schematic top plan view of a comparative example;
Fig. 9 is the configuration schematic top plan view of one embodiment of the invention.
Description of reference numerals:
100,200,300,400: active component array base board;
110: substrate;
120,220,320: the first transistor;
122,222: the first source electrodes;
124, drain electrode in 224: the first;
126,226: the first doped amorphous silicon layers;
126a, 226a: the first impurity-doped amorphous silicon pattern;
127: first grid insulating barrier;
128,228: the first passage layer;
130,330: transistor seconds;
132: the second source electrodes; Drain electrode in 134: the second;
136: the second doped amorphous silicon layers; 137: the second gate insulating barrier;
138: the second channel layer; 140: common grid;
150: protective layer; 160: pixel electrode;
310: the first signal line; 340: the secondary signal line;
370: signal receives cabling; 380: signal output cabling;
610,620,630,640: grid;
T1, T2, T3, T4, T5: transistor;
W1: the first contact hole; W2: the second contact hole;
W3: the 3rd contact hole; W: opening;
P: space; A-A ': hatching line.
Embodiment
Fig. 1 is the generalized section of the active component array base board of first embodiment of the invention.Please refer to Fig. 1, the active component array base board 100 of present embodiment comprises substrate 110, the first transistor 120, transistor seconds 130, common grid 140, protective layer 150 and pixel electrode 160.The first transistor 120 is positioned on the substrate 110, and wherein the first transistor 120 has a first passage layer 128.Transistor seconds 130 is stacked on the first transistor 120, and wherein transistor seconds 130 has a second channel layer 138.The first transistor 120 shares same common grid 140 with transistor seconds 130, and common grid 140 is between first passage layer 128 and second channel layer 138.
Particularly, the first transistor 120 comprises the first source electrode 122, the first drain electrode the 124, first doped amorphous silicon layer 126 and first grid insulating barrier 127.The first source electrode 122 and the first drain electrode 124 are between common grid 140 and substrate 110.The first impurity-doped amorphous silicon pattern 126a separated from one another lays respectively between the first source electrode 122 and the first passage layer 128 and between the first drain electrode 124 and first passage layer 128 in the first doped amorphous silicon layer 126.First grid insulating barrier 127 is between common grid 140 and first passage layer 128.
In addition, transistor seconds 130 comprises second gate insulating barrier 137, the second source electrode 132, the second drain electrode the 134 and second doped amorphous silicon layer 136.Second gate insulating barrier 137 is between common grid 140 and second channel layer 138.The second source electrode 132 and the second drain electrode 134 are positioned at the both sides of second channel layer 138.The second doped amorphous silicon layer 136 is between the second source electrode 132 and the second channel layer 138 and between the second drain electrode 134 and the second channel layer 138.
It should be noted that present embodiment increases the charging ability of TFT element in the mode of double passage length under limited area, it makes flow process will be in following description.Fig. 2 A～Fig. 2 F is the schematic top plan view that the active component array base board of first embodiment of the invention is made flow process.
Please refer to Fig. 2 A, form the first metal layer (not illustrating) at substrate 110, and this first metal layer of patterning is to form the first source electrode 122 and the first drain electrode 124, wherein the first source electrode 122 and the first drain electrode 124 each other not conductings, its material is such as being the metal materials or metal laminated such as molybdenum (Mo), aluminium (Al), titanium (Ti).
Please refer to Fig. 2 B (owing to only indicate the rete that is positioned at the superiors in the top view, therefore partial component is not illustrated in Fig. 2 B, following description please refer to the relative position of Fig. 1 structure), form the first doped amorphous silicon layer (not illustrating) at the first source electrode 122 and the first drain electrode 124 sides with respect to substrate 110.For avoiding the first source electrode 122 and the first drain electrode 124 short circuits, this first doped amorphous silicon layer of patterning in advance removing the first doped amorphous silicon layer between the first source electrode 122 and the first drain electrode 124, and forms the first impurity-doped amorphous silicon pattern.In addition, the material of the first impurity-doped amorphous silicon pattern 126a for example is N-shaped doped amorphous silicon material.Form channel layer (not illustrating) at the first impurity-doped amorphous silicon pattern 126a.Etched channels layer (not illustrating) and the first impurity-doped amorphous silicon pattern 126a are to form first passage layer 128 and the first doped amorphous silicon layer 126 simultaneously, wherein the first doped amorphous silicon layer 126 comprises that two lay respectively at the first source electrode 122 and the first first impurity-doped amorphous silicon pattern 126as of drain electrode on 124, and the first impurity-doped amorphous silicon pattern 126a and first passage layer 128 trim.In addition, form first grid insulating barrier 127 on first passage layer 128.
It should be noted that in the present embodiment first passage layer 128 is between first grid insulating barrier 127 and the first source electrode 122 and the first drain electrode 124, this structure is a top grid (top gate) structure.In the application of LCD, if light source adopts direct-light-type backlight, because the first passage layer 128 of the first transistor 120 is exposed to (backlight) backlight irradiation, easily cause leakage phenomenon.Therefore; in the prior art; usually can increase extra shading processing procedure; for example add a metal and whole insulating barrier avoided leakage current; yet in the present embodiment; first passage layer 128 can adopt special transparent conductive oxide (transparent conductive oxide) semi-conducting material, for example is indium gallium zinc oxide.Because this kind material itself is subjected to illumination effect hardly, so can need not additionally to arrange the demand that light shield layer is avoided leakage current in the active member of present embodiment.Yet the present invention is not as limit, and in other embodiments, the material of first passage layer 128 also can be other semi-conducting materials.
Please refer to Fig. 1 and Fig. 2 C, form the second metal level (not illustrating) at first grid insulating barrier 127, and this second metal level of patterning to be to form common grid 140, and wherein the material of this common grid 140 is such as being the metal materials or metal laminated such as molybdenum (Mo), aluminium (Al), titanium (Ti).So far, the first transistor 120 is finished in the above described manner.Then, at the side formation second gate insulating barrier 137 of common grid 140 with respect to first grid insulating barrier 127.
Please refer to Fig. 1 and Fig. 2 D, sequentially form second channel layer 138 and the second doped amorphous silicon layer 136 at second gate insulating barrier 137 with respect to a side of substrate 110.
Please refer to Fig. 1 and Fig. 2 E, then form the second source electrode 132 and the second drain electrode 134 at the second doped amorphous silicon layer 136, wherein the second source electrode 132 and the second drain electrode 134 are separated from one another, and its material can be as aforementioned.At this, transistor seconds 130 is finished in the above described manner.
Please refer to Fig. 2 F, in the present embodiment, the first transistor 120 and transistor seconds 130 are for example for to promote out electric current with electrical parallel way.Please simultaneously with reference to Fig. 1 and Fig. 2 F, between first grid insulating barrier 127 and second gate insulating barrier 137, form the first contact hole W1 and the second contact hole W2.The first contact hole W1 and the second contact hole W2 expose respectively the first drain electrode the 124 and first source electrode 122, make the second drain electrode 134 see through the first contact hole W1 and the first drain electrode 124 electric connections, and the second source electrode 132 see through the second contact hole W2 and the first source electrode 122 is electrically connected.
It is worth mentioning that shown in Fig. 1 and Fig. 2 F, when this kind active member is applied in the active region in order to as the switch of pixel electrode the time, electrically the binary channels active member that consists of of the first transistor in parallel and transistor seconds can increase out electric current.This moment also can be on transistor seconds 130 protective mulch 150, and form the opening W that exposes the second drain electrode 134 at protective layer 150, so that pixel electrode 160 is electrically connected the second drain electrode 134 by opening W.
In addition, Fig. 3 is the generalized section of the active component array base board of second embodiment of the invention.As shown in Figure 3, the active component array base board 200 of present embodiment has similar components with the active component array base board 100 among Fig. 1, and the two Main Differences part of thought is: the stacking order of the first passage layer 228 in the first transistor 220, the first source electrode 222 and the first drain electrode the 224 and first doped amorphous silicon layer 226 is different.In detail, in the active component array base board 200 of present embodiment, the first source electrode 222 and the first drain electrode 224 are between first grid insulating barrier 127 and first passage layer 228.And in the active component array base board 100 of the first embodiment, first passage layer 128 is between first grid insulating barrier 127 and the first source electrode 122 and the first drain electrode 124.
Particularly, present embodiment also can increase the charging ability of TFT element, the making flow process of the active component array base board of following simple description the second embodiment in the mode of double passage length under limited area.Fig. 4 A～Fig. 4 F is the schematic top plan view that the active component array base board of second embodiment of the invention is made flow process.
Please refer to Fig. 4 and Fig. 4 A (owing to only indicate the rete that is positioned at the superiors in the top view, therefore partial component does not illustrate the B at Fig. 2, following description please refer to the relative position of Fig. 3 structure), on substrate 110, sequentially form channel layer (not illustrating) and the first doped amorphous silicon layer (not illustrating).While patterning channel layer and the first doped amorphous silicon layer, to form first passage layer 228 and the first impurity-doped amorphous silicon pattern 226a, this moment, first passage layer 228 had identical profile with the first impurity-doped amorphous silicon pattern 226a, for example was all a rectangular patterns.
Then please refer to Fig. 3 and Fig. 4 B, form the first metal layer (not illustrating) at first passage layer 228 with respect to substrate 110, for example be with mask pattern the first metal layer and the first impurity-doped amorphous silicon pattern 226a, exposing first passage layer 228, and the first 224 and first impurity-doped amorphous silicon pattern 226a that drains that forms the first source electrode 222 of trimming each other and the first impurity-doped amorphous silicon pattern 226a at first passage layer 228 and trim each other.
Similar to Fig. 2 C～Fig. 2 F flow process such as the successive process of Fig. 4 C～Fig. 4 F afterwards, therefore repeat no more.It should be noted that, the first source electrode 222 in the active component array base board 200 of Fig. 3 and the first drain electrode 224 are between first grid insulating barrier 127 and first passage layer 228, and wherein the material of first passage layer 228 can be crystal silicon, amorphous silicon, polysilicon, metal oxide and transparent conductive oxide semi-conducting material etc.In addition, it is worth mentioning that in the kind of thin-film transistor, this kind the first source electrode 222 and the structure of the first drain electrode 224 between first grid insulating barrier 127 and first passage layer 228 belong to back of the body channel thin film transistors.Compared to Fig. 1, present embodiment is because can be directly forming passage with backward channel etching (Back Channel Etch, the BCE) processing procedure of standard, and is comparatively simple on the processing procedure.Yet the passage conducting of Fig. 1 belongs to the prepass thin-film transistor, its excellence be in: compared to the back of the body channel transistor of the second embodiment, the prepass thin-film transistor of the first embodiment to open the electric current benefit better.
In the first embodiment and the second embodiment, active component array base board of the present invention can comprise the first transistor and the transistor seconds effective width with the increase element electrically in parallel, and then electric current is opened in lifting.Yet active component array base board of the present invention also can be the mode of electrical series connection, by vertical stratification integrated circuit layout, makes circuit area less, and more detailed content will be in following description.
Fig. 5 is the schematic top plan view as active member in the active component array base board of the comparative example of present embodiment, only illustrate partial component for clearly demonstrating, active member 300 in the active component array base board comprise the first transistor 320, transistor seconds 330 with and common grid 140, as shown in Figure 5, the first transistor 320 and transistor seconds 330 are mutually to connect with the planar structure of two dimension.Particularly, the first transistor 320 signal that comprises the first source electrode 222, the first drain electrode 224, first passage layer 228 and be electrically connected the first source electrode 222 receives cabling 370.The signal output cabling 380 that transistor seconds 330 comprises the second source electrode 132, the second drain electrode 134, second channel layer 138 and is electrically connected the second source electrode 132.In addition, first of the first transistor 320 the drain electrode 224 links to each other with the second drain electrode 134 of transistor seconds 330.This structure obviously as seen, the occupied circuit area of active member is directly proportional with number or the series winding quantity of transistor series, that is to say that this kind active member structure occupies area larger in the circuit.Thus, can reduce the area of overall circuit by the area of reduction transistor series.
Fig. 6 A is the schematic top plan view of a kind of active member in the active component array base board of the third embodiment of the present invention, it can be used to improve the arrangement space of the active member in as shown in Figure 5 the existing active component array base board, and Fig. 6 B is that Fig. 6 A is along the generalized section of A-A ' hatching line.Please refer to Fig. 6 A and Fig. 6 B, identical components represents with same-sign, the present invention can be stacked the first transistor 320 in the active member 300 of Fig. 5 and transistor seconds 330 by the three-dimensional structure of solid, and by the first drain electrode 224 of the first contact hole W1 electric connection the first transistor 320 and the second drain electrode 134 of transistor seconds 330, with series connection two transistor 320,330.In addition; form opening W in the protective layer 150 in the second drain electrode 134 of transistor seconds 330; signal output cabling 380 is electrically connected by the second drain electrode 134 of opening W and transistor seconds 330; and form the 3rd contact hole W3 in the first grid insulating barrier 127 on the first source electrode 222 of the first transistor 320, make signal receive cabling 370 and be electrically connected by the 3rd contact hole W3 and the first source electrode 222.Can be learnt obviously that by Fig. 6 A and Fig. 5 compared to comparative example, present embodiment utilizes vertical stratification can dwindle significantly the occupied circuit area of transistor series.In addition, this structure also can reduce the situation generation of leakage current.
It is interior in order to control pixel electrode to be noted that this kind active member also can be applicable to active region, opens electric current with increase.At this moment, can be on transistor seconds 330 protective mulch 150, and in protective layer 150, form the opening W that exposes the second drain electrode 134, making for example is that the pixel electrode that is configured in signal output cabling 380 positions is electrically connected the second drain electrode 134 by opening W.
In addition, active member of the present invention in other embodiments, also can be applicable to the cabling layout of peripheral circuit except can be applicable to as in the above-mentioned active region.Fig. 7 is the generalized section of a kind of active component array base board in the third embodiment of the invention.Please refer to Fig. 7, when making the cabling layout of peripheral circuit, manufacture method is similar to Fig. 4 A～Fig. 4 F, so repeat no more, difference place between the active member 400 of Fig. 7 and the active member 300 of Fig. 6 B mainly is: in the active member 400, do not form the contact hole W1 that runs through first grid insulating barrier 127 and second gate insulating barrier 137 between the first drain electrode the 224 and second drain electrode 134, at this moment, only form the 3rd contact hole W3 that exposes the first drain electrode 224 at first grid insulating barrier 127, make first signal line 310 be electrically connected the first source electrode 222 by the 3rd contact hole W3.And on transistor seconds 130 protective mulch 150, and form opening W at protective layer 150 and make secondary signal line 340 see through opening W to be electrically connected the second drain electrode 134.Utilize the active component array base board 300 of the 3rd embodiment can reach the effect of the layout area of reduction active member.Particularly, utilize vertical stratification to be made on the same area of circuit two active members, then can effectively reduce shading-area, and then reduction component size and capable of increasing opening rate.
As mentioned above, embodiments of the invention can reach to promote in the confined space and open electric current, reduce leakage current and reduce the element area occupied by the series and parallel of first and second transistor at vertical stratification.Below will do to describe more specifically for an embodiment.
Fig. 8 is the perimeter circuit layout schematic top plan view of a comparative example.Fig. 9 is the configuration schematic top plan view of one embodiment of the invention.Configuration among Fig. 8 comprises five transistor T 1～T5 and many cablings, and wherein cabling for example is the grid 630 of the grid 610 of clock signal (clock signal), the grid 620 of selecting signal (selection signal), data wire and the grid 640 of radiation control (Emission control) circuit.In Fig. 8, the first transistor T1 and the 3rd transistor T 3 common grids 620, and transistor seconds T2 has occupied larger circuit area because of the design requirement of breadth length ratio (W/L).Utilize the active member design that proposes in the above embodiment of the present invention, can be with Fig. 8 circuit integrated in as shown in Figure 9.Specifically, utilize vertical stratification to integrate the first transistor T1 and the 3rd transistor T 3, reduce into an area that transistor is shared with originally occupying two transistor areas.In addition, utilize the mode of aforementioned parallel connection can reduce 1/2～1/3 of the shared circuit area of transistor seconds T2.By this, can effectively increase aperture opening ratio and increase in the circuit and can utilize space P.In addition, the element of common grid is more in the circuit, and the effect of integrated circuit is also larger.
It is worth mentioning that active member of the present invention also has excellent performance in the application of Organic Light Emitting Diode (Organic Light-Emitting Diode, OLED).Because can reaching to promote, embodiments of the invention open the effect of electric current in the situation that does not increase the component size size, so can avoid producing greatly because of component size in the prior art phenomenon of critical voltage skew.
In sum, active member in the active component array base board of the present invention is by vertical stratification single grid to be formed between the binary channels, namely utilize common grid to place in the middle of the element that two transistor consists of, make common grid up and down between two active layers, therefore can be simultaneously when grid voltage drives produce passage in two active layers up and down, reach the effect of double passage, can make by this element open current multiplication.In addition, utilize the series and parallel pattern integrated circuit layout of vertical stratification, and reach the reduction component size, a kind of design that also can save space and the dynamical active member of tool can be provided under the demand of high electric current, high-res and high pixel aperture ratio.
It should be noted that at last: above each embodiment is not intended to limit only in order to technical scheme of the present invention to be described; Although with reference to aforementioned each embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment puts down in writing, and perhaps some or all of technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the scope of various embodiments of the present invention technical scheme.
Claims (14)
1. an active component array base board is characterized in that, comprising:
One substrate; And
A plurality of active members are positioned on this substrate, and wherein at least one active member comprises:
One the first transistor is positioned on this substrate, and wherein this first transistor has a first passage layer; And
One transistor seconds is stacked on this first transistor, and wherein this transistor seconds has a second channel layer, and this first transistor and this transistor seconds share same common grid, and this common grid is between this first passage layer and this second channel layer.
2. active component array base board according to claim 1 is characterized in that, wherein this first transistor comprises:
One first source electrode and one first drain electrode are between this common grid and substrate;
One first doped amorphous silicon layer is between this first source electrode and this first passage layer and between this first drain electrode and this first passage layer; And
One first grid insulating barrier is between this common grid and this first passage layer.
3. active component array base board according to claim 2 is characterized in that, wherein this first passage layer is between this first grid insulating barrier and this first source electrode and this first drain electrode.
4. active component array base board according to claim 2 is characterized in that, wherein this first source electrode and this first drain electrode are between this first grid insulating barrier and this first passage layer.
5. active component array base board according to claim 2 is characterized in that, wherein this transistor seconds comprises:
One second gate insulating barrier is between this common grid and this second channel layer;
One second source electrode and one second drains, and is positioned at the both sides of this second channel layer; And
One second doped amorphous silicon layer is between this second source electrode and this second channel layer and between this second drain electrode and this second channel layer.
6. active component array base board according to claim 5 is characterized in that, wherein this second channel layer is between this second gate insulating barrier and this second source electrode and this second drain electrode.
7. active component array base board according to claim 5, it is characterized in that, wherein this first grid insulating barrier and this second gate insulating barrier have one first contact hole, and this first contact hole exposes this first drain electrode, and this second drain electrode is electrically connected by this first contact hole and this first drain electrode.
8. active component array base board according to claim 7, it is characterized in that, comprise that also a signal receives cabling and signal output cabling, wherein this signal receives cabling and the electric connection of this first source electrode, and this signal output cabling and this second source electrode are electrically connected.
9. active component array base board according to claim 5, it is characterized in that, wherein this first grid insulating barrier and this second gate insulating barrier also comprise one second contact hole, and this second contact hole exposes this first source electrode, and this second source electrode is electrically connected by this second contact hole and this first source electrode.
10. active component array base board according to claim 9; it is characterized in that; also comprise a protective layer and a pixel electrode, wherein this protective layer has an opening that exposes this second drain electrode, and this pixel electrode is by this opening and this second drain electrode electric connection.
11. active component array base board according to claim 5; it is characterized in that; also comprise a protective layer, a first signal line and a secondary signal line; wherein this first grid insulating barrier has the 3rd contact hole that exposes this first source electrode; this first signal line is electrically connected by the 3rd contact hole and this first source electrode; this protective layer has one and exposes this second opening that drains, and this secondary signal line is electrically connected by this opening and this second drain electrode.
12. active component array base board according to claim 1 is characterized in that, wherein this first transistor is electrically connected with this transistor seconds.
13. active component array base board according to claim 1 is characterized in that, wherein this first transistor is electrically in parallel with this transistor seconds.
14. an active member is positioned on the substrate, it is characterized in that, this active member comprises:
One the first transistor is positioned on this substrate, and wherein this first transistor has a first passage layer;
One transistor seconds is stacked on this first transistor, and wherein this transistor seconds has a second channel layer, and this first transistor and this transistor seconds share same common grid, and this common grid is between this first passage layer and this second channel layer.
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| CN104317126A (en) * | 2014-11-13 | 2015-01-28 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device. |
| CN104409514A (en) * | 2014-11-21 | 2015-03-11 | 京东方科技集团股份有限公司 | Thin-film transistor structure, production method thereof and related device |
| CN104576755A (en) * | 2014-12-30 | 2015-04-29 | 深圳市华星光电技术有限公司 | Thin film transistor, array substrate and display device |
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