CN214477474U - Thin film transistor - Google Patents
Thin film transistor Download PDFInfo
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- CN214477474U CN214477474U CN202120745254.1U CN202120745254U CN214477474U CN 214477474 U CN214477474 U CN 214477474U CN 202120745254 U CN202120745254 U CN 202120745254U CN 214477474 U CN214477474 U CN 214477474U
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Abstract
The utility model discloses a thin film transistor, substrate base plate and active layer including range upon range of setting, the active layer include the channel district and locate channel district both sides with the conductor ization district that the channel district is connected, the channel district is equipped with the conductor layer that separates into a plurality of channels with the channel district. The utility model discloses an active layer separates into a plurality of channels with the channel zone through the conductor layer to make the effective channel length of active layer reduce, when the width of channel is definite, can improve drive circuit thin film transistor's output current, thereby satisfy user's demand. Furthermore, the utility model discloses an active layer structure can improve the output current of the thin-film transistor of multiple not isostructure, has certain universality.
Description
Technical Field
The utility model relates to a show technical field, especially relate to a thin film transistor.
Background
Thin-Film transistors (TFTs) are the main switching elements in current Liquid Crystal Displays (LCDs) and Active Matrix Organic electroluminescent displays (AMOLEDs), and are directly related to the performance of flat panel displays.
Thin film transistors can be classified into amorphous silicon thin film transistors (a-Si: H TFTs), polycrystalline silicon thin film transistors (P-Si TFTs), organic thin film transistors, and metal oxide thin film transistors according to the semiconductor material of the active layer of the TFTs. Among them, metal oxides have become mainstream channel materials of display devices at present due to their high mobility and light transmittance. However, the output current of the conventional oxide thin film transistor device has limitations and is affected by the channel size, so that it is difficult for the TFT panel to have a high driving current. For the same TFT device, the effective channel length determines the output current of the device, and the smaller the effective channel length is, the larger the on-current of the device will be. However, the effective channel length of the device is also limited, which is related to the process that the source electrode, the drain electrode and the active layer are contacted with each other and need to be conducted, when the channel is too short, the conduction of the active layer is possible, and the device fails. Therefore, how to increase the output current of the oxide thin film transistor becomes an objective requirement.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a touch panel solves among the prior art metal oxide thin film transistor output current small defect.
In order to achieve the above object, the present invention provides a thin film transistor, including substrate base plate and the active layer of range upon range of setting, the active layer include the channel region and locate channel region both sides with the conductor ization district that the channel region is connected, the channel region is equipped with separates into the conductor layer of a plurality of channels with the channel region.
Optionally, the plurality of channels are sequentially arranged at intervals along the length direction of the channel region.
Further, the conductor layer has a higher electrical conductivity than the channel.
Further, the conductor layer includes a plurality of conductors extending in a thickness direction of the channel region, and adjacent conductors are separated by corresponding channels.
Further, the width of any of the conductors is greater than the width of the adjacent channel.
Optionally, the device further includes a gate insulating layer and a gate, the gate insulating layer is disposed on a surface of the active layer on a side away from the substrate, the gate is disposed on a surface of the gate insulating layer on a side away from the active layer, and the gate corresponds to the channel region.
Optionally, the device further includes a gate insulating layer and a gate, the gate insulating layer is disposed on a surface of the active layer on a side close to the substrate, the gate is disposed on a surface of the gate insulating layer on a side close to the substrate, and the channel region corresponds to the gate.
The source electrode and the drain electrode are arranged on one side of the active layer, which is far away from the substrate base plate, and the source electrode and the drain electrode are respectively connected with the conductor regions on two sides of the channel region.
Furthermore, a barrier layer and a light shielding layer are arranged between the active layer and the substrate, the light shielding layer corresponds to the channel region, the barrier layer is arranged on one side of the active layer close to the substrate, and the light shielding layer is arranged on one side of the barrier layer close to the substrate.
Furthermore, an etching barrier layer is arranged on the surface of the active layer, which is far away from one side of the gate insulating layer.
The utility model has the advantages that:
the utility model discloses an active layer separates into a plurality of channels with the channel zone through the conductor layer to make the effective channel length of active layer reduce, when the width of channel is definite, can improve drive circuit thin film transistor's output current, thereby satisfy user's demand. Furthermore, the utility model discloses an active layer structure can improve the output current of the thin-film transistor of multiple not isostructure, has certain universality.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, and it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope of the present invention.
Fig. 1 is a schematic structural diagram of a thin film transistor according to embodiment 1 of the present invention;
fig. 2 is a schematic structural diagram of a channel region of a thin film transistor according to the present invention;
fig. 3 is a schematic structural diagram of the active layer of the thin film transistor according to the present invention;
fig. 4 is a schematic structural diagram of a thin film transistor according to embodiment 2 of the present invention;
fig. 5 is a schematic structural diagram of a thin film transistor according to embodiment 3 of the present invention.
Description of the main element symbols:
10-a substrate base plate; 20-an active layer; 21-a channel region; 211-a channel; 22-a region of electrical conductivity; 30-a conductor layer; 31-a conductor; 40-a gate; 50-a gate insulating layer; 60-source electrode; 70-a drain electrode; 80-a barrier layer; 90-a light-shielding layer; 100-a buffer layer; 110-an interlayer dielectric layer; 120-etch the barrier layer.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments.
The components of embodiments of the present invention, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the accompanying drawings, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. Based on the embodiment of the present invention, all other embodiments obtained by the person skilled in the art without creative work belong to the protection scope of the present invention.
Hereinafter, the terms "including", "having", and their derivatives, which may be used in various embodiments of the present invention, are only intended to indicate specific features, numbers, steps, operations, elements, components, or combinations of the foregoing, and should not be construed as first excluding the existence of, or adding to, one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.
In various embodiments of the present invention, the expression "a or/and B" includes any or all combinations of the words listed simultaneously, may include a, may include B, or may include both a and B.
In the description of the present invention, it is to be understood that the terms "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "lateral", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships illustrated in the drawings, and are used for convenience of description and simplicity of description only, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present invention. Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
In the description of the present invention, unless otherwise specified and limited, it is to be noted that the terms "mounted," "connected," and "connected" are to be interpreted broadly, for example, as mechanical connection, communication between two elements, direct connection, or indirect connection via an intermediate medium, and specific meanings of the terms may be understood by those skilled in the art according to specific situations. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of the present invention belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their contextual meaning in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in various embodiments of the present invention.
The term "plurality" refers to two or more.
Example 1
The utility model provides a thin film transistor, which comprises a substrate base plate 10 and an active layer 20. The thin film transistor of the embodiment is of a top gate structure, and can improve the output current of the thin film transistor to meet the requirements of users.
Referring to fig. 1, a substrate 10 and an active layer 20 are stacked, wherein the substrate 10 is made of a transparent material, such as a glass substrate, a quartz substrate, or a plastic substrate, and the substrate 10 in this embodiment is a flexible substrate made of polyimide. Referring to fig. 2, the active layer 20 includes a channel region 21 and a conductive region 22, wherein the channel region 21 is made of a metal Oxide, and the metal Oxide includes a combination of one or more of Indium, Gallium, Zinc and Tin, such as Zinc Oxide (ZnO), Indium Gallium Zinc Oxide (IGZO), Zinc Tin Oxide (ZTO), Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Indium Zinc Tin Oxide (IZTO), Indium Gallium Oxide (IGO), and the like. The conductive regions 22 are provided on both sides of the channel region 21 and connected to the channel region 21.
Referring also to fig. 3, the channel region 21 has a plurality of channels 211 separated by the conductive layer 30. The plurality of channels 211 are sequentially arranged at intervals along the length direction of the channel region 21, and two adjacent channels 211 are separated by the conductor layer 30. Further, the conductivity of the conductive layer 30 is higher than that of the channel 211, and when the on-current of the channel 211 reaches a corresponding value, the conductive layer 30 can conduct a plurality of spaced channels 211 to conduct the entire channel region 21. The conductive layer 30 may be made of ITO, or may be made of conductive metal material such as silver and gold. Specifically, the conductor layer 30 includes a plurality of conductors 31 extending in the thickness direction of the channel region 21, and adjacent conductors 31 are separated by corresponding channels 211, so that the channel region 21 is separated into a plurality of channels 211 by the conductors 31, and in the present embodiment, the width of any conductor 31 is greater than the width of the adjacent channel 211.
Since the channel region 21 is separated into the plurality of channels 211 by the plurality of conductors 31 and any two adjacent channels 211 are not connected to each other, the plurality of channels 211 of the channel region 21 form a zigzag structure, at this time, the effective channel length L of the active layer 20 is reduced, and for the same thin film transistor device, the smaller the effective channel length is, the larger the on-current of the device is, and the larger the output current of the thin film transistor panel is. Specifically, in the embodiment shown in fig. 3, the effective channel length of the active layer 20 is L1+ L2+ L3+ L4+ … … + Ln, which is smaller than the total length of the channel region, so that the on-current of the tft is larger than that of the tft of the conventional channel region structure, thereby increasing the output current of the tft panel to meet the user's requirement.
With continued reference to fig. 1, the tft further includes a gate electrode 40 and a gate insulating layer 50. Wherein, the gate insulating layer 50 is disposed on the surface of the active layer 20 far away from the substrate 10, and the gate electrode 40 is disposed on the surface of the gate insulating layer 50 far away from the active layer 20. The gate 40 corresponds to the channel region 21, and the gate 40 may be a single layer or a multi-layer structure made of metal or an alloy thereof, and the metal may be aluminum, copper, silver, molybdenum, titanium, or the like. The gate insulating layer 50 covers the surface of the channel region 21, so that in the subsequent process of the active layer 20 after the conductor processing, the gate insulating layer 50 can protect the channel region 21, and the width of the channel region 21 is prevented from being shortened, thereby preventing the short-channel effect of the thin film transistor. The gate insulating layer 50 may be made of an organic material or an oxide, wherein the organic material may be teflon, a silicon-based material, or an acrylic-based material, and the oxide may be aluminum oxide, silicon nitride, titanium oxide, or silicon aluminum oxide.
The thin film transistor further includes a source electrode 60 and a drain electrode 70, wherein the source electrode 60 and the drain electrode 70 are respectively disposed on the side of the active layer 20 away from the substrate 10 and are respectively connected to the conductive regions 22 on both sides of the channel region 21. The source electrode 60 and the drain electrode 70 may be a single layer or a multi-layer structure of metal or an alloy thereof, and the metal may be aluminum, copper, silver, molybdenum, titanium, or the like. In this embodiment, the source electrode 60 and the drain electrode 70 are separately disposed at two sides of the active layer 20 at an interval, so that the source electrode 60 and the drain electrode 70 are electrically separated.
The thin film transistor further includes a barrier layer 80 and a light-shielding layer 90, wherein the barrier layer 80 and the light-shielding layer 90 are respectively disposed between the substrate 10 and the active layer 20, the barrier layer 80 is disposed on a side of the active layer 20 close to the substrate 10, and the light-shielding layer 90 corresponds to the channel region 21 and is disposed on a side of the barrier layer 80 close to the substrate 10. The light shielding layer 90 is used to prevent external light from irradiating the active layer 20, so as to prevent the active layer 20 from generating photo-generated carriers during light irradiation to affect the electrical performance of the thin film transistor. It should be noted that, in order to make the light shielding layer 90 block as much external light as possible from being irradiated onto the channel region of the active layer 20, an orthographic projection of the light shielding layer 90 on the substrate 10 is greater than or equal to an orthographic projection of the channel region 21 of the active layer 20 on the substrate 10. The material of the light shielding layer 90 includes a metal material or an opaque polymer material, wherein the metal material may be chromium, aluminum, copper, or titanium, and the opaque polymer material may be a resin doped with a pigment. The barrier layer 80 is located between the light shielding layer 90 and the active layer 20 to separate the light shielding layer 90 from the active layer 20, so as to prevent the material of the light shielding layer 90 from diffusing into the active layer 20 to affect the electrical property of the active layer 20. The material of the barrier layer 80 may be an insulating material, such as an inorganic material or an organic material, wherein the inorganic material may be an oxide (such as aluminum oxide, silicon oxide, titanium oxide, or silicon aluminum oxide) or a nitride (such as silicon nitride), and the organic material may be a teflon or acryl based material.
The thin film transistor further includes a buffer layer 100 and an interlayer dielectric layer 110. Wherein the buffer layer 100 are disposed between the barrier layer 80 and the substrate 10, and the buffer layer 100 can prevent impurities in the substrate 10 from diffusing into the active layer 20, thereby preventing the impurities from affecting the electrical performance of the thin film transistor. The buffer layer 100 may be a single layer or double layer SiN layer with uniform and dense structurexOr SiOx. An interlayer dielectric layer 110 is disposed on the surface of the gate electrode 40 away from the gate insulating layer 50, and the material of the interlayer dielectric layer 110 includes, but is not limited to, SiNxOr SiOx. Two spaced via holes are formed in the interlayer dielectric layer 110, the gate electrode 40 is covered by the interlayer dielectric layer 110 between the two via holes, and the source electrode 60 and the drain electrode 70 are disposed on both sides of the gate electrode 40 and are in contact with the active layer 20 through the two via holes, respectively.
In this embodiment, the manufacturing process of the top gate thin film transistor is as follows: manufacturing a substrate 10, sequentially forming a buffer layer 100, a light shielding layer 90 and a barrier layer 80 on the substrate 10, then completing film deposition of an active layer 20 on the barrier layer 80, forming the active layer 20 after exposure, development and etching processes, forming a plurality of channels 211 arranged at intervals in a channel region 21, depositing a conductor layer 30 on the film of the active layer 20 after the active layer 20 is etched, respectively arranging conductors 31 at intervals between adjacent channels 211 after the conductor layer 30 is etched, and then sequentially forming a gate insulating layer 50, a gate electrode 40, an interlayer dielectric layer 110, a source electrode 60 and a drain electrode 70 to obtain the top gate type thin film transistor of the embodiment.
Example 2
The thin film transistor provided in this embodiment includes a substrate 10 and an active layer 20. The thin film transistor is of a back channel etching structure, and the output current of the thin film transistor can be improved so as to meet the requirements of users.
Referring to fig. 4, a substrate 10 and an active layer 20 are stacked, wherein the substrate 10 is made of a transparent material, for example, the substrate 10 can be a glass substrate, a quartz substrate or a plastic substrate, and the substrate 10 in this embodiment is a flexible substrate made of polyimide. The structure of the active layer 20 of this embodiment is the same as that of the active layer 20 of embodiment 1.
The thin film transistor further includes a gate electrode 40 and a gate insulating layer 50, wherein the gate insulating layer 50 is disposed on a surface of the active layer 20 close to the substrate 10, and the gate electrode 40 is disposed on a surface of the gate insulating layer 50 close to the substrate 10. The gate electrode 40 may be a single layer or a multi-layer structure made of metal or its alloy, and the metal may be aluminum, copper, silver, molybdenum, or titanium. The gate insulating layer 50 may be made of an organic material or an oxide, wherein the organic material may be teflon, a silicon-based material, or an acrylic-based material, and the oxide may be aluminum oxide, silicon nitride, titanium oxide, or silicon aluminum oxide.
In the present embodiment, the thin film transistor further includes a source electrode 60 and a drain electrode 70, and the source electrode 60 and the drain electrode 70 are respectively disposed on the side of the active layer 20 away from the substrate 10 and are respectively connected to the conductive regions 22 on both sides of the channel region 21. The source electrode 60 and the drain electrode 70 may be a single layer or a multi-layer structure of metal or an alloy thereof, and the metal may be aluminum, copper, silver, molybdenum, titanium, or the like. In this embodiment, the source electrode 60 and the drain electrode 70 are separately disposed at two sides of the active layer 20 at an interval, so that the source electrode 60 and the drain electrode 70 are electrically separated.
In the present embodiment, the thin film transistor further includes a barrier layer 80 and a buffer layer 100, wherein the barrier layer 80 is disposed on the side of the gate 40 close to the substrate 10, and the material of the barrier layer 80 can be an insulating material, such as an inorganic material or an organic material, wherein the inorganic material can be an oxide (such as aluminum oxide, silicon oxide, titanium oxide, or silicon aluminum oxide) or a nitride (such as silicon nitride), and the organic material can be a teflon or acrylic based material. The buffer layer 100 is disposed between the base substrate 10 and the barrier layer 80. The buffer layer 100 may be a single layer or double layer SiN layer with uniform and dense structurexOr SiOx。
In this embodiment, the manufacturing process of the back channel etching type thin film transistor is as follows: manufacturing a substrate 10, sequentially forming a buffer layer 100, a barrier layer 80, a gate electrode 40 and a gate insulating layer 50 on the substrate 10, then completing film deposition of an active layer 20 on the gate insulating layer 50, forming the active layer 20 after exposure, development and etching processes, forming a plurality of channels 211 arranged at intervals in a channel region 21, depositing a conductor layer 30 on the film of the active layer 20 after the active layer 20 is etched, respectively arranging conductors 31 at intervals between adjacent channels 211 after the conductor layer is etched, and then forming a source electrode 60 and a drain electrode 70, thereby obtaining the back channel etched thin film transistor of the embodiment.
Example 3
The thin film transistor provided in this embodiment includes a substrate 10 and an active layer 20. The thin film transistor is an etching barrier layer structure, and the output current of the thin film transistor can be improved so as to meet the requirements of users.
Referring to fig. 5, a substrate 10 and an active layer 20 are stacked, wherein the substrate 10 is made of a transparent material, for example, the substrate 10 can be a glass substrate, a quartz substrate or a plastic substrate, and the substrate 10 in this embodiment is a flexible substrate made of polyimide. The structure of the active layer 20 of this embodiment is the same as that of the active layer 20 of embodiment 1.
In this embodiment, the thin film transistor further includes a gate electrode 40, a gate insulating layer 50, a source electrode 60, a drain electrode 70, a barrier layer 80 and a buffer layer 100, the structure of which is the same as that in embodiment 2, the gate insulating layer 50 may be made of an organic material or an oxide, wherein the organic material may be teflon, a silicon-based material or an acrylic-based material, and the oxide may be aluminum oxide, silicon nitride, titanium oxide or silicon aluminum oxide.
In the present embodiment, the thin film transistor further includes an etch stop layer 120, and the etch stop layer 120 is disposed on a surface of the active layer 20 on a side away from the gate insulating layer 50, and can protect the active layer 20 from being damaged when the source electrode 60 and the drain electrode 70 are formed, thereby improving the performance of the thin film transistor. Etch stop layer 120 may be an organic material, such as an organosilicone compound, or a single layer of an inorganic material, such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, hafnium oxide, or a combination thereof.
In this embodiment, the manufacturing process of the etching barrier layer type thin film transistor is as follows: manufacturing a substrate 10, sequentially forming a buffer layer 100, a barrier layer 80, a gate electrode 40 and a gate insulating layer 50 on the substrate 10, then completing film deposition of an active layer 20 on the gate insulating layer 50, forming the active layer 20 after exposure, development and etching processes, forming a plurality of channels 211 arranged at intervals in a channel region 21, depositing a conductor layer 30 on the film of the active layer 20 after the active layer 20 is etched, respectively arranging conductors 31 at intervals between adjacent channels 211 after the conductor layer is etched, and then forming a source electrode 60, a drain electrode 70 and an etching barrier layer 120 to obtain the etching barrier layer type thin film transistor of the embodiment.
In the thin film transistor provided in embodiments 1, 2, and 3 of the present application, the active layer 20 separates the channel region 21 into a plurality of channels 211 through the conductive layer 30, so that the effective channel length of the active layer 20 is reduced, and when the width of the channel is constant, the output current of the thin film transistor of the driving circuit can be increased, thereby meeting the requirements of users. The active layer 20 structure is used for a top gate type thin film transistor, a back channel etching type thin film transistor and an etching barrier layer type thin film transistor, which can improve the output current of the thin film transistor, thereby having certain universality.
Those skilled in the art will appreciate that the drawings are merely schematic representations of one preferred implementation scenario and that the blocks or flow diagrams in the drawings are not necessarily required to practice the present invention.
Those skilled in the art will appreciate that the modules in the devices in the implementation scenario may be distributed in the devices in the implementation scenario according to the description of the implementation scenario, or may be located in one or more devices different from the present implementation scenario with corresponding changes. The modules of the implementation scenario may be combined into one module, or may be further split into a plurality of sub-modules.
The above description is only exemplary of the preferred embodiments of the present invention, and should not be construed as limiting the present invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims (10)
1. The thin film transistor is characterized by comprising a substrate base plate and an active layer which are arranged in a stacked mode, wherein the active layer comprises a channel region and conductive regions which are arranged on two sides of the channel region and connected with the channel region, and the channel region is provided with a conductor layer which divides the channel region into a plurality of channels.
2. The thin film transistor according to claim 1, wherein a plurality of the channels are sequentially arranged at intervals in a length direction of the channel region.
3. The thin film transistor according to claim 1, wherein a conductivity of the conductor layer is higher than a conductivity of the channel.
4. The thin film transistor according to claim 1, wherein the conductor layer includes a plurality of conductors extending in a thickness direction of the channel region, adjacent ones of the conductors being separated by respective channels.
5. The thin film transistor of claim 4, wherein a width of any of the conductors is greater than a width of an adjacent channel.
6. The thin film transistor according to claim 1, further comprising a gate insulating layer provided on a surface of the active layer on a side away from the substrate, and a gate electrode provided on a surface of the gate insulating layer on a side away from the active layer, the gate electrode corresponding to the channel region.
7. The thin film transistor according to claim 1, further comprising a gate insulating layer provided on a surface of the active layer on a side close to the base substrate, and a gate electrode provided on a surface of the gate insulating layer on a side close to the base substrate, wherein the channel region corresponds to the gate electrode.
8. The thin film transistor according to claim 6 or 7, further comprising a source electrode and a drain electrode, wherein the source electrode and the drain electrode are disposed on a side of the active layer away from the substrate, and the source electrode and the drain electrode are respectively connected to the conductive regions on both sides of the channel region.
9. The thin film transistor of claim 6, wherein a barrier layer and a light-shielding layer are disposed between the active layer and the substrate, the light-shielding layer corresponding to the channel region, the barrier layer is disposed on a side of the active layer adjacent to the substrate, and the light-shielding layer is disposed on a side of the barrier layer adjacent to the substrate.
10. The thin film transistor according to claim 7, wherein an etching stopper layer is provided on a surface of the active layer on a side away from the gate insulating layer.
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| CN202120745254.1U CN214477474U (en) | 2021-04-12 | 2021-04-12 | Thin film transistor |
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| CN202120745254.1U CN214477474U (en) | 2021-04-12 | 2021-04-12 | Thin film transistor |
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| WO2024011658A1 (en) * | 2022-07-14 | 2024-01-18 | Tcl华星光电技术有限公司 | Display panel |
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| WO2024011658A1 (en) * | 2022-07-14 | 2024-01-18 | Tcl华星光电技术有限公司 | Display panel |
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Granted publication date: 20211022 |