JPH054521U - Insulated gate type field effect transistor - Google Patents

Insulated gate type field effect transistor

Info

Publication number
JPH054521U
JPH054521U JP4862791U JP4862791U JPH054521U JP H054521 U JPH054521 U JP H054521U JP 4862791 U JP4862791 U JP 4862791U JP 4862791 U JP4862791 U JP 4862791U JP H054521 U JPH054521 U JP H054521U
Authority
JP
Japan
Prior art keywords
gate
electrode
gate electrode
connecting portion
field effect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4862791U
Other languages
Japanese (ja)
Inventor
和徳 大野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP4862791U priority Critical patent/JPH054521U/en
Publication of JPH054521U publication Critical patent/JPH054521U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】 【目的】 絶縁ゲート型電界効果トランジスタの高周波
特性を改善すること。 【構成】 複数のゲート電極(11)を連結部(12)
によって櫛歯状に形成し、連結部(12)に拡大部(1
6)を形成し、拡大部(16)を含み連結部(12)の
略全面に取出し電極(14)をオーミック接触させる。
(57) [Abstract] [Purpose] To improve the high frequency characteristics of an insulated gate field effect transistor. [Structure] A plurality of gate electrodes (11) are connected to each other (12)
To form a comb-like shape, and the connecting portion (12) has an enlarged portion (1
6) is formed, and the extraction electrode (14) is brought into ohmic contact with substantially the entire surface of the connecting portion (12) including the enlarged portion (16).

Description

【考案の詳細な説明】[Detailed description of the device]

【0001】[0001]

【産業上の利用分野】[Industrial applications]

本考案は、ディスクリートの高周波用絶縁ゲート型電界効果トランジスタに関 する。   The present invention relates to a discrete high frequency insulated gate field effect transistor. To do.

【0002】[0002]

【従来の技術】[Prior art]

従来のこの種の装置を図4に示す。この装置は、シリコン基板上にゲート酸化 膜を介して複数本のポリシリコンゲート電極(1)を多数本平行に形成し、ゲー ト電極(1)の一端を連結部(2)で接続することにより、ゲート電極(1)全 体を櫛歯状のパターンとし、連結部(2)の一端にコンタクトホール(3)を形 成し、このコンタクトホール(3)を介してAl取出し電極(4)がオーミック 接触し、取出し電極(4)が絶縁膜上を延在して電極パッド(5)に接続したも のである(例えば、特開昭61−214579号)。   A conventional device of this type is shown in FIG. This device uses a gate oxide on a silicon substrate. A plurality of polysilicon gate electrodes (1) are formed in parallel through the film, By connecting one end of the gate electrode (1) with the connecting portion (2), the entire gate electrode (1) is The body has a comb-shaped pattern, and a contact hole (3) is formed at one end of the connecting part (2). And the Al extraction electrode (4) is ohmic through the contact hole (3). When contacted, the extraction electrode (4) extended over the insulating film and connected to the electrode pad (5). (For example, JP-A-61-214579).

【0003】 デュアルゲート型の場合、ゲート電極(1)の隣接する2本がペアとなって1 つの単位トランジスタセルを構成する。[0003]   In the case of a dual gate type, two adjacent gate electrodes (1) form a pair and One unit transistor cell is formed.

【0004】[0004]

【考案が解決しようとする課題】[Problems to be solved by the device]

しかしながら、図4の如き従来の絶縁ゲート型電界効果トランジスタでは、取 出し電極(4)がゲート電極(1)の連結部(2)の一端にコンタクトするだけ であり、連結部(2)のポリシリコン層の抵抗分が大きくなってしまう。そのた め、単位トランジスタセルへの信号伝達が均等に成されず、例えばVHF帯の如 き高周波帯で、利得の低下、ノイズレベルの悪化という欠点があった。   However, in the conventional insulated gate field effect transistor as shown in FIG. The output electrode (4) only contacts one end of the connecting portion (2) of the gate electrode (1) Therefore, the resistance of the polysilicon layer of the connecting portion (2) increases. That Therefore, the signal transmission to the unit transistor cells is not evenly performed, such as in the VHF band. In the high frequency band, there are drawbacks such as reduction of gain and deterioration of noise level.

【0005】[0005]

【課題を解決するための手段】[Means for Solving the Problems]

本考案は上述した欠点に鑑み成されたもので、櫛歯パターンの歯の部分に相当 するゲート電極(11)と連結部(12)との接続部全てに取出し電極(14) がオーミック接触するようにコンタクトホール(13)を設けると共に、ゲート 電極(11)の連結部(12)に拡大部(16)を設けることにより、高周波特 性を改善した絶縁ゲート型電界効果トランジスタを提供するものである。   The present invention has been made in view of the above-mentioned drawbacks, and corresponds to a tooth portion of a comb tooth pattern. Extraction electrode (14) at all the connecting portions between the gate electrode (11) and the connecting portion (12) A contact hole (13) to make ohmic contact with By providing the enlarged portion (16) in the connecting portion (12) of the electrode (11), a high frequency characteristic can be obtained. Provided is an insulated gate field effect transistor having improved characteristics.

【0006】[0006]

【作用】[Action]

本考案によれば、連結部(12)の略全長にわたって低抵抗の取出し電極(1 4)をオーミック接触させることにより、各セルのゲート電極(11)に均等に 信号伝達できる。また、連結部(12)の一部を拡大したことにより、連結部( 12)と取出し電極(14)とのコンタクト抵抗を大幅に低減できる。   According to the present invention, the extraction electrode (1) having a low resistance is provided over substantially the entire length of the connecting part (12). By making 4) ohmic contact, the gate electrodes (11) of each cell are evenly distributed. Can signal. Further, by enlarging a part of the connecting portion (12), the connecting portion ( The contact resistance between 12) and the extraction electrode (14) can be significantly reduced.

【0007】[0007]

【実施例】【Example】

以下に本考案の一実施例を図面を参照しながら詳細に説明する。   An embodiment of the present invention will be described below in detail with reference to the drawings.

【0008】 図1は本考案の装置のゲート電極(11)のパターンを示す平面図、図2は1 つのセルを示す平面図、図3はその断面図である。[0008]   FIG. 1 is a plan view showing a pattern of a gate electrode (11) of the device of the present invention, and FIG. FIG. 3 is a plan view showing one cell, and FIG. 3 is a sectional view thereof.

【0009】 図1において、(11)は基体表面のゲート酸化膜上を延在するポリシリコン ゲート電極、(12)はゲート電極(11)と同層のポリシリコン層で形成する ゲート電極(11)の連結部、(13)はゲート電極(11)を被覆する絶縁膜 を開口したコンタクトホール、(14)はコンタクトホール(13)を介してそ の下の連結部(12)にオーミック接触するAl取出し電極、(15)は取出し 電極(14)から連続する外部接続用のボンディングパッド、(16)は連結部 (12)の一部を拡大した拡大部である。[0009]   In FIG. 1, (11) is polysilicon extending on the gate oxide film on the substrate surface. The gate electrode (12) is formed of the same polysilicon layer as the gate electrode (11) A connecting portion of the gate electrode (11), and (13) an insulating film covering the gate electrode (11) The contact hole (14) is opened through the contact hole (13). Al take-out electrode in ohmic contact with the lower connecting part (12), (15) take-out Bonding pad for external connection continuous from the electrode (14), and (16) connecting part It is an enlarged portion obtained by enlarging a part of (12).

【0010】 平行に延在するゲート電極(11)は、これと直交するように延在する連結部 (12)によってその一端が共通接続され、全体として櫛歯状のパターンを形成 する。コンタクトホール(13)は、連結部(12)および連結部(12)の拡 大部(16)の形状に沿うように、最大の面積で形成する。この素子がデュアル ゲート型の絶縁ゲート型電界効果トランジスタである場合、前記拡大部(16) は第1ゲート用の電極に対して設けられ、2本のゲート電極(11)がペアとな って1つのセルを構成する。[0010]   The gate electrode (11) extending in parallel has a connecting portion extending so as to be orthogonal thereto. One end is commonly connected by (12), and a comb-shaped pattern is formed as a whole. To do. The contact hole (13) is provided with a connecting portion (12) and an expansion of the connecting portion (12). It is formed with the maximum area so as to follow the shape of the large part (16). This element is dual In the case of a gate type insulated gate field effect transistor, the enlarged portion (16) Is provided for the electrode for the first gate, and the two gate electrodes (11) form a pair. That constitutes one cell.

【0011】 図2はデュアルゲート型素子の1つのセルを示す。中央にドレイン電極がオー ミックコンタクトするコンタクトホール(17)が形成され、その周囲を第2ゲ ート電極(18)が囲むように配置され、さらにその外側の第1ゲート電極(1 1)が櫛歯状に延在する。ソース電極用のコンタクトホール(19)は第1ゲー ト電極(11)の外側に位置する。[0011]   FIG. 2 shows one cell of a dual gate type device. The drain electrode is in the center A contact hole (17) for making a close contact is formed, and a second gate is formed around the contact hole. The gate electrode (18) so as to surround the first gate electrode (1). 1) extends in a comb shape. The contact hole (19) for the source electrode is the first gate. Located outside the electrode (11).

【0012】 図3はその断面図である。P型のシリコン基板(20)の表面にN型のソース 領域(21)とドレイン領域(22)、および中間領域(23)を形成し、P+ 型コンタクト領域(24)を介してソース電極(25)により基板(20)にバ ックゲートバイアスを与え、ゲート絶縁膜(26)上に第1と第2のゲート電極 (11)(18)を形成し、第1と第2のゲート電極(11)(18)をCVD 酸化膜(27)で被覆し、ドレイン領域(22)表面にドレイン電極(28)を 配置してある。この素子をVHF帯のチューナ回路で使用する場合は、ソ−ス接 地とし、第1ゲート電極(11)に信号入力が印加され、高周波的に接地された 第2ゲート電極(18)に印加されるバイアス電圧を調整することにより、ドレ イン電流を可変し、電力利得を調整する形で動作させる。FIG. 3 is a sectional view thereof. P-type silicon substrate (20) a source region (21) and the drain region N-type on the surface of the (22), and an intermediate region (23) is formed, the source electrode through a P + -type contact region (24) ( A back gate bias is applied to the substrate (20) by means of 25), and first and second gate electrodes (11) and (18) are formed on the gate insulating film (26), and the first and second gate electrodes (11) are formed. (18) is covered with a CVD oxide film (27), and a drain electrode (28) is arranged on the surface of the drain region (22). When this element is used in a VHF band tuner circuit, the source is grounded, a signal input is applied to the first gate electrode (11), and a signal is applied to the second gate electrode (18) grounded at high frequency. By adjusting the bias voltage, the drain current is changed and the power gain is adjusted.

【0013】 以上に説明した本考案の素子は、低抵抗の取出し電極(14)が各セルのゲー ト電極(11)と連結部(12)との接続部分の全てにオーミック接触している ので、各セルのゲート電極(11)を均等に動作させることができる。さらに、 連結部(12)に拡大部(16)を形成することにより、取出し電極(14)と 連結部(12)とのコンタクト抵抗を大幅に低減できる。従って、高周波抵抗成 分を減じることができるので、高周波利得を向上し、NFを改善できる。[0013]   In the device of the present invention described above, the low-resistance take-out electrode (14) is used for the gate of each cell. Ohmic contact is made with all the connecting portions between the electrode (11) and the connecting portion (12). Therefore, the gate electrode (11) of each cell can be operated uniformly. further, By forming the enlarged portion (16) in the connecting portion (12), the extraction electrode (14) and The contact resistance with the connecting portion (12) can be significantly reduced. Therefore, high frequency resistance Since the amount can be reduced, the high frequency gain can be improved and the NF can be improved.

【0014】[0014]

【考案の効果】[Effect of device]

以上に説明したように、本考案によれば、各セルに均一に信号伝達でき、信号 損失の少いパターンレイアウトにできる利点を有する。さらに、コンタクト抵抗 を低減できるので、高周波利得を向上し、ノイズレベルを低減できる利点をも有 する。   As described above, according to the present invention, the signal can be uniformly transmitted to each cell. It has an advantage that a pattern layout with less loss can be realized. In addition, contact resistance It also has the advantage of improving the high frequency gain and reducing the noise level. To do.

【図面の簡単な説明】[Brief description of drawings]

【図1】本考案を説明するための平面図である。FIG. 1 is a plan view for explaining the present invention.

【図2】1つのセルを示す平面図である。FIG. 2 is a plan view showing one cell.

【図3】セル部分を示す断面図である。FIG. 3 is a cross-sectional view showing a cell portion.

【図4】従来例を説明する平面図である。FIG. 4 is a plan view illustrating a conventional example.

Claims (2)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】 半導体基板上に形成した絶縁膜と、前記
絶縁膜上に平行に配置された複数本のゲート電極と、前
記ゲート電極に直交するように延在して前記ゲート電極
の一端を連結する前記ゲート電極の連結部と、前記ゲー
ト電極を被覆する絶縁膜と、前記絶縁膜を開口したコン
タクトホールを介して前記ゲート電極の連結部にオーミ
ック接触する取出し電極とを具備する絶縁ゲート型電界
効果トランジスタにおいて、 前記取出し電極は前記ゲート電極の連結部の略全長にわ
たり接触すると共に、前記ゲート電極の連結部に拡大部
を設けたことを特徴とする絶縁ゲート型電界効果トラン
ジスタ。
1. An insulating film formed on a semiconductor substrate, a plurality of gate electrodes arranged in parallel on the insulating film, and one end of the gate electrode extending perpendicularly to the gate electrode. Insulated gate type including a connecting portion of the gate electrode to be connected, an insulating film covering the gate electrode, and an extraction electrode in ohmic contact with the connecting portion of the gate electrode through a contact hole formed in the insulating film. In the field effect transistor, the extraction electrode is in contact with substantially the entire length of the connecting portion of the gate electrode, and an enlarged portion is provided in the connecting portion of the gate electrode.
【請求項2】 前記ゲート電極がデュアルゲート型電界
効果トランジスタの第1ゲートであることを特徴とする
絶縁ゲート型電界効果トランジスタ。
2. The insulated gate field effect transistor, wherein the gate electrode is a first gate of a dual gate field effect transistor.
JP4862791U 1991-06-26 1991-06-26 Insulated gate type field effect transistor Pending JPH054521U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4862791U JPH054521U (en) 1991-06-26 1991-06-26 Insulated gate type field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4862791U JPH054521U (en) 1991-06-26 1991-06-26 Insulated gate type field effect transistor

Publications (1)

Publication Number Publication Date
JPH054521U true JPH054521U (en) 1993-01-22

Family

ID=12808633

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4862791U Pending JPH054521U (en) 1991-06-26 1991-06-26 Insulated gate type field effect transistor

Country Status (1)

Country Link
JP (1) JPH054521U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006165524A (en) * 2004-11-05 2006-06-22 Infineon Technologies Ag High-frequency switching transistor and high-frequency circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61214579A (en) * 1985-03-20 1986-09-24 Toshiba Corp Insulated gate type field effect transistor
JPS62134971A (en) * 1985-12-06 1987-06-18 Citizen Watch Co Ltd Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61214579A (en) * 1985-03-20 1986-09-24 Toshiba Corp Insulated gate type field effect transistor
JPS62134971A (en) * 1985-12-06 1987-06-18 Citizen Watch Co Ltd Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006165524A (en) * 2004-11-05 2006-06-22 Infineon Technologies Ag High-frequency switching transistor and high-frequency circuit
JP4579134B2 (en) * 2004-11-05 2010-11-10 インフィネオン テクノロジーズ アクチエンゲゼルシャフト High frequency switching transistor and high frequency circuit
US8525272B2 (en) 2004-11-05 2013-09-03 Infineon Technologies Ag High-frequency switching transistor and high-frequency circuit

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