JPS62134971A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62134971A JPS62134971A JP27462185A JP27462185A JPS62134971A JP S62134971 A JPS62134971 A JP S62134971A JP 27462185 A JP27462185 A JP 27462185A JP 27462185 A JP27462185 A JP 27462185A JP S62134971 A JPS62134971 A JP S62134971A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- electrode
- mosfet
- semiconductor device
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000000463 material Substances 0.000 claims abstract description 11
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 239000011733 molybdenum Substances 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- -1 silicide compound Chemical class 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 230000008018 melting Effects 0.000 claims 1
- 238000002844 melting Methods 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- 229910052721 tungsten Inorganic materials 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 6
- 230000007423 decrease Effects 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 230000009977 dual effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、絶縁性基板上にシリコン結晶を成長させて、
そのシリコンを用いてＭＯＳトランジスタを形成する半
導体装置に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to growing silicon crystals on an insulating substrate,
The present invention relates to a semiconductor device in which a MOS transistor is formed using the silicon.
高周波増幅用トランジスタとして、ＭＯＳＦＥＴは、伝
達特性が２乗特性に近いため、指数関数特性をもつバイ
ポーラトランジスタよりも優れた混変調特性を持ってい
る。ＭＯＳＦＥＴの高周波回路への応用は、ＦＭチュー
ナやＴＶチューナに広まっている。と（にＴＶチューナ
フロントエンド用には利得制御端子を設けたデュアルゲ
ート型ＭＯ３ＦＥＴが用いられている。このチューナ用
ＭＯ３ＦＥＴには高周波領域、特ＫＶＨＦ、Ｕ ＨＦ帯
において高利得、低雑音の特性が要求される。As a transistor for high frequency amplification, a MOSFET has a transfer characteristic close to a square-law characteristic, and thus has cross-modulation characteristics superior to a bipolar transistor having an exponential characteristic. The application of MOSFETs to high frequency circuits is widespread in FM tuners and TV tuners. A dual-gate MO3FET with a gain control terminal is used for the TV tuner front end.This tuner MO3FET has high gain and low noise characteristics in the high frequency region, especially in the KVHF and UHF bands. required.
第６図は従来の高周波用シングルゲート型ＭＯ８ＦＥＴ
の電極パターンの一例を示す平面図である。１８はゲー
ト電極、２０はソース電極、２２はドレイン電極である
。ゲート電極１８が１本の蛇行パターンの電極で形成さ
れている。第７図は従来の高周波用デュアルゲート型Ｍ
Ｏ８ＦＥＴの電極パターンの一例を示す平面図である。Figure 6 shows a conventional high-frequency single-gate MO8FET.
FIG. 3 is a plan view showing an example of an electrode pattern. 18 is a gate electrode, 20 is a source electrode, and 22 is a drain electrode. The gate electrode 18 is formed of a single meandering pattern electrode. Figure 7 shows the conventional dual gate type M for high frequency.
FIG. 3 is a plan view showing an example of an electrode pattern of an O8FET.
６０は第１ゲート、６２は第２ゲート、２０．２２は第
６図の同一の番号と同一の物である。第６図と同様に第
１ゲート６０、第２ゲート６２ともに１本の蛇行パター
ンの電極で形成されている。したがってＭＯＳＦＥＴの
入力インピーダンスの抵抗成分と容量成分は、ともに大
きく雑音指数の低い高性能ＦＥＴの製作は困難であった
。60 is the first gate, 62 is the second gate, and 20.22 are the same numbers as in FIG. As in FIG. 6, both the first gate 60 and the second gate 62 are formed of one meandering pattern electrode. Therefore, both the resistance component and the capacitance component of the input impedance of the MOSFET are large, making it difficult to manufacture a high-performance FET with a low noise figure.
現在、高周波用のＭＯＳＦＥＴは、さらに高周波化、低
雑音化が進められている。特にフロントエンド用として
の重要な特性項目に雑音指数がある。高周波ＭＯ３ＦＥ
Ｔの雑音は、そのほとんどが熱雑音であることが知られ
ており、いくつかの等価回路モデルおよび計算式が報告
されている。Currently, high-frequency MOSFETs are being developed to have even higher frequencies and lower noise. In particular, an important characteristic item for front-end applications is the noise figure. High frequency MO3FE
It is known that most of the noise in T is thermal noise, and several equivalent circuit models and calculation formulas have been reported.
Ｆ、 Ｍ、 Ｋｌａｕｓｓｅｎらによって理論計算され
たＭＯＳＦＥＴの高周波雑音は次式のように整理されて
いる。The high-frequency noise of MOSFET, which was theoretically calculated by F., M., Klaussen et al., is organized as follows.
Ｒｌｎ−Ｃ１ｎ” −−（１）
Ｆｍｉｎ ： 雑音指数
Ｒｉｎ ： 入力インピーダンスの抵抗成分Ｃｉｎ
： 入力インピーダンスの容量成分ｇｍ ：
）ランスコンダクタンスα ： 定数
ここでＲｉｎは次のように近似される。Rln-C1n” --(1) Fmin: Noise figure Rin: Resistance component Cin of input impedance
: Capacitance component gm of input impedance :
) Rance conductance α: constant Here, Rin is approximated as follows.
α
ＲｉｎキＲｇ＋Ｒｃ ＝Ｒｇ＋Ｒｓ ＋ −ｇｍ
Ｒｇ： ゲート直列抵抗
Ｒｃ： ソース直列抵抗（Ｒｓ）とチャネル抵抗（α
／ｇｍ）の和
またＣｉｎは次のような成分になる。α Rin + Rc = Rg + Rs + -gm Rg: Gate series resistance Rc: Source series resistance (Rs) and channel resistance (α
/gm) or Cin has the following components.
Ｃｉｎ ＝ Ｃｇｃ ＋ Ｃｃ
Ｃｇｃ ：ゲートとチャネル間容量
Ｃｃ：ゲート配線容量
（１）式よりＭＯＳＦＥＴの高周波領域における雑音指
数Ｆｍ１ｎを低減するためには、トランスコンダクタン
スｇｍを大きくし、入力インピーダンスの抵抗成分のゲ
ート直列抵抗Ｒｇとソース直列抵抗Ｒｓ、入力インピー
ダンスの容量成分のゲートとチャネル間容量Ｃｇｃとゲ
ート配線容量Ｃｃを小さくすればよい。Cin = Cgc + Cc Cgc: Capacitance between gate and channel Cc: Gate wiring capacitance From formula (1), in order to reduce the noise figure Fm1n in the high frequency region of MOSFET, the transconductance gm is increased and the resistance component of the input impedance is It is sufficient to reduce the gate series resistance Rg, the source series resistance Rs, the gate-to-channel capacitance Cgc as a capacitive component of the input impedance, and the gate wiring capacitance Cc.
これらのパラメータの改善を実際のＭＯＳＦＥＴの加工
技術、プロセス技術におきかえてみる。まずソースシリ
ーズ抵抗Ｒｓは主に結晶中の拡散領域で生じるシリーズ
抵抗であるので、Ｒｓを小さくするためにはソースコン
タクトとチャネル端間の距離を小さくする。これは微細
パターン化にすることにより解決できる。ゲートとチャ
ネル間容量Ｃｇｃはゲート電極面積に比例するのでゲー
ト電極の面積は小さくしなければならない。またトラン
スコンダクタンスｇｍは主にＭＯＳＦＥＴの能動領域上
のゲート電極の幅Ｗと長さＬの比Ｗ／Ｌ１７ｍ比例する
ので、その幅Ｗをできるだけ太き（する。Let's try to translate the improvement of these parameters into actual MOSFET processing technology and process technology. First, the source series resistance Rs is a series resistance mainly generated in the diffusion region in the crystal, so in order to reduce Rs, the distance between the source contact and the channel end is reduced. This can be solved by fine patterning. Since the capacitance Cgc between the gate and the channel is proportional to the area of the gate electrode, the area of the gate electrode must be made small. Further, since the transconductance gm is mainly proportional to the ratio W/L17m of the width W and length L of the gate electrode on the active region of the MOSFET, the width W is made as thick as possible.
したがってＣｇｃとｇｍからゲート電極の形状は幅Ｗを
大きく面積を小さくするために、必然的に長さＬを小さ
くすることになる。Therefore, in view of Cgc and gm, in order to increase the width W and reduce the area of the gate electrode, the length L must necessarily be decreased.
このような幅と長さの制約のもとで、重要なパラメータ
のゲート直列抵抗Ｒｇの低減は極めて困難である。従来
、この種のＭＯＳＦＥＴは単位面積当たりのより高いト
ランスコンダクタンスｇｍの達成のために、ゲート電極
のパターンとして、１本のゲートによる蛇行パターンが
用いられていた。Under such width and length constraints, it is extremely difficult to reduce the gate series resistance Rg, which is an important parameter. Conventionally, in this type of MOSFET, a meandering pattern with a single gate has been used as a gate electrode pattern in order to achieve a higher transconductance gm per unit area.
しかしながら１本のゲートによる蛇行パターンは、ゲー
ト直列抵抗Ｒｇの増大を招き、雑音指数の低減は著しく
困難であった。本発明の目的はこのような問題点を解決
するための半導体装置を提供するものである。However, the meandering pattern created by one gate increases the gate series resistance Rg, making it extremely difficult to reduce the noise figure. An object of the present invention is to provide a semiconductor device for solving these problems.
上記問題点を解決するため本発明は、絶縁性基板とこの
絶縁性基板上に設けられた半導体層を備えた半導体装置
において、上記の半導体層を用いて形成されたＭＯＳＦ
ＥＴのゲート電極をくし歯状電極とし、各（し歯状電極
を結ぶ引き出し配線部を半導体層外の絶縁基板上、ある
いは絶縁膜を介して形成し、ゲート電極の抵抗成分と容
量成分を低減し、該ＭＯ８ＦＥＴの高性能化、低雑音化
を行うものである。In order to solve the above problems, the present invention provides a semiconductor device including an insulating substrate and a semiconductor layer provided on the insulating substrate, in which a MOSFET formed using the above semiconductor layer is provided.
The gate electrode of ET is a comb-shaped electrode, and the lead-out wiring part connecting each comb-shaped electrode is formed on an insulating substrate outside the semiconductor layer or via an insulating film to reduce the resistance and capacitance components of the gate electrode. The purpose is to improve the performance and reduce noise of the MO8FET.
ＳＯＳ構造の半導体装置の特徴としては配線と基板間の
容量が小さいこと、またＭＯＳＦＥＴを形成する場合で
も、ソースやドレインと基板間の容量が小さく、バルク
シリコン上にＭＯＳＦＥＴを形成する場合に比して高速
化、低消費電力化が可能である。また、サファイア単結
晶基板が非常に高い絶縁性を持って（ごろこと、誘電率
や機械的強度が周波数、温度に対して安定であること、
高誘電率かつ低誘電体損失を示すこと、高熱伝導率を有
すること、化学的に不活性で高耐触性を持つこと、これ
らの特徴はモノソシックＩＣのみならず高密度混成ＩＣ
用の基板としても有利である。A feature of a semiconductor device with an SOS structure is that the capacitance between the wiring and the substrate is small, and even when forming a MOSFET, the capacitance between the source or drain and the substrate is small, compared to when a MOSFET is formed on bulk silicon. This makes it possible to increase speed and reduce power consumption. In addition, the sapphire single crystal substrate has extremely high insulating properties, and its dielectric constant and mechanical strength are stable over frequency and temperature.
High dielectric constant and low dielectric loss, high thermal conductivity, chemical inertness and high corrosion resistance.These characteristics are not only suitable for monolithic ICs but also for high-density hybrid ICs.
It is also advantageous as a substrate for use.
本発明では同一の絶縁性基板上、たとえばＳＯＳ構造上
にＭＯＳＦＥＴを形成し、そのゲート電極は、ゲート直
列抵抗が等節約に並列接続で小さくなる（し歯状の構造
とする。すなわちＭＯＳＦＥＴの能動領域を細か（分割
して１ユニツトあたりのゲート幅を短くした多数のゲー
ト電極を、半導体層外の絶縁性基板上に、あるいは絶縁
性基板上の絶縁膜上に引き出し、結線し並列接続とする
構造としたものである。In the present invention, MOSFETs are formed on the same insulating substrate, for example, on an SOS structure, and the gate electrode has a gate series resistance that is reduced by parallel connection in an equally economical manner (a tooth-shaped structure, that is, the active A large number of gate electrodes are divided into small regions (divided to shorten the gate width per unit) and are drawn out onto an insulating substrate outside the semiconductor layer or onto an insulating film on an insulating substrate, and connected in parallel. It is a structure.
以下、本発明の実施例を図面に基づいて詳述する。 Hereinafter, embodiments of the present invention will be described in detail based on the drawings.
第１図は本発明における実施例を示すくし歯状ゲート電
極を有するＭＯＳＦＥＴの平面図である。FIG. 1 is a plan view of a MOSFET having a comb-shaped gate electrode showing an embodiment of the present invention.
１０はＭＯＳＦＥＴの半導体能動領域、１２は（し歯状
ゲート電極、１４はゲート引き出し配線部、１６は絶縁
性基板、あるいは絶縁性基板上の絶縁膜、１８はゲート
電極、２０はソース電極、２２はドレイン電極である。10 is a semiconductor active region of the MOSFET, 12 is a tooth-shaped gate electrode, 14 is a gate lead-out wiring part, 16 is an insulating substrate or an insulating film on an insulating substrate, 18 is a gate electrode, 20 is a source electrode, 22 is the drain electrode.
第２図は第１図の線Ａ −Ａ′に沿ったＭＯＳＦＥＴの
断面図を示す。２４はゲート酸化膜である。また第１図
で示した物と同一の物には同一の番号を付しである。FIG. 2 shows a cross-sectional view of the MOSFET along line A-A' of FIG. 24 is a gate oxide film. Components that are the same as those shown in FIG. 1 are given the same numbers.
第１図のような構成においてソース、ドレインをゲート
電極をマスクとして形成する自己整合法、すなわちセル
ファライン法を用いることによりドレイン、ゲート間に
生ずる寄生容量がミラー効果により高周波特性を損うこ
とを防止することができるっセルファライン法ではＭＯ
ＳＦＥＴの能動領域上のくし歯状ゲート電極は耐熱性の
ゲート材料、たとえば多結晶シリコン、あるいはモリプ
デン、タングステン、あるいは、モリプデンシリサイド
などのシリサイド化合物が必要であるが、一般にこれら
の耐熱ゲート材料は耐熱性のないアルミニウムに比して
シート抵抗が一ケタ以上大きい。In the configuration shown in Figure 1, by using the self-alignment method, that is, the self-line method, in which the source and drain are formed using the gate electrode as a mask, it is possible to prevent parasitic capacitance generated between the drain and gate from impairing high-frequency characteristics due to the mirror effect. MO can be prevented with the Selfa Line method.
The comb-like gate electrode on the active region of the SFET requires a refractory gate material, such as polycrystalline silicon or a silicide compound such as molybdenum, tungsten, or molybdenum silicide, which are generally The sheet resistance is more than an order of magnitude higher than that of aluminum, which has no heat resistance.
しかしＭＯＳＦＥＴの能動領域外、すなわち絶縁性基板
上、あるいは絶縁性基板上の絶縁膜上のゲート引き出し
配線部１４は耐熱性のゲート材料を用いなくてもよいの
で、シート抵抗の極めて低い材料、たとえばアルミニウ
ムを用いることができる。このような構成の場合、ゲー
トのくし歯状ゲート電極数が増加してもゲート引き出し
配線部の抵抗成分の増加はほとんど増加しない。このよ
うにゲートに異種材料を組み合わせる構成とした場合は
、一般にシート抵抗の高い耐熱ゲート材料のみでＭＯＳ
ＦＥＴの能動領域上の部分と引き出し配線部を形成した
場合に比してゲート直列抵抗を著しく低減でき、雑音指
数の低減に効果が大きい。However, since it is not necessary to use a heat-resistant gate material for the gate lead-out wiring section 14 outside the active area of the MOSFET, that is, on the insulating substrate or on the insulating film on the insulating substrate, it is not necessary to use a heat-resistant gate material. Aluminum can be used. In such a configuration, even if the number of comb-shaped gate electrodes of the gate increases, the resistance component of the gate lead-out wiring portion hardly increases. When using a structure in which different types of gate materials are combined in this way, it is generally possible to create a MOS using only a heat-resistant gate material with high sheet resistance.
The gate series resistance can be significantly reduced compared to the case where a lead-out wiring section is formed with a portion above the active region of the FET, which is highly effective in reducing the noise figure.
第３図は本発明の他の実施例で、２つの絶縁ゲートをも
つくし歯状ゲート電極を有するデュアルゲート型ＭＯ８
ＦＥＴを示す平面図である。６０は第１ゲート、６２は
第２ゲート、４０はアイランドである。第４図は第３図
の線Ｂ −Ｂ’に沿ったデュアルゲート型ＭＯ８ＦＥＴ
の断面図を示す。FIG. 3 shows another embodiment of the present invention, a dual-gate MO8 having two insulated gates and a toothed gate electrode.
FIG. 2 is a plan view showing an FET. 60 is a first gate, 62 is a second gate, and 40 is an island. Figure 4 shows a dual gate MO8FET along line B-B' in Figure 3.
A cross-sectional view is shown.
第３図、第４図とも、第１図、第２図と同一の物には同
一の番号を付しである。デュアルゲート構造にしてその
第２ゲートを交流的に接地することにより、ドレインを
第１ゲート間の帰還容量は著しく小さくなり高周波特性
が著しく安定になる。In both FIGS. 3 and 4, the same parts as in FIGS. 1 and 2 are given the same numbers. By forming a dual gate structure and grounding the second gate in an alternating current manner, the feedback capacitance between the drain and the first gate is significantly reduced, and the high frequency characteristics are significantly stabilized.
このようなゲート電極構造はバルクシリコン上に同様な
ＭＯＳＦＥＴでも有効である。しかしながら、バルクシ
リコン上でゲートのくし歯状ゲート電極１２の数を増加
させることは、当然のことながら、ゲート引き出し配線
部１４の増加を伴う。Such a gate electrode structure is also effective in a similar MOSFET on bulk silicon. However, increasing the number of comb-shaped gate electrodes 12 on the bulk silicon naturally involves an increase in the number of gate lead-out wiring portions 14.
すなわち入力インピーダンスの抵抗成分が減少しても、
入力インピーダンスの容量成分の増加を引き起こし、雑
音指数の増加を招（ためゲートのくし歯状電極数の多大
な増加は望めない。本発明によれば、ゲートの（し歯状
電極数を増加させてもゲート引き出し配線部の増加によ
る入力インピーダンスの容量成分の増加は、絶縁性基板
１６を用いているがゆえにバルクシリコン上の場合に比
してはるかに少ない。In other words, even if the resistance component of the input impedance decreases,
This causes an increase in the capacitance component of the input impedance, leading to an increase in the noise figure. Therefore, it is not possible to expect a significant increase in the number of comb-shaped electrodes on the gate. However, since the insulating substrate 16 is used, the increase in the capacitance component of the input impedance due to the increase in the gate lead-out wiring portion is much smaller than that in the case of using bulk silicon.
この様子を第５図に示す。第５図において横軸はゲート
のくし歯状電極数、縦軸はＦＥＴの入力インピーダンス
の抵抗成分と入力インピーダンスの容量成分をとって示
す。曲線Ａは本発明の、絶縁性基板１６上に、あるいは
絶縁膜を介してゲート引き出し配線部を形成した場合、
曲線Ｃはバルクシリコン上にゲート引き出し配線部を形
成した場合の、それぞれの場合の入力インピーダンスの
容量成分の変化を示す。曲線Ｃは、本発明の場合の絶縁
性基板１６上に、あるいは絶縁膜を介してゲート引き出
し配線部１４を形成した場合の入力インピーダンスの抵
抗成分の変化を示す。抵抗成分の変化に関しては、バル
クシリコン上にゲート引き出し配線部１４を形成した場
合でも同様の変化を示す。This situation is shown in FIG. In FIG. 5, the horizontal axis represents the number of comb-like electrodes of the gate, and the vertical axis represents the resistance component of the input impedance and the capacitance component of the input impedance of the FET. Curve A represents the case where the gate lead-out wiring portion is formed on the insulating substrate 16 or via an insulating film according to the present invention.
Curve C shows the change in the capacitance component of the input impedance in each case when a gate lead-out wiring portion is formed on bulk silicon. Curve C shows a change in the resistance component of the input impedance when the gate lead wiring section 14 is formed on the insulating substrate 16 or via an insulating film in the case of the present invention. Regarding the change in the resistance component, a similar change occurs even when the gate lead wiring section 14 is formed on bulk silicon.
以上の説明で明らかなように、本発明によればゲートの
（し歯状電極数を増加させてもゲート引き出し配線部の
増加による入力インピーダンスの容量成分の増加は、絶
縁性基板を用いるがゆえにバルクシリコン上の場合に比
してはるかに少ない。As is clear from the above explanation, according to the present invention, even if the number of gate electrodes is increased, the increase in the capacitance component of the input impedance due to the increase in the number of gate lead-out wiring parts is due to the use of an insulating substrate. much less than on bulk silicon.
よってゲート電極の等制約な並列接続化を押し進めるこ
とができ、ＭＯＳＦＥＴの入力インピーダンスの抵抗成
分を著しく小さくすることができる。Therefore, parallel connection of gate electrodes with equal restrictions can be promoted, and the resistance component of the input impedance of the MOSFET can be significantly reduced.
さらにセルファライン法によりＭＯＳＦＥＴを形成する
場合に、半導体層上のくし歯状ゲート電極にシート抵抗
の高い耐熱性のゲート材料を用いた場合でも、ゲート引
き出し配線部をシート抵抗の低い、たとえばアルミニウ
ムなどによって形成することにより、一段とＭＯＳＦＥ
Ｔの入力インピーダンスの抵抗成分を小さくすることが
でき、Ｍ ＯＳ Ｆ Ｅ Ｔの高性能化、低雑音化に効
果が顕著である。Furthermore, when forming a MOSFET by the self-line method, even if a heat-resistant gate material with high sheet resistance is used for the comb-like gate electrode on the semiconductor layer, the gate lead-out wiring portion may be made of a material with low sheet resistance, such as aluminum. By forming the MOSFE
It is possible to reduce the resistance component of the input impedance of the T, which has a significant effect on improving the performance and reducing noise of the MOS FET.
なお以上の説明はガリウムヒ素基板上に形成した接合形
電界効果トランジスタの半導体装置でも同様の効果が得
られるのはいうまでもない。It goes without saying that the same effects as described above can be obtained in a semiconductor device of a junction field effect transistor formed on a gallium arsenide substrate.
第１図は本発明の実施例を示すくし歯状ゲート電極を有
するＭＯＳＦＥＴの平面図、第２図は第１図のＡ −Ａ
’線断面図、第３図は本発明の他の実施例を示すくし歯
状ゲート電極を有するプーアルゲート型ＭＯ８ＦＥＴの
平面図、第４図は第３図のＢ−Ｂ’線断面図、第５図は
本発明の実施例におけるＭＯＳＦＥＴのゲートのくし歯
状電極数と入力インピーダンスの抵抗成分と容量成分の
関係を示すグラフであり、第６図は従来の高周波用シン
グルゲート型ＭＯＳ Ｆ ＥＴの電極パターンの平面図
、第７図は従来の高周波用デュアルゲート型ＭＯ８ＦＥ
Ｔの電極パターンを示す平面図である。
１０・・・・・・半導体能動領域、
１２・・・・・・くし歯状ゲート電極、１４・・・・・
・ゲート引き出し配線部、１６・・・・・・絶縁性基板
、
６０・・・・・・第１ゲート、
３２・・・・・・第２ゲート。
第１図
第２図FIG. 1 is a plan view of a MOSFET having a comb-shaped gate electrode showing an embodiment of the present invention, and FIG. 2 is an A-A in FIG.
3 is a plan view of a Puar gate type MO8FET having a comb-shaped gate electrode showing another embodiment of the present invention. FIG. 4 is a sectional view taken along line BB' of FIG. FIG. 5 is a graph showing the relationship between the number of comb-like electrodes on the gate of the MOSFET and the resistance and capacitance components of the input impedance in the embodiment of the present invention, and FIG. A plan view of the electrode pattern, Figure 7 is a conventional dual gate MO8FE for high frequency use.
FIG. 3 is a plan view showing an electrode pattern of T. 10... Semiconductor active region, 12... Comb tooth-shaped gate electrode, 14...
- Gate lead-out wiring section, 16... insulating substrate, 60... first gate, 32... second gate. Figure 1 Figure 2
Claims (7)
層とから、ＭＯＳトランジスタを構成し、該ＭＯＳトラ
ンジスタのゲート電極をくし歯状電極とすることを特徴
とする半導体装置。(1) A semiconductor device characterized in that a MOS transistor is formed from an insulating substrate and a semiconductor layer provided on the insulating substrate, and a gate electrode of the MOS transistor is a comb-shaped electrode.
板上に設けたことを特徴とする特許請求の範囲第１項記
載の半導体装置。(2) The semiconductor device according to claim 1, wherein the comb-shaped electrode has a wiring portion provided on an insulating substrate.
したことを特徴とする特許請求の範囲第１項記載の半導
体装置。(3) The semiconductor device according to claim 1, wherein the comb-like electrodes are formed on the semiconductor layer with an insulating film interposed therebetween.
であることを特徴とする特許請求の範囲第１項記載の半
導体装置。(4) The semiconductor device according to claim 1, wherein the MOS transistor is a transistor with an SOS structure.
からなりそれぞれ異なる材料で構成したことを特徴とす
る特許請求の範囲第１項記載の半導体装置。(5) The semiconductor device according to claim 1, wherein the comb-shaped electrode is composed of a gate electrode portion and a lead-out wiring portion, each of which is made of different materials.
デン、あるいはタングステンなどの高融点金属、あるい
はシリサイド化合物であることを特徴とする特許請求の
範囲第５項記載の半導体装置。(6) The semiconductor device according to claim 5, wherein the gate electrode portion is made of polycrystalline silicon, a high melting point metal such as molybdenum, tungsten, or a silicide compound.
とする特許請求の範囲第５項記載の半導体装置。(7) The semiconductor device according to claim 5, wherein the lead wiring portion is made of aluminum.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27462185A JPS62134971A (en) | 1985-12-06 | 1985-12-06 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27462185A JPS62134971A (en) | 1985-12-06 | 1985-12-06 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62134971A true JPS62134971A (en) | 1987-06-18 |
Family
ID=17544274
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27462185A Pending JPS62134971A (en) | 1985-12-06 | 1985-12-06 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62134971A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH054521U (en) * | 1991-06-26 | 1993-01-22 | 三洋電機株式会社 | Insulated gate type field effect transistor |
-
1985
- 1985-12-06 JP JP27462185A patent/JPS62134971A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH054521U (en) * | 1991-06-26 | 1993-01-22 | 三洋電機株式会社 | Insulated gate type field effect transistor |
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