GB2070331A - Vertical MOSFET with a shield electrode - Google Patents
Vertical MOSFET with a shield electrode Download PDFInfo
- Publication number
- GB2070331A GB2070331A GB8104365A GB8104365A GB2070331A GB 2070331 A GB2070331 A GB 2070331A GB 8104365 A GB8104365 A GB 8104365A GB 8104365 A GB8104365 A GB 8104365A GB 2070331 A GB2070331 A GB 2070331A
- Authority
- GB
- United Kingdom
- Prior art keywords
- source
- drain
- drain region
- regions
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 210000000746 body region Anatomy 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 10
- 238000001894 space-charge-limited current method Methods 0.000 abstract description 5
- 239000002800 charge carrier Substances 0.000 description 3
- 230000005686 electrostatic field Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000001154 acute effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Microelectronics & Electronic Packaging (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A vertical MOSFET e.g a VDMOS device 50 includes source and gate electrodes 32, 52 on a major semiconductor surface, and a drain electrode 30 on an opposing semiconductor surface. A shield electrode 56 is disposed in proximity to the gate electrode 52 so as to minimize feedback capacitance between the gate electrode and drain region 24,26. Additionally, the shield electrode 56 increases the level of space charge limited current that can be supported in the drain region, and minimizes current crowding in the device. <IMAGE>
Description
SPECIFICATION
Vertical mosfet with a shield electrode
The present invention relates generally to insulated gate field effect transistors (IGFETS) such as metal oxide semiconductor FETS (MOSFETS). More particularly, it relates to vertical MOSFETS such as vertical, double diffused (VDMOS) devices.
A conventional IGFET is a unipolartransistor in which current flows from a source region, through a channel in a body region, into a drain region. The source, channel and drain regions are of N or Ptype conductivity, and the body region is of opposite conductivity type. The channel is induced (in an enhancement type device) or removed (in a depletion type device) by means of an electrostatic field produced by charges on a nearby gate electrode. The gate electrode typically lies between source and drain electrodes (disposed respectively on the source and drain regions), and in a MOSFET device it is insulated from the semiconductor surface of an oxide layer.
In vertical MOSFETS the source and drain electrodes are on opposite semiconductor surfaces and create a current flow which is substantially vertical (perpendicular to the semiconductor surfaces) through the device.
In VDMOS devices the gate electrode is typically on the same semiconductor surface as the source electrode, a configuration which provides a component of horizontal current flow (through the channel under the gate) as well. However, the transition from horizontal to vertical current flow produces current crowding, an effect which impedes device performance by reducing the maximum achievable voltage gain.
Additionally, in conventional VDMOS structures the gate typically overlaps that portion of the drain region adjacent to the channel, producing a capacitance CGD. When multiplied by the device gain
this capacitance is referred to as Miller-feedback capacitance, and it impairs device operation at high speeds and voltages.
To provide higher frequency and higher voltage operation, the present invention introduces a structure which reduces both Miller-feedback capacitance and current crowding in vertical MOSFET devices.
A shield electrode is disposed so as to reduce the capacitance between the drain region and gate, and minimize the current crowding, in a vertical MOSFET device. The shield is disposed in proximity to the gate electrode and it overlies that portion of the drain region which is adjacent to the channel portion of the device.
In the drawings:
Figure 1 is a sectional view of a prior art VDMOS device.
Figure2 is a sectional view of a VDMOS device embodying the present invention.
Referring to Figure 1, a conventional VDMOS device.10 includes a substantially planar substrate 12 having first and second opposing surfaces (14 and 16 respectively), and adjacent source, body and drain regions (18, 20 and 22 respectively) of alternate conductivity type. The drain region 22 typically comprises a relatively high conductivity portion 24 adjacent to the second surface 16 and an extended drain portion 26 of lower conductivity material extending to the first surface 14. In a typical configuration, a pair of body regions 20.
spaced apart by the extended drain region 26, extends into the substrate from the first surface 14 and forms a pair of body/drain PN junctions 23. A corresponding pair of source regions 18 extends into the substrate from the first surface 14 within the boundaries of the body regions 20. The source regions are located with respect to the extended drain region therebetween so as to define a pair of channel portions 28 at the first surface of each body region 20.
A drain electrode 30 is disposed across the second surface 16 and contacts the relatively high conductivity portion of the drain region 24. On the first surface a source electrode 32 contacts each source region 18 and body region 20 in an area displaced from the channel portion 28. A gate 34 is disposed on the first surface over both the pair of channel portions 28 and the extended drain region 26 between the channel portions.
The gate 34 typically includes an oxide 36 on the substrate surface 14 and an electrode 38 over the oxide.
Referring now to Figure 2, a VDMOS device 50 embodying the present invention is illustrated. Internally, the semiconductor structure of device 50 is substantially similar to that described with reference to the prior art device 10. Accordingly, the same reference numerals have been used to designate similar semiconductor regions. Furthermore, the device 50 also includes a drain electrode 30 contacting the relatively high conductivity drain region 24 at the second surface 16, and a source electrode 32 contacting each source and body region (18and 22 respectively) on the first surface 14. A gate electrode 52 is disposed over each channel portion 28 and is insulated from the first surface by an oxide 54.
In the present invention an insulated shield electrode 56 is disposed over the first surface such that it overlies the portion of the extended drain region 26 adjacent to the channel portions 28. In the preferred configuration an edge of each gate electrode 58 directly overlies the bodyidrain junction 23 and the shield electrode 56 is in proximity to, but isolated from, that edge. The shield electrode 56 is insulated from the first surface 14 by the same oxide 54 used to insulate the gate electrodes 52, although it is not necessary that the shield and gate electrodes be disposed on a single continuous oxide layer.In a typical device 50, the channel length is on the order of 5 micrometers, the oxide 54 thickness is approximately 100 nanometers, and the spacing between the gate and shield electrodes is in the approximate range of 100 nanometers to 5 micrometers.
The device 50 can be fabricated utilizing techniques commonly known in the semiconductor industry. For example, a conventional VDMOS device manufacturing method is described in U. S. Patent 4,055,884,
Fabrication Of Power Field Effect Transistors And The Resulting Structures, issued November 1, 1977 to C. G.
Jambotkar. To obtain the structure of the present invention additionally requires the pattern generation and formation of a shield electrode 56 and it can be performed in much the same manner as the fabrication of a standard gate electrode.
It should be noted that the described VDMOS device 50, comprising a pair of body and source regions, represents a preferred embodiment of the present invention. A device incorporating a single body and source region would also be functional. Furthermore, although the drawings illustrate semiconductor regions of a particular conductivity type (an N channel device) an operational (P channel) device would result if all indicated conductivity types were reversed.
It should also be recognized that the VDMOS device 50 can be incorporated into a larger device. For example, the larger device can include a plurality of portions, each having a sectional view of the VDMOS device 50 illustrated in Figure 2. This plurality of devices might be in the form of an interdigitated grid or meandering gate structure, as is commonly known in the semiconductor art.
The vertical VDMOS device 50 is particularly suitable for high power, high frequency operation and it can be used in either an enhancement or depletion mode. For example, under a set of typical operating conditions for an N channel enhancement mode device, the source electrode 32 is grounded, the drain electrode 16 is at 400 volts and the gate electrode 52 oscillates from 0 to 30 volts at frequencies on the order of 100 MHz. The shield electrode 56 is maintained at a substantially constant positive bias, similar in magnitude, but typically larger than, the gate bias. In the present example, the shield electrode should be maintained in the 30 - 60 volt range.
Current flow 60 in the device is substantially vertical (i.e., perpendicular to the major surfaces 14 and 16) although it has a horizontal component as well. Charge carriers flow essentially horizontally from the source regions 18 through the channel portions 28 to the extended drain region 26, and then substantially vertically through the drain region 22 to the drain electrode 30.
The presence of the shield electrode 56 significantly improves the performance of device 50. As previously indicated, in the conventional device 10 the gate electrode 38 overlaps the extended drain region 26 on the first surface 14, creating undesirable Miller-feedback capacitance during device operation. In the device 50 of the present invention Miller-feedback capacitance is minimized because the gate electrodes 58 are essentially disposed only over the channel portions 28. Although the shield electrode 56 overlaps the extended drain 26, it is maintained at a constant voltage (rather then the typically oscillating voltage of the gate 34), so it does not contribute to the feedback capacitance.
Additionally, the shield electrode 56 minimizes current crowding and increases the level of space charge limited current that can be supported in the extended drain region 26. Current crowding, accompanied by an intensification of electric field, results during the transition from horizontal current flow (through the channels 28) to vertical current flow (through the extended drain region 26). It is most acute in the areas where the PN junctions 23 intercept the first surface 14. Space charge limited current in the extended drain 26 is a function of the number of majority charge carriers in the area.
During operation of the device 50, the presence of the shield electrode 56 over the extended drain 26 creates a constant electrostatic field at the surface 14 of the extended drain. This field attacts majority charge carriers to the area, increasing the conductivity and enhancing the space charge limited current at the surface 14 of the extended drain. The shield electrode reduces the current crowding in the extended drain to the extent that it provides an electrostatic field greater than that produced by the oscillating gate voltage.
The invention has thus been described with reference to vertical, VDMOS structures. However, the invention is not so limited. It should be recognized that a shield electrode can be used in vertical, V groove (VMOS) structures and planar MOS structures as well. In VMOS and planar MOS structures, the shield electrode will also overlie that portion of the extended drain region adjacent to the channel portion of the body region. It will again minimize Miller-feedback capacitance and current crowding, while increasing the level of space charge limited current in the drain region.
Claims (5)
1. A MOSFET device, comprising:
a semiconductor substrate having a surface;
spaced source and drain regions of a first conductivity type in said substrate at said surface:
a body region of a second conductivity type in said substrate and having a channel portion between said source and drain regions at said surface;
a gate electrode disposed over the channel portion;
a source electrode contacting the source and body regions;
a drain electrode contacting the drain region; and
a shield electrode disposed over the drain region so as to minimize feedback capacitance and current crowding.
2. A device as defined in Claim 1 comprising a VDMOS transistor wherein:
the substrate is substantially planar, having first and second opposing major surfaces;
the drain region is disposed across the second surface and includes an extended drain portion extending to the first surface;
the body region extends from the first surface and is bounded by the drain region; and
the source region extends from the first surface, within the boundaries of the body region.
3. A device as defined in Claim 2 further comprising:
a pair of body regions extending into the substrate from the first surface, the body regions being spaced apart by the extended drain region;
a pair of source regions, each extending into the substrate from the first surface within the boundaries of a body region;
a pair of channel portions, defined by the pair of source regions and the extended drain region therebetween;
a pair of gate electrodes disposed over the pair of channel portions; and
the shield electrode overlying the first surface.
4. A device as defined in Claim 3 further comprising:
an oxide layer underlying the gate and shield electrodes.
5. A MOSFET device substantially as described herein with reference to the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12371580A | 1980-02-22 | 1980-02-22 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2070331A true GB2070331A (en) | 1981-09-03 |
| GB2070331B GB2070331B (en) | 1984-05-23 |
Family
ID=22410424
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8104365A Expired GB2070331B (en) | 1980-02-22 | 1981-02-12 | Vertical mosfet with a shield electrode |
Country Status (8)
| Country | Link |
|---|---|
| JP (1) | JPS56131961A (en) |
| DE (1) | DE3105693A1 (en) |
| FR (1) | FR2476914B1 (en) |
| GB (1) | GB2070331B (en) |
| IT (1) | IT1135091B (en) |
| PL (1) | PL136606B1 (en) |
| SE (1) | SE456291B (en) |
| YU (1) | YU41520B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1855544B (en) * | 2005-04-25 | 2010-05-12 | 半导体元件工业有限责任公司 | Semicondcutor with mask electrode and method |
| SG165138A1 (en) * | 2000-07-12 | 2010-10-28 | Inst Of Microelectronics | A semiconductor device |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57141964A (en) * | 1981-02-26 | 1982-09-02 | Nippon Telegr & Teleph Corp <Ntt> | Insulated gate type field effect transistor |
| DE3210353A1 (en) * | 1982-03-20 | 1983-09-22 | Robert Bosch Gmbh, 7000 Stuttgart | MONOLITHICALLY INTEGRATED DARLINGTON CIRCUIT |
| EP0207178A1 (en) * | 1985-06-25 | 1987-01-07 | Eaton Corporation | Bidirectional power fet with field shaping |
| US4577208A (en) * | 1982-09-23 | 1986-03-18 | Eaton Corporation | Bidirectional power FET with integral avalanche protection |
| EP0205639A1 (en) * | 1985-06-25 | 1986-12-30 | Eaton Corporation | Bidirectional power fet with substrate referenced shield |
| DE3465225D1 (en) * | 1983-02-17 | 1987-09-10 | Nissan Motor | A vertical-type mosfet and method of fabricating the same |
| EP0205640A1 (en) * | 1985-06-25 | 1986-12-30 | Eaton Corporation | Lateral bidirectional shielded notch fet |
| CN100508211C (en) * | 2003-01-21 | 2009-07-01 | 西北大学 | Fast switching power insulated gate semiconductor device |
| CN102569385B (en) * | 2010-12-17 | 2015-04-08 | 上海华虹宏力半导体制造有限公司 | VDMOS (vertical double-diffused metal oxide semiconductor) structure provided with shielding grid and preparation method thereof |
| CN102569386B (en) * | 2010-12-17 | 2015-02-04 | 上海华虹宏力半导体制造有限公司 | VDMOS (vertical double-diffused metal oxide semiconductor) device with shield grid and preparation method of VDMOS device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1132810A (en) * | 1966-03-30 | 1968-11-06 | Matsushita Electronics Corp | Field-effect transistor having insulated gates |
| GB1316555A (en) * | 1969-08-12 | 1973-05-09 | ||
| US3845495A (en) * | 1971-09-23 | 1974-10-29 | Signetics Corp | High voltage, high frequency double diffused metal oxide semiconductor device |
| GB1423449A (en) * | 1973-07-27 | 1976-02-04 | Standard Telephones Cables Ltd | Semiconductor device |
| JPS52106688A (en) * | 1976-03-05 | 1977-09-07 | Nec Corp | Field-effect transistor |
-
1981
- 1981-01-13 SE SE8100148A patent/SE456291B/en not_active IP Right Cessation
- 1981-01-20 IT IT19216/81A patent/IT1135091B/en active
- 1981-02-12 GB GB8104365A patent/GB2070331B/en not_active Expired
- 1981-02-17 DE DE19813105693 patent/DE3105693A1/en active Granted
- 1981-02-18 JP JP2362181A patent/JPS56131961A/en active Granted
- 1981-02-19 YU YU424/81A patent/YU41520B/en unknown
- 1981-02-20 FR FR8103443A patent/FR2476914B1/en not_active Expired
- 1981-02-20 PL PL1981229786A patent/PL136606B1/en unknown
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SG165138A1 (en) * | 2000-07-12 | 2010-10-28 | Inst Of Microelectronics | A semiconductor device |
| CN1855544B (en) * | 2005-04-25 | 2010-05-12 | 半导体元件工业有限责任公司 | Semicondcutor with mask electrode and method |
Also Published As
| Publication number | Publication date |
|---|---|
| PL136606B1 (en) | 1986-03-31 |
| PL229786A1 (en) | 1981-09-18 |
| FR2476914B1 (en) | 1985-10-18 |
| YU41520B (en) | 1987-08-31 |
| JPS56131961A (en) | 1981-10-15 |
| SE8100148L (en) | 1981-08-23 |
| FR2476914A1 (en) | 1981-08-28 |
| DE3105693A1 (en) | 1981-11-26 |
| SE456291B (en) | 1988-09-19 |
| DE3105693C2 (en) | 1992-12-10 |
| GB2070331B (en) | 1984-05-23 |
| YU42481A (en) | 1983-06-30 |
| JPH0213830B2 (en) | 1990-04-05 |
| IT8119216A0 (en) | 1981-01-20 |
| IT1135091B (en) | 1986-08-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19970212 |