GB2089118A - Field-effect semiconductor device - Google Patents

Field-effect semiconductor device Download PDF

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GB2089118A
GB2089118A GB8039498A GB8039498A GB2089118A GB 2089118 A GB2089118 A GB 2089118A GB 8039498 A GB8039498 A GB 8039498A GB 8039498 A GB8039498 A GB 8039498A GB 2089118 A GB2089118 A GB 2089118A
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epitaxial layer
layer
groove
field
drain
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Philips Electronics UK Ltd
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Philips Electronic and Associated Industries Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/405—Resistive arrangements, e.g. resistive or semi-insulating field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

A field-effect device, for example an IGFET has a lateral configuration for its channel area which is formed in for example a region (14) of an epitaxial layer (12), between a source region (16) and a low-doped drain zone (11), whilst the drain zone (11) and an overlying resistance layer (35) extend in a vertical configuration over the side-walls of a groove (20) in the epitaxial layer to contact the underlying substrate (13) which forms the highly doped drain region of the device. The resistance layer (35) electrically connected between the substrate drain region (13) and gate (15) overlying the lateral channel area spreads the electrostatic field occurring in the drain zone (11) in a manner which can be balanced with the field in the bulk of the epitaxial layer so as to permit a high breakdown voltage with acceptable drain series resistance and economic use of the major surface area of the body (1). <IMAGE>

Description

SPECIFICATION Field-effect devices This invention relates to field-effect devices, particularly but not exclusively insulated-gate field-effect transistors (IGFETs) forming discrete power transistors.
Published U.K. Patent Specification (GB) 20111 78A (our reference PHB 32602) discloses a field-effect device comprising a semiconductor body having an epitaxial layer of one conductivity type on a lower resistivity semiconductor substrate; a device channel area is present in the epitaxial layer and extends parallel to the major surface of the epitaxial layer remote from the substrate; a drain region of the opposite conductivity type is present in the body; a lower-doped drain zone of said opposite conductivity type present in the epitaxial layer extends from the channel area to the drain region; a gate is situated over and separated from the channel area by a barrier layer to control by field-effect action across the barrier layer the passage of chargecarriers along a current path through said channel area to said drain zone; a resistance layer is electrically connected between the gate and the drain region and extends over the lower-doped drain zone to provide field-relief means serving to spread the electrostatic field which occurs in the drain zone and to reduce at the body surface the magnitude of said field at the edge of the drain zone adjacent the channel area.
The device disclosed in GB 20111 78A is an IGFET in which the semiconductor substrate is of the same conductivity type as the epitaxial layer, and the source region of which may be shorted to the epitaxial layer and to the substrate by the source electrode extending into a groove in the epitaxial layer. The drain region of this IGFET is present in the epitaxial layer at its major surface remote from the substrate. The lower-doped drain zone extends along this major surface of the epitaxial layer, from the channel area to the drain region. By providing the field-relief resistance layer over the drain zone at this major surface a high breakdown voltage can be obtained as described in detail in GB 2011178A, without an unacceptable increase in drain series resistance or unacceptable decrease in transconductance (gm).
Starting from the device structures disclosed in GB 2011 178A (the whole contents of which are hereby incorporated by reference into the present specification), the present invention provides further advantageous field-effect device structures as described hereinafter.
Thus according to the present invention there is provided a field-effect device comprising a semiconductor body having an epitaxial layer of one conductivity type on a lower resistivity semiconductor substrate, a device channel area being present in the epitaxial layer and extending parallel to the major surface of the epitaxial layer remote from the substrate, a drain region of the opposite conductivity type in the body, a drain zone of said opposite conductivity type present in the epitaxial layer, having a lower doping concentration than the drain region and extending from the channel area to the drain region, a gate situated over and separated from the channel area by a barrier layer to control by field-effect action across the barrier layer the passage of charge-carriers along a current path through said channel area to said drain zone, and a resistance layer which is electrically connected between the gate and the drain region and extends over the lower-doped drain zone to provide field-relief means serving to spread the electrostatic field which occurs in the drain zone and to reduce at the body surface the magnitude of said field at the edge of the drain zone adjacent the channel area, characterized in that the semiconductor substrate is of said opposite conductivity type and provides said drain region, in that the lower-doped drain zone extends from the major surface of the epitaxial layer to the substrate by adjoining the side-walls of a groove which extends through the epitaxial layer to the substrate, and in that the resistance layer extends over the side-walls of the groove and is electrically connected to the semiconductor substrate within the groove.
Such a device combines advantageously both a lateral configuration (for the channel area and gate) with a vertical configuration (for the drain zone and resistance layer). Thus, the channel area which will usually be required to have a short well-defined length extends parallel to the major surface of the epitaxial layer and will usually adjoin (or at least be in the vicinity of) this major surface where its length and that of the overlying gate can be easily determined in a reliable manner using known techniques.
However, the lower-doped drain zone and the resistance layer both of which will usually be required to be very much longer so as to achieve a high breakdown voltage extend along the side-walls of the groove down to the substrate drain region. In this manner there can be obtained a significant saving in major surface area of the semiconductor body for a given voltage handling capability. Furthermore by having both the lower-doped drain zone and the resistance layer at the side-walls of the groove, an advantageous spreading of the electrostatic field between the channel area and the substrate drain region can also be obtained, permitting a more advantageous combination of the voltage and current handling capabilities for the device.
Further features in accordance with the invention and their advantages will now be given in the following description of some embodiments of the present invention which are described, by way of example, with reference to the accompanying diagrammatic drawings, in which Figure 1 is a cross-sectional view of a portion of an insulated-gate field-effect transistor in accordance with the invention; Figure 2 is a cross-sectional view of part of the transistor portion of Figure 1 and indicating the electrostatic field distribution between the transistor channel area and drain region;; Figure 3 is a cross-sectional view of a corresponding part of an insulated-gate field-effect transistor disclosed in GB 2011178A and not in accordance with the present invention, and indicating the elec trostatic field distribution between the transistor channel area and drain region, and Figure 4 is a cross-sectional view of a portion of another insulated-gate field-effect transistor in accordance with the present invention.
It should be noted that each of the Figures is diagrammatic and not drawn to scale. The relative dimensions and proportions of some parts of these Figures have been shown exaggerated or reduced for the sake of clarity and convenience. The same reference numerals as used in the first embodiment are generally used to refer to corresponding or similar parts in the other embodiment and in the previously-disclosed transistor.
The IGFET of Figure 1 comprises a semiconductor body 1 having between opposite major surfaces 2 and 3 an epitaxial layer 12 of one conductivity type (p-type, in the example shown) on a lower resistivity semiconductor substrate 13. Both the epitaxial layer 12 and the substrate 13 may be of for example monocrystalline silicon.
A channel area of the transistor is provided in the epitaxial layer 12 by a more highly doped region 14 where the region 14 adjoins the major surface 2 of the epitaxial layer remote from the substrate 13. In the example shown in Figure 1 the IGFET is an n-channel enhancement mode transistor so that the region 14 is p-type. The channel area so formed extends parallel to the major surface 2.
The transistor has a drain zone 11 of the opposite conductivity type (n-type, in this example) which is present in the epitaxial layer 12 and extends from the channel area to a higher-doped drain region. As will be described hereinafter this drain region is formed by the substrate 13.
A transistor gate 15 is situated over the channel area and separated therefrom by a barrier layer in the form of a thin insulating layer 25. The gate 15 serves to control by field-effect action across the layer 25 the passage of electrons along a current path through said channel area, from a source region 16 to the drain zone 11.
A resistance layer 35 extends over the drain zone 11 to provide field-relief means in a manner similar to that disclosed in GB 2011178A. The layer 35 is directly electrically connected between the gate 15 and drain region to permit the formation of a potential distribution along the layer 35 between the gate 15 and drain region during the operation of the transistor. The layer 35 may be of high resistivity polycrystalline silicon of substantially homogeneous nature at least along the resistance path so that a substantially linear fall-off in potential can occur from the drain potential where the layer 35 is connected to the drain region to the gate potential where the layer 35 is connected to the gate 15.
The underlying drain zone 11 has a sufficiently low doping that this potential distribution capacitively coupled across the insulating layer 25 spreads the electrostatic field which occurs in the drain zone 11 as a result of a depletion layer formed at the reverse-biased drain junction. In this way the magnitude of the electrostatic field at the edge of the drain zone 11 adjacent the channel area is reduced. This is advantageous for obtaining a high breakdown voltage. Because the resistance layer 35 extends over the whole distance from the gate 15 to the drain region the potential distribution along this layer 35 can influence the whole length of the current path in the drain zone 11.
In accordance with the present invention, the semiconductor substrate 13 is of opposite conductivity type (i.e. n-type, in the example shown) to that of the epitaxial layer 12, and this opposite conductivity type substrate 13 provides the drain region of the transistor. The lower-doped drain zone 11 extends from the major surface 2 of the epitaxial layer 12 to the substrate 13 by adjoining the side-walls of a groove 20 which extends through the epitaxial layer 12 to the substrate 13. The resistance layer 35 extends over the side-walls of the groove 20 and is electrically connected to the semiconductor substrate 13 within the groove 20.
In the IGFET example shown in Figure 1, the thin insulating layer 25 also extends over the side-walls of the groove 20 and has a window at the bottom of the groove where the resistance layer 35 is connected to the substrate 13. When the layer 35 is of high resistivity polycrystalline silicon it may be locally doped with a high donor concentration both at this window so as to make direct contact to the drain region 13 and above the channel area so as to form the gate 15. Instead of this very compact arrangement, it is possible to use a separate layer as the gate and to provide the connections between the layer 35 and the gate and drain region 15 and 13 as metal layer connections.
Thus this device in accordance with the invention has a lateral configuration for the gate 15 and underlying channel area and a vertical configuration for the drain zone 11, resistance layer 35 and drain region 13.
The length of the channel area in Figure 1 is defined by the lateral spacing between the edge of the p-type region 14 and the adjacent edge of the n-type source region 16. This lateral spacing can be determined in known manner by diffusing both acceptors and donors through the same window in a diffusion masking layer on the surface 2 to form the p-type region 14 and the n-type source region 16. In this way a very short channel can be obtained in a readily reproducible manner in a manufacturing process. Preferably a central area of the diffusion mask window is itself masked against the donor diffusion so that as shown in Figure 1 the region 14 extends to the surface 2 between opposite parts of the region 16 and is short-circuited to the source region 16 by the source electrode 26, for example a metal layer, provided at a window in the insulating layer 25. The provision of the more highly-doped region 14 in the high resistivity epitaxial layer 12 also inhibits the drain depletion layer punching through the channel area to the source region 16.
Furthermore, as the gate 15 is present at the major surface 2 and extends parallel to the surface 2, its length can also be readily determined, for example by a window in a diffusion masking layer provided on the polycrystalline resistance layer 35.
As shown in Figure 1, the drain region formed by the substrate 13 is contacted at the opposite major surface 3 of the body 1 by a metal electrode layer 23.
By thus having the drain electrode 23 at the back surface 3, the electrode arrangement at the top surface 2 is simplified as it comprises only the source electrode 26 and the connection to the gate 15. Thus, the source electrode 26, the gate 15 and the groove 20 may form with each other an interdigitated structure so that the basic element structure shown between the two grooves 20 in Figure 1 is repeated across the width of the semiconductor body 1, only a part of which is shown in Figure 1.
In order to achieve a high drain breakdown voltage it is desirable to have a long drain zone 11 and a correspondingly long resistance layer 35. By using the groove 20 to obtain a vertical configuration for the zone 11 and layer 35 as in the Figure 1 device structure, the zone 11 and layer 35 can be long without requiring a correspondingly large area of the major surface 2. Thus in the IGFET of Figure 1, the groove 20 has a V-shaped cross-section and may be formed in the silicon epitaxial layer 12 by anisotropic etching in known manner, the major surface 2 having a < 100 > crystal orientation and the resulting side-walls of the groove 20 being < 111 > crystal planes.In this case the inclination of the side-walls to the surface 2 is an angle of about 55 (54.7 ), so that the ratio of the distance d required at the surface 2 to accommodate a drain zone 11 and resistance layer 35 of length B is approximately 0.6. Therefore the configuration of Figure 1 represents a 40% saving in major surface area required to accommodate the zone 11 and layer 35.
This 40% space saving is illustrated in Figures 2 and 3, where Figure 2 shows part of the IGFET structure of Figure 1, and Figure 3 shows a corresponding part of the IG FET structure disclosed in GB 20111 78A. In the structure of Figure 3 the substrate 33 is of the same conductivity type as the epitaxial layer 12, the drain region 34 is at the major surface 2 of the epitaxial layer 12 and both the drain zone 11 and resistance layer 35 extend along this same surface 2.Also in the previously disclosed structure of Figure 3 further major surface area is required to accommodate the lateral extension of the surfaceadjoining drain region 34 (most of which is not shown in Figure 3); this further area also is saved in the device structure of Figures 1 and 2, except for the small area required at the bottom of the groove 20 for the connection between the resistance layer 35 and the drain region substrate 13.
Figures 2 and 3 also illustrate the electrostatic field distribution which occurs in the depletion layer between the channel area and the drain region when a voltage close to the breakdown voltage is applied to the drain of each of the transistors. The broken lines 32 correspond to equi-potentials in the field. As can be seen by comparing Figures 2 and 3, the lines 32 in the Figure 2 structure are more uniformly spaced and less distorted (especially by the higher doped drain region), because in the Figure 2 structure the substantially linear potentials distribution along the side wall of the groove 20 is balanced by the substantially linear potential distribution in the p- bulk of the epitaxial layer 12 between the regions 13 and 14. Thus, an improved field distribution is also achieved with the Figure 2 structure in accordance with the present invention.
An IGFET having the structure of Figure 1 may be designed to operate with drain voltages of, for example, up to 1000 volts. By way of example for such an IGFET, the resistivities of the substrate 13 and epitaxial layer 12 may be 0.01 and 100 ohm.cm.
respectively; the thickness of the layer 12 and the depths of the groove 20, p-type region 14 and source region 16 may be 65,70,2, and 1 micrometres respectively; the doping concentrations of the regions 14 and 16 at the surface 20 may be 1017 and 1020 dopant atoms per cm3 respectively; the thicknesses of the low-doped drain zone 11, a silicon dioxide insulating layer 25 and a polycrystalline silicon resistance layer 35 may be 1,0.1, and 1 micrometres respectively. The drain zone 11 may be formed by implanting 2 x 1012 donor dopant ions/ cm2. A typical spacing between the apex of adjacent grooves 20 and a typical width of p-type region 14 is, for example, 130 and 25 micrometres respectively.
Preferably the resistance layer 35 should have a high resistance value along its length to reduce leakage currents, for example a resistance of at least 108 ohms per cm of its width (the width of the layer 35 in Figures 2 and 3 is its dimension perpendicular to the drawing sheet). Instead of undoped polycrystalline silicon a higher resistivity material such as oxygendoped polycrystalline silicon may be used, in which case the part of the insulating layer 25 which extends into the groove 20 to separate the resistance layer 35 from the drain zone 11 may be omitted without significantly increasing leakage currents between the transistor gate 15 and drain region 13.
Figure 4 illustrates a modification of the Figure 1 structure in which an even greater space saving is achieved by replacing the V-shaped groove 20 having its side-walls substantially perpendicular to the major surface 2. In this case the major surfaces 2 and 3 of the silicon epitaxial layer 12 and substrate 13 have a < 110 > crystal orientation so that the anisotropic etching forms < 111 > side-walls of the groove 40 perpendicular to the surface 2. The etching is stopped when the grooves reach the substrate 13. The p-type region 14 may be formed before this etching step by diffusing acceptor dopant over the whole surface 2 of the epitaxial layer 12.
After the etching step, a donor dopant diffusion may be effected to define the channel area and to form the drain zone 11. In this case the drain zone 11 overdopes the edge of the p-type region 14. The transistor channel area is defined by the gap between the drain zone 11 and a simultaneouslyformed n-type source extension zone 36 where the corresponding part of the surface 2 was masked against the diffusion.
The doping concentration and thickness of such a drain zone 11 adjoining such a perpendicular groove 40 are preferably chosen such that the negative space-charge occurring on depletion in each p-type layer part 12 between adjacent grooves 20 substantially balances the positive space-charge occurring in the pair of zones 11 adjoining that layer part 12. The resulting interleaved balanced positive and negative space charges between the drain region 13 and transistor channel area can result in an advantageous electrostatic field distribution because they appear to behave on a macroscopic scale as effectively intrinsic material. Such a device structure allows fabrication of an IG FET with very high voltage capability, while the series resistivity of the effectively intrinsice portion increases only in proportion to the designed breakdown voltage. This is described in our co-pending patent application 8039499 (our reference PHB 32740) entitled "High Voltage Semiconductor Devices" which is filed on the same day as the present patent application and the relevant contents of which are hereby incorporated into the present specification.
Although only n-channel enhancement mode IGFETs have been shown in Figures 1,2 and 4, the invention may also be used with p-channel devices and with depletion-mode devices. The devices may be Schottky-gate field-effect transistors in which the gate is separated from the channel area by a Schottky (metal-semiconductor) rectifying junction forming the barrier layer. The present invention is also applicable to field-effect devices other than transistors.

Claims (8)

1. Afield-effect device comprising a semiconductor body having an epitaxial layer of one conductivitytype on a lower resistivity semiconductor substrate, a device channel area being present in the epitaxial layer and extending parallel to the major surface of the epitaxial layer remote from the substrate, a drain region of the opposite conductivity type in the body, a drain zone of said opposite conductivity type present in the epitaxial layer, having a lower doping concentration than the drain region and extending from the channel area to the drain region, a gate situated over and separated from the channel area by a barrier layer to control by field-effect action across the barrier layer the passage of charge-carriers along a current path through said channel area to said lower-doped drain zone, and a resistance layer which is electrically connected between the gate and the drain region and extends overthe lower-doped drain zone to provide fieldrelief means serving to spread the electrostatic field which occurs in the drain zone and to reduce at the body surface the magnitude of said field at the edge of the drain zone adjacent the channel area, characterized in that the semiconductor substrate is of said opposite conductivity type and provides said drain region, in that the lower-doped drain zone extends from the major surface of the epitaxial layer to the substrate by adjoining the side-walls of a groove which extends through the epitaxial layer to the substrate, and in that the resistance layer extends over the side-walls of the groove and is electrically connected to the semiconductor substrate within the groove.
2. Afield-effect device as claimed in Claim 1, further characterized in that said groove has a V-shaped cross-section.
3. Afield-effect device as claimed in Claim 2, further characterized in that at least the epitaxial layer is of silicon having a major surface with a < 100 > crystal orientation, and in that the side-walls of the groove are < 111 > crystal planes.
4. A field-effect device as claimed in Claim 1, further characterized in that said groove has sidewalls substantially perpendicular to said major surface of the epitaxial layer.
5. Afield-effect device as claimed in Claim 4, further characterized in that at least the epitaxial layer is of silicon having a major surface with a < 110 > crystal orientation, and in that the side-walls of the groove are < 111 > crystal planes.
6. Afield-effect device as claimed in any of the preceding Claims, further characterized in that a part of the resistance layer contacts the substrate at the bottom of said groove to form the electrical connection to the drain region.
7. A field-effect device as claimed in any of the preceding Claims, further characterized in that the resistance layer extends on an insulating layer at the side-walls of the groove.
8. A field-effect transistor substantially as described with reference to Figure 1 or Figure 4 of the accompanying drawings.
GB8039498A 1980-12-10 1980-12-10 Field-effect semiconductor device Withdrawn GB2089118A (en)

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Cited By (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4541001A (en) * 1982-09-23 1985-09-10 Eaton Corporation Bidirectional power FET with substrate-referenced shield
US4716446A (en) * 1982-12-16 1987-12-29 U.S. Philips Corporation Insulated dual gate field effect transistor
US5430315A (en) * 1993-07-22 1995-07-04 Rumennik; Vladimir Bi-directional power trench MOS field effect transistor having low on-state resistance and low leakage current
EP0730302A2 (en) * 1995-02-28 1996-09-04 STMicroelectronics, Inc. Vertical switched-emitter structure with improved lateral isolation
US5554870A (en) * 1994-02-04 1996-09-10 Motorola, Inc. Integrated circuit having both vertical and horizontal devices and process for making the same
WO1997029518A1 (en) * 1996-02-05 1997-08-14 Siemens Aktiengesellschaft Field effect controlled semiconductor component
WO1997035346A1 (en) * 1996-03-20 1997-09-25 Siemens Aktiengesellschaft Field effect-controlled semiconductor component
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EP1073123A2 (en) * 1999-07-29 2001-01-31 Kabushiki Kaisha Toshiba High withstand voltage semiconductor device
WO2001059846A1 (en) 2000-02-12 2001-08-16 Koninklijke Philips Electronics N.V. Semiconductor device with voltage divider for increased reverse blocking voltage
US6337499B1 (en) 1997-11-03 2002-01-08 Infineon Technologies Ag Semiconductor component
EP1211734A1 (en) * 1999-07-02 2002-06-05 Kabushiki Kaisha Toyota Chuo Kenkyusho Vertical semiconductor device and method for producing the same
EP1261036A2 (en) * 2001-05-25 2002-11-27 Kabushiki Kaisha Toshiba Power MOSFET semiconductor device and method of manufacturing the same
JP2003046082A (en) * 2001-05-25 2003-02-14 Toshiba Corp Semiconductor device and method of manufacturing the same
EP1315213A2 (en) 2001-11-23 2003-05-28 Robert Bosch Gmbh MIS semiconductor devices having a trench gate electrode
US6630698B1 (en) 1998-09-02 2003-10-07 Infineon Ag High-voltage semiconductor component
US6674123B2 (en) * 1997-09-10 2004-01-06 Samsung Electronics Co., Ltd. MOS control diode and method for manufacturing the same
US6819089B2 (en) 2001-11-09 2004-11-16 Infineon Technologies Ag Power factor correction circuit with high-voltage semiconductor component
US6825514B2 (en) 2001-11-09 2004-11-30 Infineon Technologies Ag High-voltage semiconductor component
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US8110868B2 (en) 2005-07-27 2012-02-07 Infineon Technologies Austria Ag Power semiconductor component with a low on-state resistance
US8461648B2 (en) 2005-07-27 2013-06-11 Infineon Technologies Austria Ag Semiconductor component with a drift region and a drift control region

Cited By (42)

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US4541001A (en) * 1982-09-23 1985-09-10 Eaton Corporation Bidirectional power FET with substrate-referenced shield
US4716446A (en) * 1982-12-16 1987-12-29 U.S. Philips Corporation Insulated dual gate field effect transistor
US5430315A (en) * 1993-07-22 1995-07-04 Rumennik; Vladimir Bi-directional power trench MOS field effect transistor having low on-state resistance and low leakage current
US5554870A (en) * 1994-02-04 1996-09-10 Motorola, Inc. Integrated circuit having both vertical and horizontal devices and process for making the same
EP0730302A3 (en) * 1995-02-28 1999-10-13 STMicroelectronics, Inc. Vertical switched-emitter structure with improved lateral isolation
EP0730302A2 (en) * 1995-02-28 1996-09-04 STMicroelectronics, Inc. Vertical switched-emitter structure with improved lateral isolation
WO1997029518A1 (en) * 1996-02-05 1997-08-14 Siemens Aktiengesellschaft Field effect controlled semiconductor component
WO1997035346A1 (en) * 1996-03-20 1997-09-25 Siemens Aktiengesellschaft Field effect-controlled semiconductor component
US5973360A (en) * 1996-03-20 1999-10-26 Siemens Aktiengesellschaft Field effect-controllable semiconductor component
US6674123B2 (en) * 1997-09-10 2004-01-06 Samsung Electronics Co., Ltd. MOS control diode and method for manufacturing the same
WO1999023704A1 (en) * 1997-11-03 1999-05-14 Infineon Technologies Ag Semiconductor component
US6337499B1 (en) 1997-11-03 2002-01-08 Infineon Technologies Ag Semiconductor component
US6630698B1 (en) 1998-09-02 2003-10-07 Infineon Ag High-voltage semiconductor component
US6960798B2 (en) 1998-09-02 2005-11-01 Infineon Technologies Ag High-voltage semiconductor component
US6894329B2 (en) 1998-09-02 2005-05-17 Infineon Technologies Ag High-voltage semiconductor component
EP1211734A4 (en) * 1999-07-02 2004-07-21 Toyoda Chuo Kenkyusho Kk Vertical semiconductor device and method for producing the same
EP1211734A1 (en) * 1999-07-02 2002-06-05 Kabushiki Kaisha Toyota Chuo Kenkyusho Vertical semiconductor device and method for producing the same
EP1073123A2 (en) * 1999-07-29 2001-01-31 Kabushiki Kaisha Toshiba High withstand voltage semiconductor device
EP1073123A3 (en) * 1999-07-29 2001-05-23 Kabushiki Kaisha Toshiba High withstand voltage semiconductor device
US6353252B1 (en) 1999-07-29 2002-03-05 Kabushiki Kaisha Toshiba High breakdown voltage semiconductor device having trenched film connected to electrodes
EP1959501A3 (en) * 1999-12-09 2009-04-08 Hitachi, Ltd. Power semiconductor device
US6624472B2 (en) 2000-02-12 2003-09-23 Koninklijke Philips Electronics N.V. Semiconductor device with voltage sustaining zone
WO2001059846A1 (en) 2000-02-12 2001-08-16 Koninklijke Philips Electronics N.V. Semiconductor device with voltage divider for increased reverse blocking voltage
JP2003046082A (en) * 2001-05-25 2003-02-14 Toshiba Corp Semiconductor device and method of manufacturing the same
EP1261036A2 (en) * 2001-05-25 2002-11-27 Kabushiki Kaisha Toshiba Power MOSFET semiconductor device and method of manufacturing the same
EP1261036A3 (en) * 2001-05-25 2004-07-28 Kabushiki Kaisha Toshiba Power MOSFET semiconductor device and method of manufacturing the same
JP4559691B2 (en) * 2001-05-25 2010-10-13 株式会社東芝 Manufacturing method of semiconductor device
US7226841B2 (en) 2001-05-25 2007-06-05 Kabushiki Kaisha Toshiba Power MOSFET semiconductor device and method of manufacturing the same
US6819089B2 (en) 2001-11-09 2004-11-16 Infineon Technologies Ag Power factor correction circuit with high-voltage semiconductor component
US6825514B2 (en) 2001-11-09 2004-11-30 Infineon Technologies Ag High-voltage semiconductor component
US6828609B2 (en) 2001-11-09 2004-12-07 Infineon Technologies Ag High-voltage semiconductor component
EP1315213A2 (en) 2001-11-23 2003-05-28 Robert Bosch Gmbh MIS semiconductor devices having a trench gate electrode
EP1315213A3 (en) * 2001-11-23 2007-10-03 Robert Bosch Gmbh MIS semiconductor devices having a trench gate electrode
EP2261992A2 (en) 2005-07-27 2010-12-15 Infineon Technologies Austria AG Semiconductor component with a drift region and with a drift control region
WO2007012490A2 (en) 2005-07-27 2007-02-01 Infineon Technologies Austria Ag Semiconductor component with a drift region and with a drift control region
EP2267785A2 (en) 2005-07-27 2010-12-29 Infineon Technologies Austria AG Semiconductor component with a drift region and with a drift control region
US8110868B2 (en) 2005-07-27 2012-02-07 Infineon Technologies Austria Ag Power semiconductor component with a low on-state resistance
US8461648B2 (en) 2005-07-27 2013-06-11 Infineon Technologies Austria Ag Semiconductor component with a drift region and a drift control region
US8643086B2 (en) 2005-07-27 2014-02-04 Infineon Technologies Austria Ag Semiconductor component with high breakthrough tension and low forward resistance
US9190511B2 (en) 2005-07-27 2015-11-17 Infineon Technologies Austria Ag Semiconductor component with a drift region and a drift control region
DE102006009942A1 (en) * 2006-03-03 2007-09-06 Infineon Technologies Austria Ag Semiconductor component e.g. power transistor, has drift zone, and drift control zone made of semiconductor material and arranged adjacent to drift zone in body, where accumulation dielectric is arranged between zones
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