JPS6228593B2 - - Google Patents
Info
- Publication number
- JPS6228593B2 JPS6228593B2 JP54101454A JP10145479A JPS6228593B2 JP S6228593 B2 JPS6228593 B2 JP S6228593B2 JP 54101454 A JP54101454 A JP 54101454A JP 10145479 A JP10145479 A JP 10145479A JP S6228593 B2 JPS6228593 B2 JP S6228593B2
- Authority
- JP
- Japan
- Prior art keywords
- impurity concentration
- electrode
- gate
- gaas
- active layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 32
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 32
- 239000012535 impurity Substances 0.000 claims description 25
- 229910045601 alloy Inorganic materials 0.000 claims description 8
- 239000000956 alloy Substances 0.000 claims description 8
- 230000005669 field effect Effects 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000005275 alloying Methods 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】
本発明は砒化ガリウムシヨツトキバリア形電界
効果トランジスタに関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a gallium arsenide shot barrier type field effect transistor.
砒化ガリウム（GaAsと記す）を使用したシヨ
ツトキバリア型電界効果トランジスタ（MES
FETと記す）は、現在、ミリ波帯まで使用可能
な三端子半導体デバイスとして、マイクロ波通
信、レーダー等の分野において広く使用されてい
る。GaAs MES FETの雑音指数Ｆは次式で表わ
される。 Schottky barrier field effect transistor (MES) using gallium arsenide (abbreviated as GaAs)
FET) is currently widely used in fields such as microwave communications and radar as a three-terminal semiconductor device that can be used up to the millimeter wave band. The noise figure F of GaAs MES FET is expressed by the following formula.
Ｆ＝１＋２πKfCgsＲｇ＋Ｒｓ／Ｇｍ ……(1)
(1)式でＫは定数、ｆは使用周波数、Cgsはゲー
ト・ソース間容量、Rgはゲート抵抗、Rsはソー
ス直列抵抗、Gmは相互コンダクタンスを表わ
す。(1)式から明らかなように、小さな雑音指数を
実現するためには(1)Cgsを小さくする。(2)Gmを
大きくする。(3)Rgを小さくする。(4)Rsを小さく
することが必要である。 F=1+2πKfCgsRg+Rs/Gm... (1) In equation (1), K is a constant, f is the operating frequency, Cgs is the gate-source capacitance, Rg is the gate resistance, Rs is the source series resistance, and Gm is the mutual conductance. As is clear from equation (1), in order to achieve a small noise figure, (1) Cgs should be small. (2) Increase Gm. (3) Reduce Rg. (4) It is necessary to reduce Rs.
(1)、(2)のCgsを小さくし、Gmを大きくするた
めには、本質的にゲート長を短くする必要があ
る。現在、商品化されているGaAs MES FETの
中で最も短いゲート長は0.5ミクロンであり、さ
らに0.3〜0.25ミクロンの、いわゆるクオーター
ミクロンゲートの実現が計られている。しかし、
クオーターミクロンが実現できても、他のパラメ
ータRgとRsとが大きと雑音指数の低減は小幅に
とどまる。Rgの低減は、ゲート金属の厚さを厚
くすればよいが、ゲート長を短くするためにはゲ
ート長より厚い金属を使用することはできない。
そこで、単位のゲート幅の小さいゲートを多数並
列にし、実質的にRgの低減が計られている。一
方、Rsはゲートとソース間隔で決まる抵抗と、
ソースのオーム性電極とGaAsとの接触抵抗の和
と考えられる。従つて、Rsを低減するために
は、ゲートとソース間隔を短くすること、ゲート
とソース間のGaAs活性層の抵抗を下げること、
および、オーム性電極とGaAsとの接触抵抗を下
げることが必要である。 In order to reduce Cgs and increase Gm in (1) and (2), it is essentially necessary to shorten the gate length. Currently, the shortest gate length of commercially available GaAs MES FETs is 0.5 microns, and efforts are being made to realize so-called quarter-micron gates of 0.3 to 0.25 microns. but,
Even if a quarter micron size can be achieved, if the other parameters Rg and Rs are large, the reduction in noise figure will remain small. Rg can be reduced by increasing the thickness of the gate metal, but in order to shorten the gate length, it is not possible to use a metal that is thicker than the gate length.
Therefore, a large number of gates with a small unit gate width are arranged in parallel to substantially reduce Rg. On the other hand, Rs is the resistance determined by the distance between the gate and source,
This is thought to be the sum of the contact resistance between the source ohmic electrode and GaAs. Therefore, in order to reduce Rs, shorten the distance between the gate and source, lower the resistance of the GaAs active layer between the gate and source,
Additionally, it is necessary to reduce the contact resistance between the ohmic electrode and GaAs.
ゲート・ソース間隔を短くすることは、ゲート
電極とソース電極との位置合せの精度からその下
限は決まり、現在の技術では１ミクロンが限界で
ある。ゲート・ソース間のGaAs活性層の抵抗を
下げるためには、その活性層の不純物濃度を上
げ、その厚さを厚くすることが必要である。しか
し、活性層の不純物濃度を上げると、ゲート電極
の逆方向耐圧が低下し、逆方向リーク電流が増加
してかえつて雑音の発生を招く。また、活性層の
厚さを厚くするとFETのピンチオフ電圧が大き
くなり、ゲート電極下の空乏層が大きくなるため
に、実効的なゲート長が長くなり、雑音指数を大
きくする原因ともなる。従つて、低雑音増幅用
GaAs MES FETのピンチオフ電圧は１〜3Vに
設計され、ピンチオフ電圧と活性層の不純物濃度
から、活性層の厚さは限定される。一方、オーム
性電極とGaAsとの接触抵抗を下げるためには、
GaAs中の不純物濃度が高い方がよい。しかし、
その不純物濃度はゲート耐圧から上限が決められ
る。このように、GaAs MES FETの雑音指数の
低減については、理論的、製造技術的面からも多
くの問題が控えている。 The lower limit of reducing the gate-source distance is determined by the accuracy of alignment between the gate electrode and the source electrode, and with current technology, the limit is 1 micron. In order to lower the resistance of the GaAs active layer between the gate and source, it is necessary to increase the impurity concentration and thickness of the active layer. However, increasing the impurity concentration of the active layer lowers the reverse breakdown voltage of the gate electrode, increases reverse leakage current, and even causes noise. Furthermore, increasing the thickness of the active layer increases the pinch-off voltage of the FET and increases the depletion layer under the gate electrode, which increases the effective gate length and increases the noise figure. Therefore, for low noise amplification
The pinch-off voltage of GaAs MES FET is designed to be 1 to 3 V, and the thickness of the active layer is limited by the pinch-off voltage and the impurity concentration of the active layer. On the other hand, in order to lower the contact resistance between the ohmic electrode and GaAs,
The higher the impurity concentration in GaAs, the better. but,
The upper limit of the impurity concentration is determined by the gate breakdown voltage. As described above, there are many problems in reducing the noise figure of GaAs MES FETs, both theoretically and in terms of manufacturing technology.
本発明は、ゲート耐圧を低下せることなく、ソ
ースシリーズ抵抗を低減し、GaAs MES FETの
低雑音化を実現しようとするものである。 The present invention aims to reduce the source series resistance without lowering the gate withstand voltage, thereby achieving lower noise in GaAs MES FETs.
本発明では、ゲート耐圧はゲート電極が設けら
れたGaAs活性層の表面濃度によつてほとんど決
定され、一方、ソースおよびドレインのオーム性
電極とGaAsとの接触抵抗は、前記電極のアロイ
層とGaAs層との接触面におけるGaAs層の不純物
濃度によつて決まり、不純物濃度が高ければ高い
程、接触抵抗は低くなるので、ゲート耐圧に関係
する表面の不純物濃度を低くしておいて、接触抵
抗を低くする不純物濃度の高い位置をGaAs活性
層の深い位置に設けて、この深い位置において、
オーム性電極のアロイ層と接触させることにより
ゲート耐圧を低下させずにソースシリーズ抵抗を
低下させている。 In the present invention, the gate breakdown voltage is mostly determined by the surface concentration of the GaAs active layer provided with the gate electrode, while the contact resistance between the source and drain ohmic electrodes and GaAs is determined by the contact resistance between the alloy layer of the electrode and the GaAs active layer. It is determined by the impurity concentration of the GaAs layer at the contact surface with the GaAs layer, and the higher the impurity concentration, the lower the contact resistance. A position with a high impurity concentration to be lowered is provided deep in the GaAs active layer, and at this deep position,
By contacting the alloy layer of the ohmic electrode, the source series resistance is lowered without lowering the gate breakdown voltage.
つぎに図を用いて本発明を詳述する。第１図は
上述の本発明原理を適用するためのGaAs活性層
の表面の深さ方向に対す不純物濃度を示す曲線図
であり、表面濃度は1017cm-3で、最大値２×1018
cm-3、基板面で1018cm-3の山形の濃度分布を示
す。第２図は、本発明の第１の実施例であり、図
において、１はゲート電極であり、これを間に置
いてソース電極２とドレイン電極３がGaAs活性
層４の上に設けられ、ソース電極２、ドレイン電
極３によるアロイ層６の深さは、オーム性金属の
厚さ、アロイ時の温度、時間によつて決まり、従
つて、アロイ層６の深さを、第１図に示す不純物
濃度分布の最も不純物濃度の高い位置７の近傍領
域に届くように形成されている。なお、５は半絶
縁性のGaAs基板である。 Next, the present invention will be explained in detail using figures. FIG. 1 is a curve diagram showing the impurity concentration in the depth direction of the surface of the GaAs active layer for applying the above-mentioned principle of the present invention. The surface concentration is 10 17 cm -3 and the maximum value is 2×10 18
cm -3 , showing a mountain-shaped concentration distribution of 10 18 cm -3 on the substrate surface. FIG. 2 shows a first embodiment of the present invention. In the figure, 1 is a gate electrode, and with this gate electrode in between, a source electrode 2 and a drain electrode 3 are provided on a GaAs active layer 4. The depth of the alloy layer 6 formed by the source electrode 2 and drain electrode 3 is determined by the thickness of the ohmic metal, the temperature and time during alloying, and therefore the depth of the alloy layer 6 is shown in FIG. It is formed so as to reach the region near the position 7 where the impurity concentration is the highest in the impurity concentration distribution. Note that 5 is a semi-insulating GaAs substrate.
このように、上記第２図の例では、1017cm-3の
低い表面不純物濃度のため、ゲート１の耐圧は充
分保証され、かつ、内部の２×1018cm-3の高い不
純物濃度の位置でソース電極２のアロイ層６と
GaAs活性層の接触がなされて、低抵抗接触を実
現させ、よつて、低雑音化が得られている。 In this way, in the example shown in FIG. 2, the breakdown voltage of gate 1 is sufficiently guaranteed due to the low surface impurity concentration of 10 17 cm -3 , and the high impurity concentration of 2×10 18 cm -3 inside With the alloy layer 6 of the source electrode 2 at the position
A GaAs active layer contact is made to provide a low resistance contact and thus low noise.
第３図は、第１図の不純物濃度は全面にわたつ
ていたのに対し、オーム性電極の部分にだけ局部
的に形成された深さ方向の高不純物濃度分布を示
すもので、これは1017cm-3の全面にわたり一様な
不純物濃度分布３１を有するGaAs活性層に、ソ
ース電極とドレイン電極形成部に局部的に、例え
ばイオン注入法により活性層内部で最大値５×
1018cm-3の不純物濃度をもつように形成したもの
であり、第４図はこの不純物拡散領域８の、最大
値を示す７の深さ位置に届くようにソース電極２
とドレイン電極３のアロイ層６が形成されてい
る。 Figure 3 shows a high impurity concentration distribution in the depth direction that was locally formed only in the ohmic electrode area, whereas the impurity concentration in Figure 1 was over the entire surface. In a GaAs active layer having a uniform impurity concentration distribution 31 over the entire surface of 10 17 cm -3 , a maximum concentration of 5
The source electrode 2 is formed to have an impurity concentration of 10 18 cm -3 , and in FIG.
and an alloy layer 6 of the drain electrode 3 are formed.
この第２の実施例では、第２図の例に比べ、局
部的に、深さ方向で山形の不純物濃度分布を形成
する面倒さはあるが、ゲート電極１を形成する場
所の表面不純物濃度に何らの影響なしに独立にソ
ース電極の低抵抗接触が可能となる効果がある。 In this second embodiment, compared to the example shown in FIG. 2, although there is the trouble of locally forming a mountain-shaped impurity concentration distribution in the depth direction, This has the effect of making it possible to independently connect the source electrode with low resistance without any influence.
上述のとおり、本発明によるGaAs MES FET
は、ソース抵抗が小さくなつているので高効率
で、かつ、ゲート耐圧も高く、低雑音で高出力を
得ることができる。なお、上例では、ソース電極
とドレイン電極ともに、低接触抵抗化が計られて
いるが、ソース電極だけに適用されることがあり
得るのはいうまでもない。 As mentioned above, the GaAs MES FET according to the present invention
Since the source resistance is small, it is highly efficient and has a high gate breakdown voltage, so it is possible to obtain high output with low noise. In the above example, the contact resistance is reduced for both the source electrode and the drain electrode, but it goes without saying that this may be applied only to the source electrode.
第１図は、本発明が適用されるGaAs活性層の
深さ方向の不純物濃度の曲線図、第２図は本発明
の第１の実施例の断面図、第３図は、オーム性電
極形成部に局部的に形成された山形の不純物濃度
分布を示す曲線図、第４図は第３図に対応する本
発明の第２の実施例の断面図である。
１……ゲート電極、２……ソース電極、３……
ドレイン電極、４……GaAs活性層、５……半絶
縁性GaAs基板、６……オーム性電極アロイ層、
７……不純物濃度最大値深さ位置、８……高濃度
不純物拡散領域。
FIG. 1 is a curve diagram of impurity concentration in the depth direction of a GaAs active layer to which the present invention is applied, FIG. 2 is a cross-sectional view of the first embodiment of the present invention, and FIG. 3 is a diagram showing the formation of an ohmic electrode. FIG. 4 is a sectional view of a second embodiment of the present invention corresponding to FIG. 3. 1... Gate electrode, 2... Source electrode, 3...
Drain electrode, 4... GaAs active layer, 5... Semi-insulating GaAs substrate, 6... Ohmic electrode alloy layer,
7... Maximum impurity concentration depth position, 8... High concentration impurity diffusion region.
Claims (1)
電極およびドレイン電極を有する電界効果トラン
ジスタにおいて、前記ゲート電極は前記砒化ガリ
ウム活性層の低不純物濃度表面に形成され、前記
ソース電極およびドレイン電極は前記砒化ガリウ
ム活性層の表面で低く内部で高くなつておりさら
に内部で低くなる山形の不純物濃度分布部分上に
形成されており、かつ少なくとも前記ソース電極
はそのアロイ層が前記山形の不純物濃度分布部分
のほぼ最高の不純物濃度となる位置で終端するよ
うに形成されていることを特徴とする電界効果ト
ランジスタ。1. In a field effect transistor having a gate electrode, a source electrode, and a drain electrode on the surface of the gallium arsenide active layer, the gate electrode is formed on the low impurity concentration surface of the gallium arsenide active layer, and the source electrode and the drain electrode are formed on the surface of the gallium arsenide active layer. The source electrode is formed on a mountain-shaped impurity concentration distribution portion that is low at the surface and high in the interior, and further lower in the interior, and at least the source electrode is formed so that its alloy layer is approximately at the highest level of the mountain-shaped impurity concentration distribution portion. A field effect transistor characterized in that it is formed so as to terminate at a position having an impurity concentration.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10145479A JPS5624979A (en) | 1979-08-08 | 1979-08-08 | Field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10145479A JPS5624979A (en) | 1979-08-08 | 1979-08-08 | Field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5624979A JPS5624979A (en) | 1981-03-10 |
| JPS6228593B2 true JPS6228593B2 (en) | 1987-06-22 |
Family
ID=14301132
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10145479A Granted JPS5624979A (en) | 1979-08-08 | 1979-08-08 | Field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5624979A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4494016A (en) * | 1982-07-26 | 1985-01-15 | Sperry Corporation | High performance MESFET transistor for VLSI implementation |
| JPS6085567A (en) * | 1983-10-17 | 1985-05-15 | Mitsubishi Electric Corp | Field-effect transistor |
| JPH0812867B2 (en) * | 1984-05-23 | 1996-02-07 | 日本電気株式会社 | Semiconductor device |
| JPS6476774A (en) * | 1987-09-18 | 1989-03-22 | Nec Corp | Semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5268379A (en) * | 1975-12-04 | 1977-06-07 | Fujitsu Ltd | Semiconductor device |
| JPS5348488A (en) * | 1976-10-14 | 1978-05-01 | Mitsubishi Electric Corp | Field effect transistor |
-
1979
- 1979-08-08 JP JP10145479A patent/JPS5624979A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5268379A (en) * | 1975-12-04 | 1977-06-07 | Fujitsu Ltd | Semiconductor device |
| JPS5348488A (en) * | 1976-10-14 | 1978-05-01 | Mitsubishi Electric Corp | Field effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5624979A (en) | 1981-03-10 |
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