JPH0715018A - Field-effect transistor - Google Patents

Abstract

PURPOSE:To reduce gate length by forming gate electrodes on the side surface of a protrusion of an uneven part formed on a main surface of a compound semiconductor substrate. CONSTITUTION:When bias voltages are so applied that a source electrode 3 is ground, a drain electrode 4, is of a positive potential, and a gate electrode 5 is of a negative potential, a drain current flows from the drain electrode 4 to the source electrode 3, and is controlled by a depletion layer 6 stretching from the gate electrode 5. Since a semiinsulative substrate does not exist in a drain current path, the current component toward the substrate side, as one of short channel effect, is completely controlled. Since the depletion layer 6 under the gate stretches from both side surfaces of a protrusion, a channel thickness can be designed to be large. Thereby the short channel effect can be remarkably reduced. Since the gate length is almost determined by the trench depth of the unnvenness, an FET having an extremely short gate whose length is 0.1mum or smaller can be easily manufactured only by controlling the etching depth.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to improvements in field effect transistors.

[0002]

2. Description of the Related Art A field effect transistor (hereinafter abbreviated as FET) using a compound semiconductor such as GaAs.
Is widely used as a key device of a microwave wireless communication system. The performance of FETs has been remarkably improved in recent years, and improvements are still being made aiming at higher frequency, lower noise, and higher output. There are some measures to improve the performance of the FET, but the most effective method is to shorten the gate length. As the gate length is shortened, the transfer conductance (gm) is increased and the gate capacitance (Cgs) is reduced. As a result, higher frequency and higher gain are achieved. The gate length of the FET that was put into practical use in the early days was usually 0.5 to 1 μm, but due to the progress of the electrode processing technology that makes full use of the electron beam exposure method, the FET with a gate length of 0.2 μm has recently been put into practical use. Has reached the end.

The "short channel effect" is a problem in improving the performance by shortening the gate length. As a problem of the FET according to the conventional example, the short channel effect will be described in detail with reference to FIG.

FIG. 4 is a diagram showing a cross-sectional structure of a GaAs FET according to a conventional example, in which 101 is a semi-insulating GaA.
s substrate, 102 is an n-type GaAs layer serving as a channel, 10
Reference numerals 3 and 104 denote source and drain electrodes which make ohmic contact with the n-type GaAs layer 102, and 105 denotes n-type GaA.
It is a gate electrode forming a Schottky junction with the s layer 102.
In the GaAs FET shown in FIG. 4, the electric current flowing from the drain electrode 104 to the source electrode 103
The operating principle is to control by the depletion layer formed in the n-type GaAs layer 102 by the voltage (electric field) applied to the.

In the GaAs FET shown in FIG. 4, when the gate length is shortened, the shape of the depletion layer under the gate is changed from a semi-elliptical shape 106 shown by a solid line to a semi-circular shape 106a shown by a broken line in the channel. The electric field component extending in the lateral direction (horizontal direction in the figure) from the gate end cannot be ignored as compared with the electric field component in the depth direction (downward direction in the figure) that controls the current. Therefore, the current in the channel cannot be effectively controlled by the gate electric field. Also, if the gate length is shortened,
The current component flowing on the substrate side under the channel becomes ignorable compared to the current component flowing in the channel, and in this case also, the gate current cannot be controlled by the gate electric field.

[0006]

The shape effect of the depletion layer under the gate and the current leakage effect to the substrate side, which are caused by the shortening of the gate length, are collectively called a short channel effect. When the short channel effect occurs, the channel current cannot be effectively controlled by the gate voltage (electric field).
The gm near the pinch-off decreases and the drain conductance (gd) increases. As a result, if the gate length is shortened, there is a problem that the gain is rather decreased and the noise figure (NF) is increased.

The conventional method for suppressing the short channel effect is to reduce the shape effect of the depletion layer by first reducing the gate length to make the n-type GaAs layer thin and highly concentrated. The second method is to insert a layer such as a p-type GaAs layer serving as a potential barrier at the interface between the substrate and the n-type GaAs layer in order to reduce the current flowing on the substrate side. However, in the first method, there is a problem that the ohmic contact resistance between the source and the drain increases and the breakdown voltage between the gate and the source decreases due to the thinning of the n-type GaAs layer with high concentration.
In the second method, the n-type is formed by inserting the p-type GaAs layer.
As a result of the formation of the pn junction with the type GaAs layer, there arises a problem that the stray capacitance increases.

As described in detail above, in the conventional FET shown in FIG. 4, the method of improving the performance by shortening the gate length is approaching the limit due to the short channel effect. Met.

The present invention has been made in consideration of the above circumstances. Even if the gate length is shortened to 0.2 μm or less, the short channel effect is suppressed, and higher frequency and higher gain are possible. It is an object of the present invention to provide a field effect transistor having a novel structure.

[0010]

A field-effect transistor according to the present invention comprises an uneven portion formed on one main surface of a compound semiconductor substrate, a convex upper surface and a concave lower surface of the uneven portion, or a convex upper surface. A first metal layer deposited on the other principal surface of the compound semiconductor substrate to form an ohmic contact with the compound semiconductor substrate, and a second metal layer deposited on the side surface of the convex portion to form a Schottky junction with the compound semiconductor substrate. And a layer. Further, the metal layer deposited on the upper surface of the convex portion is a drain electrode, the metal layer deposited on the bottom surface of the concave portion or the other main surface of the compound semiconductor substrate is a source electrode, and the metal layer deposited on the side surface of the convex portion. An embodiment is that the layer is a gate electrode.

[0011]

In the field effect transistor having the above structure,
By providing the gate electrode on the convex side surface of the uneven portion formed on the one main surface of the compound semiconductor substrate, the gate length can be shortened and the short channel effect caused by the shortened gate length can be suppressed. , High gain is possible.

[0012]

Embodiments Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of an FET showing a first embodiment of an FET according to the present invention, in which 1 is a semi-insulating G
aAs substrate, 2 is an n-type GaAs layer, 3 and 4 are source and drain electrodes, and 5 is a gate electrode. In the figure, the source and drain electrodes 3 and 4 form an ohmic junction with the n-type GaAs layer 2, and the gate electrode 5 forms a Schottky junction with the n-type GaAs layer 2.

In the FET shown in FIG. 1, the source electrode 3
When a bias is applied so that is the ground potential, the drain electrode 4 is a positive potential, and the gate electrode 5 is a negative potential, a drain current flows from the drain electrode flow 4 toward the source electrode 3 (indicated by an arrow in the figure). The current is controlled by the depletion layer 6 extending from the gate electrode 5. In the FET according to the present invention shown in FIG. 1, since the semi-insulating substrate does not exist in the drain current path, the current component to the substrate side, which is one cause of the short channel effect, is completely suppressed. Regarding the shape effect of the depletion layer, which is another cause of the short channel effect, in the FET according to the present invention, since the depletion layer under the gate extends from both sides of the convex portion, the channel thickness (shown by W in the figure). ) Can be designed thicker than the FET of the conventional structure, the short channel effect can be greatly reduced when compared under the condition that the drain currents are the same. Further, in the FET according to the present invention, the gate length (indicated by l in the figure) is determined by the depth of the groove having substantially irregularities, so that the gate length is 0.1 μm or less, which is extremely difficult to form in the FET having the conventional structure. An FET with an extremely short gate can be easily manufactured by only controlling the etching depth.

(Embodiment 2) A second embodiment of the present invention is shown in FIG.
Shown in. In FIG. 2, 10 is an n-type GaAs substrate, 13
Is a source electrode, 14 is a drain electrode, and 15 is a gate electrode. The FET shown in FIG. 2 has exactly the same bias voltage applying method and operating principle as the FET shown in FIG.
An n-type GaAs substrate is used instead of the semi-insulating GaAs substrate, and the source electrode 13 is replaced with the bottom surface of the recess to form GaAs
The difference is that it is placed on the back side of the substrate. FE having the structure shown in FIG.
At T, as described with reference to FIG. 1, the short channel effect is suppressed more than that of the conventional FET, but in addition to this, the back surface of the substrate becomes the ground electrode as it is, so that the via hole is formed. This eliminates the need to electrically connect the source electrode to the back surface of the substrate, and enables power FETs and MMICs.
This is a great advantage when manufacturing.

(Embodiment 3) FIG. 3 is a sectional view showing an FET according to a third embodiment of the present invention.

In FIG. 3, 21 is a semi-insulating GaAs substrate, 22 is an n ⁺ type GaAs layer, and 27 is undoped GaA.
s layer, 28 is n ⁺ type AlGaAs layer, 29 is n ⁺ type Ga
As layers, 23 and 24 are source and drain electrodes, 2
Reference numeral 5 represents a gate electrode. The operation principle of the third embodiment is the same as that of the first embodiment, so that the short channel effect is suppressed, of course, but in the third embodiment, the n-type GaAs layer 2 of the first embodiment is used. N ⁺ AlGaA instead of (Fig. 1)
The heterojunction interface between the s layer 28 and the undoped GaAs layer 27 is used as a current channel, and can be regarded as an improved type of a high electron mobility transistor (HEMT).
In the FET of FIG. 3, suppression of the short channel effect and HE
Due to the two effects of high electron mobility of MT, the operating frequency is dramatically improved as compared with the conventional FET.

In the first to third embodiments described above, the case where GaAs is used as the compound semiconductor substrate has been illustrated, but the present invention is not limited to this, and other compound semiconductors such as InP may be used. It can be widely applied when used.

[0019]

As described above, according to the present invention, it is possible to suppress the short channel effect, which is a problem with the shortening of the gate length, which is difficult to avoid in the FET having the conventional structure. And higher gain are possible.

[Brief description of drawings]

FIG. 1 is a cross-sectional view for explaining an FET according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing an FET according to a second embodiment of the present invention.

FIG. 3 is a sectional view showing an FET of Example 3 according to the present invention.

FIG. 4 is a cross-sectional view for explaining a conventional FET.

[Explanation of symbols]

1, 21, 101 Semi-insulating GaAs substrate 2, 102 n-type GaAs layer 3, 13, 23, 103 Source electrode 4, 14, 24, 104 Drain electrode 5, 15, 25, 105 Gate electrode 6, 106, 106a Depletion Layer 10 n-type GaAs substrate 22, 29 n ⁺ -type GaAs layer 27 undoped GaAs layer 28 n ⁺ -type AlGaAs layer

Claims (2)

[Claims] 1. An uneven portion formed on one main surface of a compound semiconductor substrate, a convex upper surface and a concave bottom surface of the uneven portion, or a convex upper surface and the other main surface of the compound semiconductor substrate, respectively. A field effect transistor comprising: a first metal layer that forms an ohmic contact with the compound semiconductor substrate; and a second metal layer that is deposited on the side surface of the convex portion and forms a Schottky junction with the compound semiconductor substrate. 2. The metal layer deposited on the upper surface of the convex portion is a drain electrode, the metal layer deposited on the bottom surface of the concave portion or the other main surface of the compound semiconductor substrate is a source electrode, and the metal layer deposited on the side surface of the convex portion. The field effect transistor according to claim 1, wherein the formed metal layer is a gate electrode.