JPS5882562A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5882562A JPS5882562A JP56180890A JP18089081A JPS5882562A JP S5882562 A JPS5882562 A JP S5882562A JP 56180890 A JP56180890 A JP 56180890A JP 18089081 A JP18089081 A JP 18089081A JP S5882562 A JPS5882562 A JP S5882562A
- Authority
- JP
- Japan
- Prior art keywords
- region
- diode
- conductivity type
- type
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 239000012535 impurity Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims description 5
- 230000003071 parasitic effect Effects 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 4
- 230000003321 amplification Effects 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 3
- 230000001133 acceleration Effects 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
- H01L27/0825—Combination of vertical direct transistors of the same conductivity type having different characteristics,(e.g. Darlington transistors)
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、いわゆるダーリントン接続回路装置２１’−
：
において第１段トランジスタのエミッタ・ベース間にダ
イオードを挿入した回路要素を単一半導体基板上に形成
した半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a so-called Darlington connection circuit device 21'-
The present invention relates to a semiconductor device in which a circuit element in which a diode is inserted between the emitter and base of a first stage transistor is formed on a single semiconductor substrate.
第１図は２個のトランジスタＴｒｊｌＴｒ２をダーリン
トン接続した従来装置の回路を示している。FIG. 1 shows a circuit of a conventional device in which two transistors TrjlTr2 are connected in a Darlington manner.
ベース端子Ｂは第１段トランジスタ’Ｉ’ｒｔのベース
電極と接続され、さらにこのトランジスタＴｒ、のエミ
ッタ電極が第２段トランジスタＴｒ２のベース電極と接
続されている。またエミッタ端子Ｘは後段トランジスタ
Ｔτ２のエミッタ電極と接続されるとともにコレクタ端
子Ｃは上記両トランジスタＴｒｊ＃Ｔｒ２のコレクタ電
極に接続されている。The base terminal B is connected to the base electrode of the first stage transistor 'I'rt, and the emitter electrode of this transistor Tr is further connected to the base electrode of the second stage transistor Tr2. Further, the emitter terminal X is connected to the emitter electrode of the subsequent transistor Tτ2, and the collector terminal C is connected to the collector electrodes of both the transistors Trj#Tr2.
なお、Ｒ１は第１段トランジスタＴｒｉのベース・エミ
、り間の抵抗、Ｒ２は第２段トランジスタＴｒ２の、ベ
ース・エミッタ間の抵抗、Ｄｌは第２段トランジスタＴ
ｒ２のエミッタ・コレクタ間のダイオードである。Note that R1 is the resistance between the base and emitter of the first stage transistor Tri, R2 is the resistance between the base and emitter of the second stage transistor Tr2, and Dl is the resistance between the base and emitter of the second stage transistor T.
This is a diode between the emitter and collector of r2.
第２図は上記ダーリントン接続回路をたとえばシリコン
ウェハー上に構成した場合の断面図である。第１段のト
ランジスタ”ｒｌはＮ層３．２層２、３１”−２
８層１からなるＮＰＮ ）ランジスタで、この８層３上
にはＴｒｉのエミッタ電極および’Ｉ’ｒ２のベース電
極となる内部配線９が、また２層２の上にはベース電極
８が形成されている。一方第２段トランジスタＴｒ２は
Ｈ層４．２層２、Ｈ層１からなシ、Ｎ層４の上にはエミ
ッタ電極１ｏが形成されている。また、抵抗Ｒ１は領域
６に、抵抗Ｒ２は領域６にそれぞれ形成され、ダイオー
ドＤ１は２層２．８層１よシ構成される領域７に形成さ
れる０また１１はコレクタ電極、１２は絶縁膜である。FIG. 2 is a sectional view of the Darlington connection circuit constructed on, for example, a silicon wafer. The first stage transistor ``rl'' is an NPN transistor consisting of 3 N layers, 2 layers 2, 31''-2 8 layers 1, and on these 8 layers 3 are the emitter electrode of Tri and the base electrode of 'I'r2. Further, on the two layers 2, a base electrode 8 is formed. On the other hand, the second stage transistor Tr2 includes an H layer 4, a second layer 2, an H layer 1, and an emitter electrode 1o formed on the N layer 4. Further, the resistor R1 is formed in the region 6, the resistor R2 is formed in the region 6, and the diode D1 is formed in the region 7 composed of two layers 2.8 layers 1.0 or 11 is a collector electrode, and 12 is an insulating electrode. It is a membrane.
このように構成された従来のダーリントン接続回路では
、スイッチング動作で、ＯＮからｏｙｙへの切）替え時
にベース・エミッタ間が逆ノ（イアスされると、Ｔｒｌ
はＯＦＦ状態となシ、Ｔｒｔのベース・エミッタ間には
電流が流れないため、Ｔｒ２のベース領域に蓄積された
キャリアの放出は抵抗Ｒ１を通じて、ベース電極へ徐々
に流出するだけであシ、抵抗Ｒ１が大きいときにはキャ
リアの放出速度は小であシ、蓄積されたキャリアは比較
的長時間ベース領域に残留する。その結果スイッチ、ン
グ速度が遅くなるという欠点がある。上記欠点を改善す
るために第３図に示すようにダイオードＤ２をＴｘｌ
のエミッタ・ベース間に挿入する方法が知られている。In the conventional Darlington connection circuit configured in this way, when the base and emitter are reversely connected (earthed) during switching operation (from ON to oyy), Trl
is in the OFF state, and no current flows between the base and emitter of Trt, so the carriers accumulated in the base region of Tr2 are released only gradually through the resistor R1 to the base electrode. When R1 is large, the carrier release rate is low and the accumulated carriers remain in the base region for a relatively long time. As a result, the switching speed becomes slow. In order to improve the above drawback, diode D2 is connected to Txl as shown in Figure 3.
There is a known method of inserting it between the emitter and base of.
しかし、このダイオードＤ２は他の回路要素のように単
一半導体基板内に一体的に作り込むことは寄生トランジ
スタが、形成されるという不都合をともなうので、その
形成がはなはだ困難なため、従来は外部接続によって回
路構成する必要があり、したがって、このような回路構
成になすことは同回路装置の製作上、量産性、信頼性の
面で、必ずしも十分とはいえない。However, if this diode D2 is integrated into a single semiconductor substrate like other circuit elements, this would result in the formation of a parasitic transistor. It is necessary to configure the circuit by making connections, and therefore, such a circuit configuration is not necessarily sufficient in terms of production, mass productivity, and reliability of the circuit device.
本発明は上記問題点を解消し、スイッチングの高速化お
よび高信頼性を有する多段結合形トランジスタ回路装置
を与えるもので、少なくとも２段結合トランジスタ回路
構成を有し、第１段トランジスタのエミッタ・ベース間
に、寄生トランジスタ作用をもたないようなダイオード
を単一半導体基板内に設けた半導体装置を提供するもの
である。The present invention solves the above-mentioned problems and provides a multi-stage coupled transistor circuit device having high switching speed and high reliability. The present invention provides a semiconductor device in which a diode that does not have a parasitic transistor effect is provided in a single semiconductor substrate between the two.
以下本発明を図面によシ詳細に説明する〇ので第４図ａ
は左右に第１段、第２段トランジスタを形成した半導体
装置の断面図、ｂはａのＸ−Ｘ断面の表面側から深さ方
向にみた不純物濃度分布グラフである。The present invention will be explained in detail below with reference to the drawings.
is a cross-sectional view of a semiconductor device in which first and second stage transistors are formed on the left and right sides, and b is an impurity concentration distribution graph viewed from the surface side of the XX cross section of a in the depth direction.
第４図ａにおいて、１はトランジスタ’Ｉ’ｒ＋および
Ｔｘ２の共通コレクタ領域となる翼型シリコン基体、２
はトランジスタ’Ｉ’ｒ＋およびＴｒ２の共通ベース領
域となるイ型拡散領域、３はトランジスタＴｒｉのエミ
ッタ領域となるＨ型拡散領域、４はトランジスタＴｒ２
のエミッタ領域となるに型拡散領域、６は抵抗Ｒ１を形
成する抵抗領域、６は抵抗Ｒ２を形成する抵抗領域、７
はダイオードＤ１ を形成するＰＮ接合部分、１３はト
ランジスタＴ、。In FIG. 4a, 1 is a wing-shaped silicon substrate serving as a common collector region of transistors 'I'r+ and Tx2, 2
3 is an A-type diffusion region which becomes a common base region of transistors 'I'r+ and Tr2, 3 is an H-type diffusion region which becomes an emitter region of transistor Tri, and 4 is a transistor Tr2.
6 is a resistor region forming a resistor R1, 6 is a resistor region forming a resistor R2, 7 is a type diffusion region which becomes an emitter region of
13 is a PN junction portion forming a diode D1, and 13 is a transistor T.
のベース領域中へ作り込まれダイオードＤ２のカソード
領域となるＨ型拡散領域、１４はＮ型拡散領域１３の中
へ作シ込まれ、Ｐ寅接合ダイオードＤ２のアノード領域
となるＰ型拡散領域、８はトランジスタ’Ｉ”ｒｔのベ
ースとダイオードＤ２のカソード領域とを相互接続する
ための内部配線を兼ね１−２
るベース電極、そして９はトランジスタＴｒｉのエミッ
タとダイオードＤ２のアノードおよびＴｒ２ のベース
間を相互接続するための内部配線である０なお、１ｏは
エミッタ電極、１１はコレクタ電極、１２は二酸化シリ
コン（Ｓｉ０２）等の絶縁膜である。An H-type diffusion region 14 is formed into the base region of the diode D2 and becomes the cathode region of the diode D2; a P-type diffusion region 14 is formed into the N-type diffusion region 13 and becomes the anode region of the P-junction diode D2; Reference numeral 8 denotes a base electrode 1-2 which also serves as an internal wiring for interconnecting the base of the transistor 'I'rt and the cathode region of the diode D2, and 9 a base electrode between the emitter of the transistor Tri, the anode of the diode D2, and the base of the diode D2. Note that 1o is an emitter electrode, 11 is a collector electrode, and 12 is an insulating film such as silicon dioxide (Si02).
第４図ａのアノード領域１４とカソード領域１３より形
成されるＰＭ接合をダイオードとして動作させるに際し
、領域１４、領域１３、領域２より構成されるいわゆる
ＰＮＰ寄生トランジスタ構造はこの寄生トランジスタの
電流増幅率を極めて小さくすれば、そのトランジスタ作
用が除去できる。When operating the PM junction formed by the anode region 14 and cathode region 13 in FIG. By making it extremely small, the transistor effect can be eliminated.
本発明は第４図すに示すように、領域１４の活性不純物
濃度を領域１３の活性不純物濃度より低く押えることに
よシ、上述のようなＰＩＰ寄生トランジスタ構造ではあ
っても、その電流増幅率を極めて小さくし、そのトラン
ジスタ作用を無視できるようになしたものである０
このような濃度分布は領域１３の拡散不純物表”ｒ’＋
−”
面濃度に対して、領域１４の不純物濃度を不純物蒸着時
において、若干高い程度に押えることによって得られる
。たとえば、領域１３の拡散不純物表面濃度が１．５ｘ
１ｏ／ｉ の場合、領域１４の不純物濃度を蒸着時に３
．０Ｘ１０／ｃｄにすることによシ拡散熱処理後におい
て、領域１４の不純物表面濃度は７．ＯＸ １ ｏ／ｃ
ｔｌｉになる。このような不純物拡散プロファイルを測
定したグラフが第４図すに相当する。As shown in FIG. 4, the present invention, by suppressing the active impurity concentration in the region 14 to be lower than the active impurity concentration in the region 13, allows the current amplification factor to be reduced even in the PIP parasitic transistor structure as described above. This concentration distribution is made extremely small so that its transistor effect can be ignored.
-" This can be obtained by suppressing the impurity concentration in region 14 to a slightly higher level than the surface concentration during impurity evaporation. For example, if the surface concentration of diffused impurity in region 13 is 1.5x
In the case of 1o/i, the impurity concentration of region 14 is reduced to 3 during deposition.
．． After the diffusion heat treatment, the impurity surface concentration of the region 14 is set to 0.times.10/cd. OX 1 o/c
It becomes tli. A graph obtained by measuring such an impurity diffusion profile corresponds to FIG.
このようにして形成されたＰＮＰ寄生トランジスタの電
流増幅率は極めて低く、したがってＰＮＰ寄生トランジ
スタの作用はほぼ完全に除去でき、アノード領域１４と
カソード領域１３から成るＰＭ接合はダイオードとして
動作することになる。The current amplification factor of the PNP parasitic transistor formed in this way is extremely low, so the effect of the PNP parasitic transistor can be almost completely eliminated, and the PM junction consisting of the anode region 14 and cathode region 13 operates as a diode. .
以上説明したところから明らかなように、本発明によれ
ば、従来のダーリントン接続回路素子の製造工程にダイ
オードＤ２領域を形成するだめの工程が追加されるだけ
で、外部接続によってダイオードを付加した従来回路構
成と同等のスイッチング速度を持ち、しかも信頼性の面
で非常に優れ８゜
た半導体装置を得ることができる。As is clear from the above explanation, according to the present invention, only the step of forming the diode D2 region is added to the conventional manufacturing process of the Darlington connection circuit element, and the conventional process of adding the diode by external connection is performed. It is possible to obtain a semiconductor device which has a switching speed equivalent to that of the circuit configuration and which is extremely reliable in terms of 8°.
また以上の説明ではＮＰＮ型ダーリントン接続回路装置
を例示したが、本発明はＰＮＰ型にも同様の構成原理が
適用し得ることは勿論である。Further, in the above description, an NPN type Darlington connection circuit device has been illustrated, but it goes without saying that the same principle of construction can be applied to a PNP type as well.
第１図は従来のダーリントン接続回路の等価回路図、第
２図は従来のダーリントン接続回路装置の断面図、第３
図はダイオードを挿入したダーリントン接続回路の等価
回路図、第４図ａは本発明の一実施例にかかるダーリン
トン接続回路装置の断面図、第４図すは本発明のダイオ
ード部の活性不純物濃度分布図である。
１・・・・・・コレクタ領域となる半導体基体、２・・
・・・・Ｐ型ベース領域、３．４・・・・・・Ｎ型エミ
ッタ領域、６．６・・・・・・抵抗領域、７・・・・・
・ダイオードＤ、を形成するＰＩ接合部分、８・・・・
・・ベース電極、９・・・・・・内部配線、１ｏ・・・
・・・エミッタ電極、１１・・・・・・コレクタ電極、
１２・・・・・・絶縁膜、１３・・・・・・ダイオード
Ｄ２のカソード領域、１４・・・・・・ダイオードＤ２
のアノード領域。
１１２図
第３＠ｃ
第４図
＃ノFig. 1 is an equivalent circuit diagram of a conventional Darlington connection circuit, Fig. 2 is a sectional view of a conventional Darlington connection circuit device, and Fig. 3 is an equivalent circuit diagram of a conventional Darlington connection circuit.
The figure is an equivalent circuit diagram of a Darlington connection circuit in which a diode is inserted, FIG. 4a is a sectional view of a Darlington connection circuit device according to an embodiment of the present invention, and FIG. It is a diagram. 1...Semiconductor base serving as collector region, 2...
...P type base region, 3.4...N type emitter region, 6.6...Resistance region, 7...
・PI junction part forming diode D, 8...
...Base electrode, 9...Internal wiring, 1o...
...Emitter electrode, 11...Collector electrode,
12... Insulating film, 13... Cathode region of diode D2, 14... Diode D2
anode area. 112 Figure 3@c Figure 4 #ノ
Claims (1)
領域中に前記−導電型の複数のエミッタ領域を設けてな
る多段結合トランジスタ構成の半導体装置であって、第
１段トランジスタのベース領域中に前記エミッタとは独
立の前記−導電型の領域を形成し、前記独立の一導電型
領域中に前記反対導電型の領域を形成して、前記反対導
電型領域を第１段トランジスタのエミッタ領域と電気的
に短絡し、かつ前記独立の一導電型領域を前記第１段ト
ランジスタのベース領域と電気的に短絡した構造を−な
し、かつ、前記独立の一導電型領域内に形成されるｐｎ
接合域の活性不純物濃度がその独立の一導電型領域の活
性不純物濃度より低く形成されたことを特徴とする半導
体装置。A semiconductor device having a multi-stage coupled transistor configuration in which a plurality of emitter regions of the - conductivity type are provided in a common base region of an opposite conductivity type provided on a semiconductor substrate of one conductivity type, wherein the base region of the first stage transistor is forming the - conductivity type region independent of the emitter, forming the opposite conductivity type region in the independent one conductivity type region, and forming the opposite conductivity type region into the emitter region of the first stage transistor. and a structure in which the independent one conductivity type region is electrically shorted to the base region of the first stage transistor, and the pn formed in the independent one conductivity type region
A semiconductor device characterized in that the active impurity concentration of the junction region is lower than the active impurity concentration of the independent one conductivity type region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56180890A JPS5882562A (en) | 1981-11-10 | 1981-11-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56180890A JPS5882562A (en) | 1981-11-10 | 1981-11-10 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5882562A true JPS5882562A (en) | 1983-05-18 |
| JPH0412031B2 JPH0412031B2 (en) | 1992-03-03 |
Family
ID=16091115
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56180890A Granted JPS5882562A (en) | 1981-11-10 | 1981-11-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5882562A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59110166A (en) * | 1982-12-15 | 1984-06-26 | Sansha Electric Mfg Co Ltd | Darlington transistor |
| US4811074A (en) * | 1984-09-27 | 1989-03-07 | Siemens Aktiengesellschaft | Darlington circuit comprising a field effect transistor and a bipolar output transistor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5140781A (en) * | 1974-08-02 | 1976-04-05 | Trw Inc | |
| JPS5658260A (en) * | 1979-10-16 | 1981-05-21 | Matsushita Electronics Corp | Darlington junction type transistor and production thereof |
-
1981
- 1981-11-10 JP JP56180890A patent/JPS5882562A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5140781A (en) * | 1974-08-02 | 1976-04-05 | Trw Inc | |
| JPS5658260A (en) * | 1979-10-16 | 1981-05-21 | Matsushita Electronics Corp | Darlington junction type transistor and production thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59110166A (en) * | 1982-12-15 | 1984-06-26 | Sansha Electric Mfg Co Ltd | Darlington transistor |
| JPH0236061B2 (en) * | 1982-12-15 | 1990-08-15 | Sansha Electric Mfg Co Ltd | |
| US4811074A (en) * | 1984-09-27 | 1989-03-07 | Siemens Aktiengesellschaft | Darlington circuit comprising a field effect transistor and a bipolar output transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0412031B2 (en) | 1992-03-03 |
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