JPH02278736A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a junction capacity between a buried collector and a substrate by forming the buried collector only of a region directly under a base region, and composing a collector extraction electrode of horizontal extraction electrode and vertical extraction electrode buried in an insulating film. CONSTITUTION:A N<+> type buried collector 2 is formed on a P-type semiconductor substrate 1, a N-type epitaxial layer 4A is formed thereon, and its lower layer forms an N<+> type epitaxial layer 4 by external diffusion of an impurity from the collector. These epitaxial layers are surrounded by a thick insulating film 3, a P<+> type graft base 7 and a P-type base 8 are formed on the layer 4A, an N<+> type emitter 9 is further formed to compose a vertical NPN transistor. A collector extraction electrode is composed of a horizontal extraction electrode 61 buried horizontally in the film 3 and connected at its end to the layer 4 and a vertical collector extraction electrode 62 for connecting it to an electrode wiring 10. Thus, a junction capacity between the collector and the substrate can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor devices, and particularly to the structure of a collector lead electrode of a vertical NPN transistor.

[Conventional technology]

Conventionally, the collector lead electrode of an NPN bipolar transistor has been formed by diffusing an N-type impurity such as phosphorus from the upper surface of an epitaxial layer so as to be directly connected to the N+ type buried collector region. The manufacturing method will be explained below with reference to FIG.

First, arsenic is selectively diffused onto the surface of the P-type semiconductor substrate 1,
An N" type buried collector 2 is formed. Next, an N type epitaxial layer is grown to a thickness of 1 μm. At this time, arsenic from the buried collector is diffused outward into this N type epitaxial layer.
N+ type epitaxial layer 4 is formed to a thickness of approximately 0.6 μm, and the remaining thickness is formed as N type epitaxial layer 4A.
becomes. Subsequently, an insulating film 3 for isolation between elements is selectively formed.

Next, the N+ type buried collector extraction electrode 6 is formed by ion implantation of phosphorous to be deeply diffused so as to be connected to the N+ type buried collector 2. Subsequently, after providing a surface protection insulating film 5, a P+ type graft base 7 is formed by selective boron ion implantation, and a P type base 8 is further formed by selective boron ion implantation.

Next, contact openings for the base, emitter, and collector are selectively provided in the surface protection insulating film 5. After this, arsenic ions are selectively implanted through the emitter contact opening, and N+
A mold emitter 9 is formed.

After this, electrode wiring 10 is formed.

In this way, according to the prior art, the N+ type buried collector 2 is connected to the N" type collector 6 from the bottom of the P+ type and P type base.
It was formed over the entire area, right under the .

[Problem to be solved by the invention]

In the structure of the collector lead-out electrode of the conventional semiconductor device described above, the buried collector needs to extend directly below the lead-out electrode, and therefore occupies a large area. For this reason, recent advances in miniaturization of other parts of bipolar transistors have left behind, and the junction capacitance between the collector substrates has hardly been reduced, which has become a major obstacle to further speeding up bipolar semiconductor devices. Ta.

Furthermore, in bipolar memory devices, the depletion layer between the collector substrates is the largest area for charge generation due to alpha ray irradiation, making it possible to achieve memory cells with a sufficiently small soft error rate (SER). The structure of the conventional collector lead-out electrode has been a major obstacle in achieving this goal.

In contrast to the conventional collector extraction electrode jf1 structure described above, the present invention is an epitaxial structure in which the collector extraction electrode is completely buried in the insulating film and the extraction opening is made N+ by outward diffusion from the N+ type buried collector. The difference is that it is provided so as to be connected to the layer portion from the horizontal direction. Therefore, in the structure of the present invention, the N+ type buried collector, which conventionally does not extend directly under the collector extraction electrode, does not have that part.
It will exist only directly under the base area.

[Means to solve the problem]

The semiconductor device of the present invention includes: an N2 type buried collector formed on a P type semiconductor substrate; an N type epitaxial layer surrounded by an insulating film and formed on the N+ type buried collector;
A vertical type including a P-type base formed on the N-type epitaxial layer, an N+-type emitter formed on the P-type base, and a collector lead-out electrode connected to an electrode wiring formed on the insulating film. A semiconductor device having an NPN transistor, wherein the collector lead electrode includes a horizontal lead electrode buried horizontally in the insulating film and whose end portion is connected to the N-type epitaxial layer, and the horizontal lead electrode and the electrode wiring. It consists of a vertical lead-out electrode that connects the

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of one embodiment of the present invention.

An N+ type buried collector 2 is formed on a P type semiconductor substrate 1. And on top of that is an N-type epitaxial layer 4A.
However, the underlying layer is N+ type epitaxial N4 due to the outward diffusion of impurities from the N+ type buried collector.
It consists of These epitaxial layers are surrounded by a thick insulating film 3, and a P" type graft base 7 and a P type base 8 are formed on the N type epitaxial layer 4A, and an N+ type emitter is formed above the P type base 8. 9 is formed to constitute a vertical NPN transistor.In particular, a horizontal lead electrode 61 is buried horizontally in the insulating film 3 and has an end connected to the N+ type epitaxial layer 4;
A collector lead-out electrode is constituted by the horizontal lead-out electrode 61 and the vertical collector 9 lead-out electrode 62 that connects the electrode wiring 10. The manufacturing method will be explained below with reference to FIG.

First, as shown in FIG. 2(a), a first oxide film 30 with a thickness of 4000 A is formed by thermal oxidation on the main surface of the P-type semiconductor substrate 1.
A first polysilicon film 61A having a thickness of 3000 Å is provided thereon. Thereafter, arsenic ions are implanted into this polysilicon film to give an arsenic concentration of approximately IQ 20 cm-3.

Next, as shown in FIG. 2(b), the first polysilicon film 61A is selectively etched, and then the second oxidation [3
1 is provided on the entire surface with a film thickness of 500OA.

Next, as shown in FIG. 2(c), vertical openings are formed in the three-layer film of the first oxide film 30, the first polysilicon film 61A, and the second oxide film 31 by anisotropic dry etching. A horizontal collector extraction electrode 61 is formed. Thereafter, arsenic ions are implanted to form an N+ type buried collector 2.

Next, as shown in FIG. 2(d), an N-type epitaxial layer is selectively formed in the opening. At this time, due to the outward diffusion of arsenic from the N+ type buried collector 2, the N+ type epitaxial layer is changed from the bottom to the N+ type to become an N+ type epitaxial layer 4, and an N type epitaxial layer 4A is formed on the remaining upper part.

Thereafter, an opening is selectively formed in the second oxide film 31 on the horizontal collector extraction electrode 61 made of the first polysilicon film, and then a second polysilicon film is grown and buried to form the vertical collector extraction electrode 61. form. Next, phosphorus ions are selectively implanted into this extraction electrode, and the impurity concentration is approximately 10.
2102O' N+ type.

Next, as shown in FIG. 2(e), a 3000A surface protection insulating film 5 is formed on the surface, and boron ions are selectively implanted through the insulating film 5 to form a P1 type graft base 7 and a P type base. form 8. Thereafter, contacts between the emitter and the collector are selectively opened, and arsenic ions are implanted to form an N+ type emitter 9.

Next, as shown in FIG. 2(f), contacts in the base are selectively opened.

As shown in FIG. 1, an aluminum-based electrode material film is sputtered and then selectively etched to form an electrode wiring 10.

According to this embodiment configured in this way, the N+ type buried collector 2 is short, extending only to the lower part of the base, and the N+ type collector extraction electrode is buried in the insulating film. The junction capacitance between the collector and the P-type semiconductor substrate is reduced.

Incidentally, in the above embodiment, the vertical collector extraction electrode 62
We have explained the case where it is formed with a polysilicon film, but
A metal film such as tungsten may be embedded using the CVD method. In this case, there is an advantage that collector pull-out resistance can be significantly reduced.

〔Effect of the invention〕

As explained above, in the present invention, the buried collector is formed only in the region immediately below the base region, and the collector lead electrode is composed of a horizontal lead electrode and a vertical lead electrode buried in an insulating film, so that the buried collector substrate Since the junction capacitance between the two can be significantly reduced, it is possible to realize a semiconductor device capable of ultra-high-speed operation. Furthermore, in bipolar memory devices, the depletion layer region between the buried collector substrates, which is the most sensitive area that causes soft errors due to alpha particle collisions, can be significantly reduced, significantly improving soft error resistance. It has the effect of being able to

[Brief explanation of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention, FIG. 2 is a sectional view of a semiconductor chip for explaining the manufacturing method of the embodiment of the invention, and FIG. 3 is a sectional view of a conventional example. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... N+ type buried collector, 3... Insulating film, 4... N+ type epitaxial layer,
4A...N-type epitaxial layer, 5...Surface protection insulating film, 6...N+ type collector extraction electrode, 7...P
+ type graft base, 8...P type base, 9...N
+ type emitter, 10... electrode wiring, 30... first oxide film, 31... second oxide film, 61... horizontal collector extraction electrode, 62... vertical collector extraction electrode.

Claims (1)

[Claims] An N^+ type buried collector formed on a P type semiconductor substrate, an N type epitaxial layer surrounded by an insulating film and formed on the N^+ type buried collector, and an N type epitaxial layer formed on the N type epitaxial layer. A semiconductor having a vertical NPN transistor including a formed P-type base, an N^+-type emitter formed on the P-type base, and a collector extraction electrode connected to an electrode wiring formed on the insulating film. A device,
The collector extraction electrode includes a horizontal extraction electrode that is buried horizontally in the insulating film and has an end connected to the N-type epitaxial layer, and a vertical extraction electrode that connects the horizontal extraction electrode and the electrode wiring. A semiconductor device characterized by: