JPH0786418A - Manufacture of semiconductor device and semiconductor device - Google Patents

Abstract

PURPOSE:To provide a forming method of a P-N junction capacitance wherein a sufficiently large junction capacitance can be obtained when the area of a P-N junction part is made small, regarding the forming method of a P-N junction capacitance and a semiconductor storage device. CONSTITUTION:After a first buried layer 3 of the opposite conductivity type is formed on a part of a semiconductor substrate 1 of a conductivity type, a first epitaxial layer 2 of the opposite conductivity type is formed. A second epitaxial layer 6 of the opposite conductivity type is formed by forming a second buried layer 7 of the opposite conductivity type so as to come into contact with the first buried layer 3. An impurity diffusion layer 9 of a conductivity type is formed by introducing impurities of a conductivity type into the region corresponding with the second buried layer 7 of the second epitaxial layer 6 and annealing the substrate. A P-N junction capacitance is formed between the impurity diffusion layer 9 of a conductivity type and the second buried layer 7 of the opposite conductivity type.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a PN junction capacitor and a semiconductor device.

[0002]

2. Description of the Related Art In order to improve the soft error resistance of an IC (semiconductor integrated circuit) due to α rays, it is necessary to increase the PN junction capacitance.

A conventional PN junction capacitance forming method is as follows.
As shown in FIG. 7, for example, n is formed on the p-type silicon substrate 11.
After forming the ⁺ type buried layer 13, the n ⁻ type epitaxial layer 12 is epitaxially grown, and a p type impurity is introduced into the PN junction formation region of the n ⁻ type epitaxial layer 12 so as to be in contact with the n ⁺ type buried layer 13. ^{A +} type impurity diffusion region 14 is formed, and the p ⁺ type impurity diffusion region 14 and n are formed.
A method of forming a PN junction capacitor at the junction with the ⁺ type buried layer 13 is known.

[0004]

The size of the junction capacitance is P
It depends on the area of the N-junction. The area of the PN junction must be reduced in order to improve the degree of integration of the IC, but if the area is reduced, the junction capacitance is reduced and the soft error resistance due to α rays is reduced.

An object of the present invention is to eliminate this drawback, and a method of forming a PN junction capacitor which allows a sufficiently large junction capacitance to be obtained even if the area of the PN junction portion is reduced, and a method of forming the same. And a semiconductor device incorporating a PN junction capacitor formed by using the forming method.

[0006]

Among the above objects, the method of manufacturing a semiconductor device is such that a first buried layer (3) of opposite conductivity type is formed in a partial region of a semiconductor substrate (1) of one conductivity type. Then, on the semiconductor substrate (1) of the one conductivity type on which the first buried layer (3) is formed, the first semiconductor of the opposite conductivity type is formed.
An epitaxial layer (2) is formed, and a second buried layer of the opposite conductivity type is formed in the PN junction forming region of the first epitaxial layer (2) so as to be in contact with the first buried layer (3). Forming a layer (7), and forming a second epitaxial layer (6) of the opposite conductivity type on the first epitaxial layer (2) on which the second buried layer (7) is formed. , The impurity of one conductivity type is introduced into a region of the second epitaxial layer (6) corresponding to the second buried layer (7), and annealed to introduce an impurity diffusion layer of one conductivity type (9). ) Is formed and a PN junction capacitance is formed with the second buried layer (7) of the opposite conductivity type. The amount of the one conductivity type impurity introduced into the second epitaxial layer (6) and the annealing temperature and time may be adjusted to adjust the size of the PN junction capacitance.

Among the above-mentioned objects, the semiconductor device includes a semiconductor substrate (1) of one conductivity type and a first epitaxial layer () of the opposite conductivity type formed on the surface of the semiconductor substrate (1) of one conductivity type. 2) and this first epitaxial layer (2)
A second epitaxial layer (6) formed on the surface of the semiconductor device, the opposite conductivity type formed between the semiconductor substrate (1) and the first epitaxial layer (2). First buried layer (3) and a second conductive type second layer formed on the surface of the first buried layer (3).
A buried layer (7) and an impurity layer (9) of one conductivity type formed on the surface of the second buried layer (7),
Moreover, it is achieved by a semiconductor device having at least a junction capacitance between the second buried layer (7) and the impurity layer (9).

[0008]

Function: The impurity diffusion layer 9 of one conductivity type and the second conductivity type of the opposite conductivity type
Since the impurity diffusion distance (depth) of each buried layer 7 is short, the impurity concentration at the PN junction can be made higher than in the conventional case, and a large junction capacitance can be formed. Therefore, even if the area of the PN junction is reduced to improve the degree of integration, a sufficient junction capacitance can be formed, and the soft error resistance due to α rays can be improved.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of forming a PN junction capacitor according to an embodiment of the present invention and a semiconductor memory device incorporating a junction capacitor formed by the method will be described below with reference to the drawings.

Referring to FIG. 2, an n ⁺ -type impurity is ion-implanted into a partial region of the p ⁻ -type silicon substrate 1 using a known method, and then an n ⁻ -type first silicon layer 2 is epitaxially grown. This allows
The n ⁺ type first buried layer 3 is formed.

Referring to FIG. 3, a resist film 4 is formed and patterned to form an opening 5 in the junction capacitance forming region.

Referring to FIG. 4, n ⁺ -type impurities are ion-implanted into the n ⁻ -type first silicon layer 2 through the opening 5 of the resist film 4 and then the resist film 4 is removed to remove the n ⁻ -type second silicon. The layer 6 is grown epitaxially. As a result, the n ⁺ -type second buried layer 7 is formed in the junction capacitance forming region.

When a bipolar transistor is formed on the first and second silicon layers 2 and 6 in the region excluding the PN junction capacitance forming region, in order to keep the withstand voltage of the transistor at the same level as in the conventional case, an n ^- type transistor is used. The first silicon layer 2 and n ⁻
The total thickness of the second silicon layer 6 of the mold must be the same as the thickness of the conventional n ^- silicon layer 12 shown in FIG. Further, in order to increase the impurity concentration of the PN junction, it is preferable that the thickness of the n ⁻ -type second silicon layer 6 be thin.

Referring to FIG. 1, the field oxide film 8 is selectively formed in a region except on the n ⁺ -type second buried layer 7 by using the same method as the conventional method. Then, the p ⁺ -type impurity is selectively ion-implanted into the n ⁻ -type second silicon layer 6 on the n ⁺ -type second buried layer 7 and annealed to diffuse the impurity to p ^{+ -type.}
A type impurity diffusion region 9 is formed, and a PN junction is formed with the n ⁺ type second buried layer 7. Hereinafter, the electrode 10 made of polysilicon, aluminum or the like is formed by using a usual method.

FIG. 5 is a circuit diagram of an emitter coupled logic (ECL) type random access memory (RAM) including bipolar transistors. In this circuit diagram, the capacitance C _WC connected between the word line and the collector of the bipolar transistor BPT and the capacitance C _CB connected between the collector and the base of the bipolar transistor BPT form the junction capacitance. FIG. 6 shows a sectional view of the device when it is formed by using the method in a range surrounded by a broken line in FIG. 5 which is directly related to the present invention.

Referring to FIG. 6, in FIG. 6, 1 is a p ^- type silicon substrate and 3 is n.
⁺ -Type a first buried layer of, 2 the n ^- a first silicon layer of the mold, 6 the n ^- a second silicon layer of the mold, a second buried layer of n ⁺ type 7 And 9 is a p ⁺ type impurity diffusion region. p ⁺ type impurity diffusion region 9 and n ⁺
A PN junction is formed between the second buried layer 7 of the mold and a junction capacitance C _WC and a junction capacitance C _CB are formed. Symbol BP
Although the range indicated by T is a well-known bipolar transistor, detailed description thereof will be omitted, but 21 is an emitter, 22 is a base, 23 is a collector electrode contact region, 24 is a field oxide film, E
Is an emitter electrode, B is a base electrode, and C is a collector electrode.

By connecting the electrode 25 of the junction capacitance C _WC to the word line, the junction capacitance C _WC is inserted between the word line and the collector electrode C. Also, the junction capacitance C _CB
By connecting the electrode 26 of B to the base electrode B, the junction capacitance C _CB is inserted between the base electrode B and the collector electrode C.

[0018]

As described above, in the method of manufacturing a semiconductor device and the semiconductor device according to the present invention, the second buried layer of the opposite conductivity type is formed on the first buried layer of the opposite conductivity type. Since the PN junction is formed by forming the impurity diffusion region of the one conductivity type on the second buried layer of the opposite conductivity type, it is possible to increase the impurity concentration of the PN junction portion, which is small. A large junction capacitance can be formed with the area of the junction. As a result,
Even when the degree of integration of the IC is improved, the soft error resistance to α rays becomes good, which largely contributes to the improvement of the reliability of the semiconductor device.

[Brief description of drawings]

FIG. 1 is a sectional view of a PN junction capacitor according to the present invention.

FIG. 2 is a manufacturing process diagram of a PN junction capacitor.

FIG. 3 is a manufacturing process diagram of a PN junction capacitor.

FIG. 4 is a manufacturing process diagram of a PN junction capacitor.

FIG. 5 is a circuit diagram of an ECL RAM.

FIG. 6 is a cross-sectional view when an PN junction capacitor according to the present invention is used in an ECL RAM.

FIG. 7 is a cross-sectional view of a PN junction capacitor according to a conventional technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 p ⁻ type silicon substrate 2 n ⁻ type first silicon layer 3 n ⁺ type first burying layer 4 resist film 5 opening 6 n ⁻ type second silicon layer 7 n ⁺ type second burying Layer 8 Field oxide film 9 p ⁺ type impurity diffusion region 10 Electrode 11 p ⁻ type silicon substrate 12 n ⁻ Silicon layer 13 n ⁺ type buried layer 14 p ⁺ type impurity diffusion region 21 Emitter 22 Base 23 Collector electrode contact region 24 Field oxidation Film 25 Junction capacitance C _WC electrode 26 Junction capacitance C _CB electrode E Emitter electrode B Base electrode C Collector electrode BPT Bipolar transistor C _CB Collector-base junction capacitance C _WC Wordline-collector junction capacitance

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/822

Claims (3)

[Claims] 1. A first buried layer (3) of opposite conductivity type is formed in a partial region of a semiconductor substrate (1) of one conductivity type, and the first buried layer (3) is formed. The first epitaxial layer (2) of the opposite conductivity type is formed on the semiconductor substrate (1) of the conductivity type, and the first buried layer () is formed in the PN junction formation region of the first epitaxial layer (2). 3) A second buried layer (7) of the opposite conductivity type is formed so as to be in contact with the opposite conductive type, and the opposite conductivity is formed on the first epitaxial layer (2) on which the second buried layer (7) is formed. Type second epitaxial layer (6) is formed, the one conductivity type impurity is introduced into a region of the second epitaxial layer (6) corresponding to the second buried layer (7), and annealing is performed. An impurity diffusion layer (9) of one conductivity type is formed, and the impurity diffusion layer (9) of the opposite conductivity type is formed. 2 of the buried layer (7)
And a step of forming a PN junction capacitance between the semiconductor device and the semiconductor device. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the amount of impurities of one conductivity type introduced into the second epitaxial layer (6) and the temperature and time of annealing are adjusted to obtain the PN junction capacitance. A method for manufacturing a semiconductor device, characterized in that the size is adjusted. 3. A semiconductor substrate (1) of one conductivity type, a first epitaxial layer (2) of opposite conductivity type formed on the surface of the semiconductor substrate (1) of one conductivity type, and the first substrate. A semiconductor device comprising a second epitaxial layer (6) formed on the surface of an epitaxial layer (2), wherein the semiconductor device is formed between the semiconductor substrate (1) and the first epitaxial layer (2). A first buried layer (3) of opposite conductivity type, a second buried layer (7) of opposite conductivity type formed on the surface of the first buried layer (3), and the second buried layer ( 7) and an impurity layer (9) of one conductivity type formed on the surface of (7), and at least a junction capacitance between the second buried layer (7) and the impurity layer (9). A semiconductor device characterized by the above.