JPH0722528A - Semiconductor device and fabrication thereof - Google Patents

Abstract

PURPOSE:To reduce the area of a semiconductor device in which there are formed on the same substrate a bipolar transistor operable in an analog manner and a logic circuit, and further reduce the number of fabrication processes of the semiconductor device. CONSTITUTION:There are formed an nSIT 2, a D-type p<-> MIS transistor 5, and an E-type pMOS transistor 6 on a p type semiconductor substrate 1. In a fabrication process of the semiconductor device, there are simultaneosuly formed a p<+> type gate region 15A of the nSIT2, and p<+> type source regions 15D, 15E and p'' type drain regions 15D', 15E' of the MOS transistors 5, 6 and further there are simultaneously formed a source polysilicon electrode 18A of the nSIT2 and gate electrodes 18D, 18E of the MOS transistors 5, 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a bipolar transistor and a MOS transistor are formed on the same substrate, and a manufacturing method thereof.

[0002]

2. Description of the Related Art The development of semiconductor technology that supports the electronics industry is remarkable, and it is used in all fields. Further, various developments are being made according to applications such as high power consumption and high speed. Further, in order to meet the demand for miniaturization of various electronic devices, integration of semiconductor devices has been promoted.

FIG. 8 shows a semiconductor in which a bipolar static induction transistor capable of handling a relatively large amount of power and capable of high-speed switching and a logic circuit for controlling driving of the static induction transistor are formed on the same substrate. Shows the device.

In FIG. 1, the surface portion of the p ^-- type semiconductor substrate 1 is
1 shows a cross section of a semiconductor device in which a bipolar n-type static induction transistor 2 (hereinafter simply referred to as nSIT2), a capacitor 3, and two lateral pnp transistors 4 as logic circuits are formed.

The elements, that is, the nSIT 2, the capacitor 3, and the pnp transistor 4 are electrically isolated from each other by p ⁺ type isolation diffusion regions 11A, 11B, and 11C.

The nSIT 2 has an n ⁺ -type buried layer 12A at the bottom of an n ^-- type epitaxial layer 13A formed on the surface of the p ^-- type semiconductor substrate 1. Then, n ^- the surface portion of the type epitaxial layer 13A, p ^- type channel layer 14, the p ^- on the surface of the mold channel layer 14 ^- so as to surround the mold channel layer 14 p ⁺ -type gate region 15, p An n ⁺ type drain region 17 is selectively formed on the surface of the n ⁺ type source region 16 and the n ⁻ type epitaxial layer 13A at a position spaced apart from the p ⁺ type gate region 15 by a predetermined distance.

Further, the source polysilicon electrode 18 and the n ⁺ type drain region 17 are connected to the n ⁺ type source region 16.
And a drain polysilicon electrode 19 is formed. Further, the source electrode 20 and the drain electrode 2 are connected to the source polysilicon electrode 18, the drain polysilicon electrode 19 and the p ⁺ type gate region 15, respectively.
1 and the gate electrode 22 are formed. The electrodes are insulated from each other by the field oxide film 23 and the interlayer insulating film 24.

The capacitor 3 has an n ⁺ type buried layer 12B at the bottom of an n ⁻ type epitaxial layer 13B formed on the surface of the p ⁻ type semiconductor substrate 1. Then, the p ⁺ type semiconductor region 31 is formed on the surface portion of the n ⁻ type epitaxial layer 13B. In addition, the p ⁺ type semiconductor region 31
An electrode 32 is formed in contact with the vicinity of the end of the surface, and an electrode 34 is formed on the upper surface of the p ⁺ type semiconductor region 31 and above the capacitor oxide film 33 thinner than the field oxide film 23.

The pnp transistor 4 has an n ⁺ type buried layer 12C at the bottom of an n ⁻ type epitaxial layer 13C formed on the surface of the p ⁻ type semiconductor substrate 1. Also,
n ^- type in the surface portion of the epitaxial layer @ 13 C, p ⁺ -type emitter region 41, p ⁺ -type emitter region 41 at a predetermined distance from the p ⁺ -type emitter region 41 so as to surround the p ⁺ -type collector region 42, and p ⁺ type collector region 4
An n ⁺ type base region 43 is formed at a position slightly distant from the outer side of 2. A base polysilicon electrode 44 is formed so as to be connected to the n ⁺ type base region 43, and the p ⁺ type emitter region 41 and the p ⁺ type collector region 4 are further formed.
2, and an emitter electrode 45, a collector electrode 46, and a base electrode 47 are formed so as to be connected to the base polysilicon electrode 44 and the base polysilicon electrode 44, respectively.

As described above, conventionally, when a bipolar electrostatic induction type transistor for analog operation and a logic circuit for digital control are formed on the same substrate, the logic circuit is generally bipolar type. It consisted of transistors.

[0011]

By the way, in the case of forming a plurality of bipolar transistors on the same substrate, in order to prevent the operation of each bipolar transistor from being influenced by an adjacent bipolar transistor,
It has become common to isolate each bipolar transistor by a reverse biased pn junction. In the example shown in FIG. 8, the potential of the p ⁺ type isolation diffusion region 11C formed between the pnp transistors 4 and 4 is set lower than the potential of the n ⁻ type epitaxial layer 13C, so that the pnp transistor 4 is formed. , 4 are separated.

In FIG. 8, only two pnp transistors 4 are shown as lateral type bipolar transistors forming a logic circuit, but in actuality, a large number are formed. Therefore, in order to isolate the large number of bipolar transistors, a large number of p ⁺ -type isolation diffusion regions 1 are formed.
1C must be formed.

However, this p ⁺ type isolation diffusion region 11C
Is deeply diffused so as to reach the p ⁻ type semiconductor substrate 1 from the surface of the n ⁻ type epitaxial layer 13C, so that it is inevitably diffused in the lateral direction as well. Therefore, the area of the region formed to separate the bipolar transistors from each other becomes larger than the entire semiconductor device, and the area where an actual element can be formed becomes relatively small, so that the area efficiency of the semiconductor device is improved. There was a problem of being bad.

The present invention solves the above problems,
An object of the present invention is to provide a method for reducing the area of a semiconductor device in which a bipolar transistor and a logic circuit for analog operation are formed on the same substrate and manufacturing the semiconductor device with a smaller number of steps.

[0015]

According to a first aspect of the present invention, a semiconductor device is formed so as to surround a first conductivity type low impurity concentration semiconductor region and the first conductivity type low impurity concentration semiconductor region. Connected to the surfaces of the first conductivity type high impurity concentration semiconductor region and the second conductivity type semiconductor region formed on the surface portion in the first conductivity type low impurity concentration semiconductor region and the surface of the second conductivity type semiconductor region. It is premised that a transistor having a second conductivity type polysilicon electrode and a MOS transistor are formed on the same semiconductor substrate.

The transistor formed with the MOS transistor on the semiconductor substrate is, for example, a static induction transistor (SIT). In this case, the first conductivity type low impurity concentration semiconductor region, the first conductivity type high impurity concentration semiconductor region, the second conductivity type semiconductor region, and the second conductivity type polysilicon electrode are respectively the channel layers of the SIT. , Gate region, source region, and source polysilicon electrode.

Then, the first conductivity type high impurity concentration semiconductor region and the source region and drain region of the MOS transistor are formed in the same step. The semiconductor device according to claim 2 is based on the semiconductor device according to claim 1, and the semiconductor region of the second conductivity type and the channel stopper of the MOS transistor are formed in the same step.

A semiconductor device according to claim 3 is the semiconductor device according to claim 1.
Based on the semiconductor device described in (1) above, a plurality of the MOS transistors are formed, and the plurality of MOS transistors include both enhancement type MOS transistors and depletion type MOS transistors.

A semiconductor device according to a fourth aspect is the semiconductor device according to the third aspect.
On the premise of the semiconductor device described in 1), the gate oxide film of the enhancement type MOS transistor is formed in the same step as the field oxide film of the semiconductor substrate.

A semiconductor device according to a fifth aspect is the semiconductor device according to the third aspect.
On the premise of the semiconductor device described in 1. above, the polysilicon electrode and the gate electrode of the enhancement type MOS transistor are formed in the same step.

A semiconductor device according to a sixth aspect is the semiconductor device according to the third aspect.
Based on the semiconductor device described in 1. above, the polysilicon electrode and the gate electrodes of the enhancement type MOS transistor and the depletion type MOS transistor are formed in the same step.

According to a seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which a first conductivity type low impurity concentration semiconductor region and a first conductivity type low impurity concentration semiconductor region are formed so as to surround the first conductivity type low impurity concentration semiconductor region. A second conductivity type semiconductor region formed on a surface portion in the conductivity type high impurity concentration semiconductor region and the first conductivity type low impurity concentration semiconductor region, and a second conductivity type connected to the second conductivity type semiconductor region. It is premised on a method of manufacturing a semiconductor device in which a transistor having a polysilicon electrode and a MOS transistor are formed on the same semiconductor substrate. Further, similar to the semiconductor device according to claim 1, the transistor is, for example, an electrostatic induction transistor (SI).
T).

Then, there is a first step of simultaneously forming the high-concentration semiconductor region of the first conductivity type and the source region and the drain region of the MOS transistor.
A method of manufacturing a semiconductor device according to claim 8 of the present invention is directed to a first conductivity type low impurity concentration semiconductor region and a first conductivity type low impurity concentration semiconductor region formed so as to surround the first conductivity type low impurity concentration semiconductor region. A second conductivity type semiconductor region formed on a surface portion in the high impurity concentration semiconductor region and the first conductivity type low impurity concentration semiconductor region, and a second conductivity type polysilicon connected to the second conductivity type semiconductor region. It is premised on a method for manufacturing a semiconductor device in which a transistor having an electrode, an enhancement type MOS transistor, and a depletion type MOS transistor are formed on the same semiconductor substrate. Further, similar to the semiconductor device according to claim 1, the transistor is, for example, a static induction transistor (SIT).

Then, a second region for simultaneously forming the first conductivity type high impurity concentration semiconductor region, the source region and the drain region of the enhancement type MOS transistor, and the source region and the drain region of the depletion type MOS transistor are formed. Have steps.

The method for manufacturing a semiconductor device according to claim 9 is based on the method for manufacturing a semiconductor device according to claim 8, and after the second step, a field oxide film is formed on the semiconductor substrate. The third step, the fourth step of selectively removing the field oxide film to form the gate oxide film of the depletion type MOS transistor in the region where the field oxide film is removed, and the depletion type MOS transistor There is a fifth step of performing channel doping through the gate oxide film.

A method for manufacturing a semiconductor device according to a tenth aspect is based on the method for manufacturing a semiconductor device according to the ninth aspect, and after the fifth step, the upper surface of the low-concentration semiconductor region of the first conductivity type is formed. 6. The sixth step of selectively removing the field oxide film and uniformly depositing polysilicon from the upper surfaces of the field oxide film and the gate oxide film, and etching the deposited polysilicon to remove the polysilicon film. There is a seventh step of forming a silicon electrode, a gate electrode of the enhancement type MOS transistor, and a gate electrode of the depletion type MOS transistor.

The method for manufacturing a semiconductor device according to claim 11 is based on the method for manufacturing a semiconductor device according to claim 8, and after the second step, a field oxide film is formed on the semiconductor substrate. An eighth step, a ninth step of forming an insulating film on the field oxide film, and a step of selectively removing the field oxide film and the insulating film to form a region above the field oxide film and the insulating film. Tenth step of forming a gate oxide film of a depletion type MOS transistor, and eleventh step of performing channel doping through the gate oxide film of the depletion type MOS transistor.
Has the steps of.

A method for manufacturing a semiconductor device according to a twelfth aspect is based on the method for manufacturing a semiconductor device according to the eleventh aspect, and prior to the ninth step, the low-concentration semiconductor region of the first conductivity type is formed. A twelfth step of selectively removing the field oxide film on the upper surface and uniformly depositing polysilicon from the upper surface of the field oxide film, and etching the deposited polysilicon to form the polysilicon electrode and the enhancement. The thirteenth step includes the step of forming the gate electrode of the MOS transistor.

[0029]

In the semiconductor device of the present invention, the logic circuit portion formed on the semiconductor substrate together with a transistor (hereinafter referred to as SIT for convenience) that operates in an analog manner such as a static induction transistor is formed of a MOS transistor. To do. At this time, a region for electrically isolating the MOS transistors from each other is unnecessary, and the logic circuit portion can be formed in a small area. Therefore, the chip area of the semiconductor device is reduced.

Further, in the manufacturing method, since the gate region of the SIT and the source region and the drain region of the MOS transistor are formed at the same time, and the source polysilicon electrode of the SIT and the gate electrode of the MOS transistor are formed at the same time, the number is small. The semiconductor device can be manufactured by the number of steps.

[0031]

Embodiments of the present invention will be described below with reference to the drawings. In addition, the area | region which attached | subjected the code | symbol same as the code | symbol in FIG.

In this embodiment, the p ^-- type semiconductor substrate 1 is used.
Above the n-type static induction transistor 2 (hereinafter referred to as nSIT2
,), Capacitor 3, and pnp-type transistor 4
And depletion type p-channel MOS transistor 5
A semiconductor device having (hereinafter referred to as D-type pMOS transistor 5) and enhancement-type p-channel MOS transistor 6 (hereinafter referred to as E-type pMOS transistor 6) will be described. Here, the logic circuit of this semiconductor device is composed of a D-type pMOS transistor 5 and an E-type pMOS transistor 6.

The manufacturing process of the first embodiment will be described with reference to FIGS. In the following description, the nSIT2, which is the main part of this semiconductor device, and the D-type p
The manufacturing process of the MOS transistor 5 and the E-type pMOS transistor 6 will be mainly described.

First, as shown in FIG. 1A, the n ⁺ type buried layers 12A, 12B, 1 are formed on the surface of the p ⁻ type semiconductor substrate 1.
An n-type impurity for forming 2C and 12F is selectively introduced. And on the upper surface, 5 × 10 ¹⁴ to 1 ×
An n ⁻ type epitaxial layer is grown with an impurity concentration of about 10 ¹⁵ . (This n ⁻ type epitaxial layer is separated by ap ⁺ type separation diffusion region 11A described later, and n ⁻ type epitaxial layers 13A, 13B, 13C, and 13 are formed.
F is a constituent of F and is not shown here.) Thereafter, a silicon oxide film (not shown) is uniformly formed on the surface of the n ⁻ type epitaxial layer. Then, the silicon oxide film is selectively removed, and p-type impurities are introduced into the surface of the n ⁻ type epitaxial layer using the silicon oxide film as a mask. This p-type impurity is driven in so as to reach the p ⁻ type semiconductor substrate 1 to form the p ⁺ type isolation diffusion region 11A. Due to the p ⁺ type isolation diffusion region 11A, the n ⁻ type epitaxial layer becomes n
^- -type epitaxial 13A, 13B, 13C, and 1
It is divided into 3F and becomes regions for forming the nSIT 2, the pnp type transistor 4, the capacitor 3, and the D type pMOS transistor 5 and the E type pMOS transistor 6, respectively. At the same time, the n-type impurities introduced into the surface of the p ⁻ type semiconductor substrate 1 are also diffused, and n
⁺ Type buried layers 12A, 12B, 12C, and 12F are formed.

After that, a silicon oxide film (not shown) is again formed uniformly, and the silicon oxide film is selectively removed on the n ⁻ type epitaxial layer 13A. Then, using the silicon oxide film as a mask, a p ^- type film is formed on the surface of the n ⁻ -type epitaxial layer 13A by a general method.
^{The −} type channel layer 14 is formed. p ⁻ type channel layer 14
Is formed to a depth of about 2 to 3 μm.

Then, as shown in FIG. 1B, a silicon oxide film (not shown) is again formed uniformly, and the silicon oxide film (not shown) is again formed on the n ⁻ type epitaxial layer 13A at the end of the p ⁻ type channel layer 14. The field oxide film is selectively removed at a position where it overlaps and a predetermined position above the n ⁻ type epitaxial layer 13F. Then, after introducing the p-type impurity using the field oxide film as a mask, the p-type impurity is diffused to p-type on the surface portion of the n ⁻ -type epitaxial layer 13A.
^{A +} type gate region 15A is formed. The p ⁺ type gate region 15A is formed to a depth of about 2 to 4 μm so as to be deeper than the depth of the p ⁻ type channel layer 14. Further, the p ⁺ type gate region 15A surrounds the p ⁻ type channel layer 14. On the other hand, the n ⁻ type epitaxial layer 13F
P ⁺ type source regions 15D, 15E
And p ⁺ -type drain regions 15D 'and 15E' are p ⁺
It is formed simultaneously with the formation of the mold gate region 15A. (First
Or the second step) In the above step, the p ⁻ type channel layer 14 and
Although the p ⁺ type gate region 15A and the like are diffused in a separate step, they may be driven in at the same time in the next step of forming the silicon oxide film 23.

Thereafter, a silicon oxide film (field oxide film) 23 is uniformly formed on the surfaces of the n ^-- type epitaxial layers 13A and 13F in which the respective regions are formed. (Third or Eighth Process) Next, as shown in FIG. 2A, the p ⁺ type source region 15 is formed.
The field oxide film 23 above the n ⁻ type epitaxial layer 13F between the D and the p ⁺ type drain region 15D ′ and in the vicinity thereof is selectively removed. After that, the gate oxide film 51 is formed on the surface of the region where the field oxide film 23 is removed. (Fourth Step) Subsequently, the field oxide film 23 and the gate oxide film 51.
P-type impurities are ion-implanted (channel dope) from above. The acceleration energy of the ion implantation at this time is such that it can pass through the gate oxide film 51 and not through the field oxide film 23.
The type impurity amount is determined by the characteristics of the D-type pMOS transistor 5. Therefore, the p ⁺ type source region 15D
A p channel 50 is formed in the surface portion of the n ⁻ type epitaxial layer 13F between the p ⁺ type drain region 15D ′ and the p ⁻ type drain region 15D ′. (Fifth Step) As described above, in the fifth step, channel doping can be performed only in a desired region by utilizing the difference in film thickness between the gate oxide film 51 and the field oxide film 23. It is not necessary to prepare a mask for performing the channel doping. Further, in the capacitor 3 described later, the p-type impurity reaches the p ⁺ -type semiconductor region 31 through the capacitor oxide film 33 having the same thickness as the gate oxide film 51.
Since they have the same conductivity type (p type), they do not affect the electrical characteristics.

Next, as shown in FIG. 2B, the field oxide film 23 is formed on the p ⁻ type channel layer 14 and on the n ⁻ type epitaxial layer 13A at a predetermined distance from the p ⁺ type gate region 15A. Are selectively removed. Also, p
Also on the upper surface of the n ⁻ type epitaxial layer 13F between the ⁺ type drain region 15D ′ and the p ⁺ type source region 15E,
The field oxide film 23 is selectively removed. Then, on the upper surfaces of the field oxide film 23 and the gate oxide film 51,
Polysilicon 18 'is uniformly deposited. The method of depositing the polysilicon 18 'is, for example, the CVD method. Here, in the region where the field oxide film 23 is selectively removed, the polysilicon 18 ′ is formed in each semiconductor region (p ⁻ type channel layer 14, n ⁻ type epitaxial layer 13A, and n ⁻ type epitaxial layer 13F). Connect directly to part of the surface. (Sixth Step) Next, as shown in FIG. 3, the polysilicon 18 ′ is selectively removed by etching, and the source polysilicon electrode 18 A connected to the p ⁻ type channel layer 14 and the n ⁻ type epitaxial layer are formed. Drain polysilicon electrode 19 connected to layer 13A, gate electrode 1 on the surface of gate oxide film 51
8D, p ⁺ type source region 15E and p ⁺ type drain region 1
Field oxide film 2 on and near the upper portion between 5E '
3. A gate electrode 18E on the upper surface of 3 and a channel stopper polysilicon electrode 18F connected to the n ⁻ type epitaxial layer 13F between the p ⁺ type drain region 15D ′ and the p ⁺ type source region 15E are formed. (Seventh Step) Further, in FIG. 3, after the seventh step, n-type impurities are ion-implanted over the entire surface. The ion implantation acceleration energy at this time is such that the n-type impurities can pass through the polysilicon layer (the source polysilicon electrode 18A or the like) which is each of the polysilicon electrodes, and the n-type impurities pass through the polysilicon layer. Type impurity is gate oxide film 5
It is a size that cannot pass 1. Further, the n-type impurities cannot pass through the field oxide film 23 due to the acceleration energy.

When the n-type impurities are ion-implanted with such acceleration energy, the n-type impurities that have passed through the source polysilicon electrode 18A and the drain polysilicon electrode 19 are removed from the surface portion of the p ^-- type channel layer 14 and the n ^-- type channel layer 14, respectively. It is injected into the surface portion of the mold epitaxial layer 13A.
Further, the n-type impurities that have passed through the channel stopper polysilicon electrode 18F are injected into the surface portion of the n ⁻ type epitaxial layer 13F. However, the n-type impurities that have passed through the gate electrode 18D are blocked by the gate oxide film 51 and do not reach the n ⁻ -type epitaxial layer 13F (or the p channel 50). Furthermore, since the field oxide film 23 is formed in the other regions, n-type impurities do not reach each semiconductor region.

[0040] Then, by the n-type impurities implanted into the surface portion of each of these regions is thermally diffused, p ^- surface portion n ⁺ -type source region 16A of the type channel layer 14, n ^- the surface of the type epitaxial layer 13A A channel stopper 16F is formed on the surface of the n ⁺ type drain layer 17 and the n ⁻ type epitaxial layer 13F between the p ⁺ type drain region 15D ′ and the p ⁺ type source region 15E.

[0041] p ^- n ⁺ -type source region 16A of the surface of the mold channel layer 14, p ^- the p ⁺ -type gate region 15A, which is formed so as to surround the mold channel layer 14,
It is formed with a gap of 1 to 2 μm. This is shown in FIG.
In (b), it can be realized by appropriately designing a mask shape for selectively removing the field oxide film 23 on the p ⁻ type channel layer 14.

By the above ion implantation, the source polysilicon electrode 18A and the drain polysilicon electrode 19 become the n ⁺ type source regions 16A and n ⁺ , respectively.
Although it is in a state of being connected to the surface of the type drain region 17, a large amount of n-type impurities are implanted into the polysilicon forming the electrodes 18A and 19, so that each of them has an appropriate resistance value as an electrode.

After the step of FIG. 3, as shown in FIG.
The interlayer insulating film 24 such as SG is uniformly formed. And
The interlayer insulating film 24 is selectively removed on the source polysilicon electrode 18A and the drain polysilicon electrode 19. In addition, p ⁺ type gate region 15A, p ⁺ type source regions 15D and 15E, and p ⁺ type drain region 15D ′,
The interlayer insulating film 24 and the field oxide film 23 are selectively removed on the upper portion of 15E '.

After that, aluminum or aluminum-silicon electrodes are formed by connecting to the corresponding regions. That is, the source electrode 20 is formed by connecting to the source polysilicon electrode 18A, and the drain electrode 21 is formed by connecting to the drain polysilicon electrode 19. Further, the gate electrode 22 is formed in contact with the surface of the p ⁺ type gate region 15A. Furthermore, connected to the p ⁺ -type source region 15D and the p ⁺ -type drain region 15D ', respectively forming the source electrode 52 and drain electrode 53 of the D-type pMOS transistor 5, p ⁺ -type source region 15E and p ⁺ -type drain Connect to area 15E 'and
A source electrode 61 and a drain electrode 62 of the pMOS transistor 6 are formed. The channel stopper polysilicon electrode 18F is formed of the n ^-- type epitaxial layer 13
It is connected to a region having a stable potential so that the potential of F does not become a floating state.

Next, the parts of the manufacturing process diagrams of FIGS. 1 to 3 that are not described will be described. The p ⁺ type semiconductor region 31 of the capacitor 3 is formed by nS in the first or second step.
It is formed at the same time as the p ⁺ type gate region 15A of IT2. Further, the capacitor oxide film 33 is formed at the same time as the gate oxide film 51 of the D-type pMOS transistor 5 in the fourth step. Further, the oxide film 33 for the capacitor
The upper polysilicon electrode 35 is formed simultaneously with the source polysilicon electrode 18A of nSIT2 in the seventh step. Then, the electrode 36 is formed by connecting to the polysilicon electrode 35, and the electrode 32 is formed by connecting to the surface of the p ⁺ type semiconductor region 31.

The p ⁺ type emitter region 41 and the p ⁺ type collector region 42 of the pnp transistor 4 are formed simultaneously with the p ⁺ type gate region 15A of the nSIT2 in the first or second step. In addition, the n ⁺ type base region 43
Are formed at the same time as the n ⁺ type source region 16A of nSIT2. Further, the base polysilicon electrode 44 is formed at the same time as the source polysilicon electrode 18A of nSIT2 in the seventh step. Then, an emitter electrode 45 and a collector electrode 46 are formed to be connected to the surfaces of the p ⁺ type emitter region 41 and the p ⁺ type collector region 42, respectively, and a base electrode 47 is formed to be connected to the base polysilicon electrode 44.

NSIT2 formed as described above
It is, n is shown as an example ^- in response to the impurity concentration of the type epitaxial layer 13A, the distance between the depth and the p ⁺ -type gate region 15A and the n ⁺ -type source region 16A of p ⁺ -type gate region 15A is designed It Then, by forming the structure shown in the above embodiment, the characteristics of the SIT can be obtained while performing the bipolar operation. That is, the amplification factor is improved by forming the impurity concentration of the p ⁻ type channel layer 14 lower than the impurity concentration of the base region of a normal bipolar transistor. Generally, when the impurity concentration of the p ⁻ type channel layer 14 is lowered as described above, punch-through easily occurs between the source and the drain, and the breakdown voltage decreases. However, the nSIT2 above structure, p ^- so as to surround the mold channel layer 14, and the p ^- In the cross-sectional view of which is deeper than type channel layer 14 (FIG. 4, p ^- type channel layer 14 The depletion layers extending from the p ⁺ type gate region 15A (formed on the left and right sides) reach each other under the p ⁻ type channel layer 14 to secure the above breakdown voltage.

In the semiconductor device shown in this embodiment,
As described above, since the formation of the nSIT 2 having the above characteristics and the formation of the D-type pMOS transistor 5 and the E-type pMOS transistor 6 are performed in the same steps as much as possible, the manufacturing can be performed with a small number of steps. .

[0049] Also, n D-type pMOS transistors 5 and E-type pMOS transistor 6 is formed ^- but to form a connected to the lower portion of the type epitaxial layer 13F n ⁺ -type buried layer 12F, the n ⁺ -type Buried layer 12F
Is ap ⁻ type semiconductor substrate 1 and an n ⁻ type epitaxial layer 13
F and p ⁺ type source regions 15D, 15E or p ⁺
Parasitic pnp consisting of type drain regions 15D ', 15E'
It prevents the transistor from turning on.

Next, the second embodiment will be described with reference to FIGS.
Will be explained. The manufacturing process of the semiconductor device of the second embodiment is partially the same as the manufacturing process of the first embodiment. That is, the steps described with reference to FIGS.
Since this process is also performed in the second embodiment, the process after FIG. 1B will be described here.

After the state of FIG. 1 (b), as shown in FIG. 5 (a), an n ^-- type epitaxial layer 13A spaced apart from the upper part of the p ^-- type channel layer 14 and the p ⁺ type gate region 15A by a predetermined distance. The field oxide film 23 is selectively removed on the upper part of the. Further, the field oxide film 23 is selectively removed also on the upper surface of the n ⁻ type epitaxial layer 13F between the p ⁺ type drain region 15D ′ and the p ⁺ type source region 15E. Then, the polysilicon 18 ′ is uniformly deposited on the upper surface of the field oxide film 23. This polysilicon 1
The 8'deposition method is, for example, a CVD method. Here, in the region where the field oxide film 23 is selectively removed, the polysilicon 18 'is formed in each semiconductor region (p ⁻ type channel layer 14, n ⁻ type epitaxial layer 13A, and n ^{− type).}
It is directly connected to a part of the surface of the type epitaxial layer 13F). (Twelfth Step) Subsequently, as shown in FIG.
Are selectively removed by etching. By this etching, the source polysilicon electrode 18A connected to the p ⁻ type channel layer 14 and the n ⁻ type epitaxial layer 1 are formed.
Drain polysilicon electrode 19 connected to 3A, p
The gate electrode 18E on the upper surface of the field oxide film 23 in the upper part and the vicinity thereof between the ⁺ type source region 15E and the p ⁺ type drain region 15E ′, and the p ⁺ type drain region 15D ′.
A channel stopper polysilicon electrode 18F connected to the n ⁻ type epitaxial layer 13F between the p ⁺ type source region 15E and the p ⁺ type source region 15E is formed. (Thirteenth step) Further, in FIG. 5B, after the thirteenth step, n-type impurities are ion-implanted over the entire surface. The ion implantation acceleration energy at this time is of a magnitude that allows the n-type impurities to pass through the polysilicon electrode but not the field oxide film 23.
Then, when the n-type impurity is ion-implanted with this acceleration energy, the n-type impurity becomes p ^{− −} as in the first embodiment.
The n ^- type epitaxial layer 13A and the surface regions of the n ⁻ type epitaxial layer 13A and the n ⁻ type epitaxial layer 13F are implanted.

[0052] Then, by the n-type impurities implanted into the surface portion of each of these regions is thermally diffused, p ^- surface portion n ⁺ -type source region 16A of the type channel layer 14, n ^- the surface of the type epitaxial layer 13A forming a channel stopper 16F on the surface of the mold epitaxial layer 13F ^- n ⁺ -type drain region 17, p ⁺ -type drain region 15D 'and between the p ⁺ -type source region 15E n separate component.

Thereafter, as shown in FIG. 6, on the upper surface of the field oxide film 23 and the upper surface of each polysilicon electrode,
An interlayer insulating film 24 such as PSG is uniformly formed. (9th
Then, the field oxide film 23 and the interlayer insulating film 24 above the n ⁻ type epitaxial layer 13F between the p ⁺ type source region 15D and the p ⁺ type drain region 15D ′ and in the vicinity thereof are selectively removed. . After this, the field oxide film 2
A gate oxide film 51 is formed on the surface of the region where 3 and the interlayer insulating film 24 are removed. (Tenth Step) Then, as in the first embodiment, ion implantation (channel doping) of p-type impurities is performed through the gate oxide film 51 to form the p ⁺ -type source region 15D and the p ⁺ -type drain region 15.
On the surface of the n ⁻ type epitaxial layer 13F between D ′ and
The p-channel 50 is formed. (Eleventh Step) Thereafter, as shown in FIG. 7, each electrode is formed in the same manner as in the first embodiment. However, the gate electrode of the D-type pMOS transistor 5 is different from that of the first embodiment in that aluminum or aluminum.
An electrode 54 made of silicon is formed.

As described above, in the first and second embodiments, the n-type SIT and the p-channel MOS transistor are formed on the same semiconductor substrate, but the present invention is not limited to this, and the same semiconductor is used. It is also applicable when forming a p-type SIT and an n-channel MOS transistor on a substrate.

[0055]

According to the present invention, when a static induction type transistor and a logic circuit are formed on the same semiconductor substrate, the transistors forming the logic circuit are MO transistors.
Since it is composed of S transistors, the chip area is reduced.

Further, since the formation of the electrostatic induction type transistor and the formation of the MOS transistor are common in many steps, the number of manufacturing steps is reduced.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram (1) of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram (2) of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a manufacturing process diagram (3) of the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a manufacturing process diagram (1) of a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a manufacturing process diagram (2) of the semiconductor device according to the second embodiment of the present invention.

FIG. 7 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 8 is a cross-sectional view of a semiconductor device, which is an example of a conventional semiconductor device, in which a static induction transistor and a lateral pnp transistor are formed on the same semiconductor substrate.

[Explanation of symbols]

1 p ⁻ type semiconductor substrate 2 n type static induction transistor (nSIT) 3 capacitor 4 pnp transistor 5 depletion type p channel MOS transistor (D type pMOS transistor 6 enhancement type p channel MOS transistor (E type pMOS transistor 11A p ⁺ type isolation Diffusion region 12A, F n ⁺ type buried layer 13A, F n ⁻ type epitaxial layer 14 p ⁻ type channel layer 15A p ⁺ type gate region 15D, E p ⁺ type source region 15D ′, E ′ p ⁺ type drain region 16A n ⁺ Type source region 16F n ⁺ type channel stopper 18A source polysilicon electrode 18D, E gate electrode 50 p channel 51 gate oxide film 54 gate electrode

Claims (12)

[Claims] 1. A first conductivity type low impurity concentration semiconductor region and a first conductivity type high impurity concentration semiconductor region formed so as to surround the first conductivity type low impurity concentration semiconductor region and the first conductivity type. And a MOS transistor having a second conductivity type semiconductor region formed on the surface of the low impurity concentration semiconductor region and a second conductivity type polysilicon electrode connected to the surface of the second conductivity type semiconductor region. In a semiconductor device in which the first conductivity type high impurity concentration semiconductor region and the MO layer are formed on the same semiconductor substrate.
A semiconductor device, wherein a source region and a drain region of an S transistor are formed in the same step. 2. A semiconductor region of the second conductivity type and the M
The semiconductor device according to claim 1, wherein the channel stopper of the OS transistor is formed in the same step. 3. The semiconductor device according to claim 1, wherein a plurality of the MOS transistors are formed, and the plurality of MOS transistors include both an enhancement type MOS transistor and a depletion type MOS transistor. 4. The semiconductor device according to claim 3, wherein the gate oxide film of the enhancement type MOS transistor is formed in the same step as the field oxide film of the semiconductor substrate. 5. The semiconductor device according to claim 3, wherein the polysilicon electrode and the gate electrode of the enhancement type MOS transistor are formed in the same step. 6. The semiconductor device according to claim 3, wherein the polysilicon electrode and the gate electrodes of the enhancement type MOS transistor and the depletion type MOS transistor are formed in the same step. 7. A first-conductivity-type low-impurity-concentration semiconductor region, a first-conductivity-type high-impurity-concentration semiconductor region formed so as to surround the first-conductivity-type low-impurity-concentration semiconductor region, and the first-conductivity-type. And a MOS transistor having a second conductivity type semiconductor region formed on the surface of the low impurity concentration semiconductor region and a second conductivity type polysilicon electrode connected to the second conductivity type semiconductor region. A method of manufacturing a semiconductor device formed on the same semiconductor substrate, comprising: a first-conductivity-type high impurity concentration semiconductor region;
A method of manufacturing a semiconductor device, comprising a first step of simultaneously forming a source region and a drain region of a transistor. 8. A first conductivity type low impurity concentration semiconductor region, a first conductivity type high impurity concentration semiconductor region formed so as to surround the first conductivity type low impurity concentration semiconductor region, and the first conductivity type. Of a second-conductivity-type semiconductor region formed on the surface of the low-impurity-concentration semiconductor region and a second-conductivity-type polysilicon electrode connected to the second-conductivity-type semiconductor region, and an enhancement-type MOS transistor And a depletion type MOS transistor are formed on the same semiconductor substrate, wherein the first conductivity type high impurity concentration semiconductor region, a source region and a drain region of the enhancement type MOS transistor, and the depletion Type step of simultaneously forming a source region and a drain region of a MOS transistor The method of manufacturing a semiconductor device characterized in that it comprises. 9. A third step of forming a field oxide film on the semiconductor substrate after the second step, wherein the field oxide film is selectively removed, and the field oxide film is formed in a region where the field oxide film is removed. 9. The semiconductor according to claim 8, further comprising a fourth step of forming a gate oxide film of the depletion type MOS transistor and a fifth step of performing channel doping through the gate oxide film of the depletion type MOS transistor. Device manufacturing method. 10. After the fifth step, the field oxide film on the upper surface of the low-concentration semiconductor region of the first conductivity type is selectively removed, and polysilicon is removed from the upper surfaces of the field oxide film and the gate oxide film. And a seventh step of etching the deposited polysilicon to form the polysilicon electrode and the gate electrodes of the enhancement type MOS transistor and the depletion type MOS transistor. The method for manufacturing a semiconductor device according to claim 9, further comprising: 11. An eighth step of forming a field oxide film on the semiconductor substrate after the second step, a ninth step of forming an insulating film on the field oxide film, and the field oxidation. Film and the insulating film are selectively removed, and a tenth step of forming a gate oxide film of the depletion type MOS transistor in a region where the field oxide film and the insulating film are selectively removed, and the depletion type MOS transistor 9. The method of manufacturing a semiconductor device according to claim 8, further comprising an eleventh step of performing channel doping through the gate oxide film of. 12. Before the ninth step, the field oxide film on the upper surface of the first-conductivity-type low-concentration semiconductor region is selectively removed, and polysilicon is uniformly applied from the upper surface of the field oxide film. 12. The method according to claim 11, further comprising a twelfth step of depositing, and a thirteenth step of etching the deposited polysilicon to form the polysilicon electrode and the gate electrode of the enhancement type MOS transistor. Of manufacturing a semiconductor device of.