JPH0745517A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To reduce the area of a semiconductor device wherein a bipolar system transistor for analog operation and a logic circuit are formed on the same board, and decrease the number of manufacturing processes of the semiconductor device. CONSTITUTION:An nSIT 2, an E-type nM0S transistor 5 and a D-type nMOS transistor 6 are formed on a P type semiconductor substrate 1. In the manufacturing process of the above semiconductor device, a P<-> type channel layer 14A of the nSIT 2 and P<-> type well regions 14E, 14D of the MOS transistor 5, 6 are formed at the same time, a P<+> type gate region 15A of the nSIT 2 and P<+> type channel stoppers 15F of the MOS transistors 5, 6 are formed at the same time, and a source poly silicon electrode 18A of the nSIT 2 and gate electrodes 18E, 18D of the MOS transistors 5, 6 are formed at the same time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a bipolar transistor and a MOS transistor are formed on the same substrate, and a manufacturing method thereof.

[0002]

2. Description of the Related Art The development of semiconductor technology that supports the electronics industry is remarkable, and it is used in all fields. Further, various developments are being made according to applications such as high power consumption and high speed. Further, in order to meet the demand for miniaturization of various electronic devices, integration of semiconductor devices has been promoted.

FIG. 6 shows a semiconductor in which a bipolar static induction transistor capable of handling a relatively large amount of power and capable of high-speed switching, and a logic circuit for controlling driving of the static induction transistor are formed on the same substrate. Shows the device.

In FIG. 1, the surface portion of the p ^-- type semiconductor substrate 1 is
1 shows a cross section of a semiconductor device in which a bipolar n-type static induction transistor 2 (hereinafter simply referred to as nSIT2), a capacitor 3, and two lateral pnp transistors 4 as logic circuits are formed.

The elements, that is, the nSIT 2, the capacitor 3, and the pnp transistor 4 are electrically isolated from each other by p ⁺ type isolation diffusion regions 11A, 11B, and 11C.

The nSIT 2 has an n ⁺ -type buried layer 12A at the bottom of an n ^-- type epitaxial layer 13A formed on the surface of the p ^-- type semiconductor substrate 1. Then, n ^- the surface portion of the type epitaxial layer 13A, p ^- type channel layer 14, the p ^- on the surface of the mold channel layer 14 ^- so as to surround the mold channel layer 14 p ⁺ -type gate region 15, p An n ⁺ type drain region 17 is selectively formed on the surface of the n ⁺ type source region 16 and the n ⁻ type epitaxial layer 13A at a position spaced apart from the p ⁺ type gate region 15 by a predetermined distance.

Further, the source polysilicon electrode 18 and the n ⁺ type drain region 17 are connected to the n ⁺ type source region 16.
And a drain polysilicon electrode 19 is formed. Further, the source electrode 20 and the drain electrode 2 are connected to the source polysilicon electrode 18, the drain polysilicon electrode 19 and the p ⁺ type gate region 15, respectively.
1 and the gate electrode 22 are formed. The electrodes are insulated from each other by the field oxide film 23 and the interlayer insulating film 24.

The capacitor 3 has an n ⁺ type buried layer 12B at the bottom of an n ⁻ type epitaxial layer 13B formed on the surface of the p ⁻ type semiconductor substrate 1. Then, the p ⁺ type semiconductor region 31 is formed on the surface portion of the n ⁻ type epitaxial layer 13B. In addition, the p ⁺ type semiconductor region 31
An electrode 32 is formed in contact with the vicinity of the end of the surface, and an electrode 34 is formed on the upper surface of the p ⁺ type semiconductor region 31 and above the capacitor oxide film 33 thinner than the field oxide film 23.

The pnp transistor 4 has an n ⁺ type buried layer 12C at the bottom of an n ⁻ type epitaxial layer 13C formed on the surface of the p ⁻ type semiconductor substrate 1. Also,
n ^- type in the surface portion of the epitaxial layer @ 13 C, p ⁺ -type emitter region 41, p ⁺ -type emitter region 41 at a predetermined distance from the p ⁺ -type emitter region 41 so as to surround the p ⁺ -type collector region 42, and p ⁺ type collector region 4
An n ⁺ type base region 43 is formed at a position slightly distant from the outer side of 2. A base polysilicon electrode 44 is formed so as to be connected to the n ⁺ type base region 43, and the p ⁺ type emitter region 41 and the p ⁺ type collector region 4 are further formed.
2, and an emitter electrode 45, a collector electrode 46, and a base electrode 47 are formed so as to be connected to the base polysilicon electrode 44 and the base polysilicon electrode 44, respectively.

As described above, conventionally, when a circuit that performs an analog operation and a logic circuit that performs digital control are formed on the same substrate, the logic circuit is generally composed of bipolar transistors.

[0011]

By the way, in the case of forming a plurality of bipolar transistors on the same substrate, in order to prevent the operation of each bipolar transistor from being influenced by an adjacent bipolar transistor,
It has become common to isolate each bipolar transistor by a reverse biased pn junction. In the example shown in FIG. 6, the potential of the p ⁺ type isolation diffusion region 11C formed between the pnp transistors 4 and 4 is set to be lower than the potential of the n ⁻ type epitaxial layer 13C, so that the pnp transistor 4 is formed. , 4 are separated.

In FIG. 6, only two pnp transistors 4 are shown as lateral type bipolar transistors constituting a logic circuit, but in reality, a large number of them are formed. Therefore, in order to isolate the large number of bipolar transistors, a large number of p ⁺ -type isolation diffusion regions 1 are formed.
1C must be formed.

However, this p ⁺ type isolation diffusion region 11C
Is deeply diffused so as to reach the p ⁻ type semiconductor substrate 1 from the surface of the n ⁻ type epitaxial layer 13C, so that it is inevitably diffused in the lateral direction as well. Therefore, the area of the region formed to separate the bipolar transistors from each other becomes larger than the entire semiconductor device, and the area where an actual element can be formed becomes relatively small, so that the area efficiency of the semiconductor device is improved. There was a problem of being bad.

The present invention solves the above problems,
An object of the present invention is to provide a method for reducing the area of a semiconductor device in which a bipolar transistor and a logic circuit for analog operation are formed on the same substrate and manufacturing the semiconductor device with a smaller number of steps.

[0015]

According to a first aspect of the present invention, a semiconductor device is formed so as to surround a first conductivity type low impurity concentration semiconductor region and the first conductivity type low impurity concentration semiconductor region. Connected to the surfaces of the first conductivity type high impurity concentration semiconductor region and the second conductivity type semiconductor region formed on the surface portion in the first conductivity type low impurity concentration semiconductor region and the surface of the second conductivity type semiconductor region. It is premised that a transistor having a second conductivity type polysilicon electrode and a MOS transistor are formed on the same semiconductor substrate.

The transistor formed with the MOS transistor on the semiconductor substrate is, for example, a static induction transistor (SIT). In this case, the first conductivity type low impurity concentration semiconductor region, the first conductivity type high impurity concentration semiconductor region, the second conductivity type semiconductor region, and the second conductivity type polysilicon electrode are respectively the channel layers of the SIT. , Gate region, source region, and source polysilicon electrode.

Then, the first conductivity type low impurity concentration semiconductor region and the well region of the MOS transistor are formed in the same step, and the first conductivity type high impurity concentration semiconductor region and the channel stopper of the MOS transistor are formed. Are formed in the same process, and the polysilicon electrode and the MOS are formed.
The gate electrode of the transistor is formed in the same step.

A semiconductor device according to a second aspect is the semiconductor device according to the first aspect.
On the premise of the semiconductor device described in 1., the second conductivity type semiconductor region and the source region and the drain region of the MOS transistor are formed in the same step.

A semiconductor device according to a third aspect is the semiconductor device according to the first aspect.
On the premise of the semiconductor device described in 1. above, the well region of the MOS transistor is formed on the surface portion of the second conductive type epitaxial layer formed on the upper surface of the semiconductor substrate, and the well region of the second conductive type is formed below the well region. Form a buried layer.

A semiconductor device according to a fourth aspect is premised on the semiconductor device according to the first, second or third aspect, in which a plurality of the MOS transistors are formed and the plurality of MOS transistors are formed.
The transistors include both enhancement type MOS transistors and depletion type MOS transistors.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein the first conductivity type low impurity concentration semiconductor region and the first conductivity type low impurity concentration semiconductor region are formed so as to surround the first conductivity type low impurity concentration semiconductor region. A second conductivity type semiconductor region formed on a surface portion in the conductivity type high impurity concentration semiconductor region and the first conductivity type low impurity concentration semiconductor region, and a second conductivity type connected to the second conductivity type semiconductor region. It is premised on a method of manufacturing a semiconductor device in which a transistor having a polysilicon electrode and a MOS transistor are formed on the same semiconductor substrate. Further, similar to the semiconductor device according to claim 1, the transistor is, for example, an electrostatic induction transistor (SI).
T).

Then, a first step of forming an epitaxial layer of the second conductivity type on the upper surface of the semiconductor substrate and forming an isolation diffusion region at a predetermined position of the epitaxial layer, and a low impurity concentration of the first conductivity type. A second step of simultaneously forming a semiconductor region and a well region of the MOS transistor; the first conductivity type high impurity concentration semiconductor region;
A third step of simultaneously forming a channel stopper of an OS transistor, a fourth step of forming a gate oxide film of the MOS transistor, and a fifth step of simultaneously forming the polysilicon electrode and the gate electrode of the MOS transistor. Step, the second conductivity type semiconductor region, and the MO
The sixth step of forming a source region and a drain region of the S transistor.

A method of manufacturing a semiconductor device according to a sixth aspect is based on the method of manufacturing a semiconductor device according to the fifth aspect, and the depletion type M is used as the MOS transistor.
When forming an OS transistor, a seventh step of performing channel doping on the surface of the well region below the gate oxide film of the MOS transistor is performed after the fourth step.

[0024]

In the semiconductor device of the present invention, the logic circuit portion formed on the semiconductor substrate together with a transistor (hereinafter referred to as SIT for convenience) that operates in an analog manner such as a static induction transistor is formed of a MOS transistor. To do. At this time, a region for electrically isolating the MOS transistors from each other is unnecessary, and the logic circuit portion can be formed in a small area. Therefore, the chip area of the semiconductor device is reduced.

Further, in the manufacturing method thereof, the channel layer of the SIT and the well region of the MOS transistor are simultaneously formed, the gate region of the SIT and the channel stopper of the MOS transistor are simultaneously formed, and the source polysilicon electrode of the SIT is formed. Since the gate electrode of the MOS transistor is formed at the same time and the source region of the SIT and the source region and the drain region of the MOS transistor are simultaneously formed, the semiconductor device can be manufactured with a small number of steps.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. It should be noted that the areas given the same reference numerals as those in FIG. 6 showing the conventional technique represent the same areas.

In this embodiment, the p ^-- type semiconductor substrate 1 is used.
Above the n-type static induction transistor 2 (hereinafter referred to as nSIT2
, A capacitor 3, an enhancement type n-channel MOS transistor 5 (hereinafter referred to as an E-type nMOS transistor 5), and a depletion type n-channel M.
A semiconductor device having the OS transistor 6 (hereinafter referred to as the D-type nMOS transistor 6) will be described.
However, in the manufacturing process diagrams of FIGS. 1 to 4, only the main part of the nSIT 2, the E-type nMOS transistor 5, and the D-type nMOS transistor 6 are shown in order to make the drawings easy to see.

First, as shown in FIG. 1A, p
N ⁺ type buried layers 12A and 12 are formed on the surface of the ⁻ type semiconductor substrate 1.
An n-type impurity for forming F is selectively introduced, and an n-type impurity having an impurity concentration of about 5 × 10 ¹⁴ to 1 × 10 ¹⁵ is formed on the upper surface thereof.
^- type epitaxial layer 13A, grow 13F.
(The n ⁻ type epitaxial layers 13A and 13F are the same epitaxial layer, but the p ⁺ type isolation diffusion region 11 to be described later is used.
Since it is separated into two regions by A, it is described separately in advance.) Thereafter, the silicon oxide film 71 is uniformly formed on the surfaces of the n ⁻ type epitaxial layers 13A and 13F. Then, the silicon oxide film 71 is selectively removed, and the silicon oxide film 71 is used as a mask to introduce p-type impurities into the surfaces of the n ⁻ -type epitaxial layers 13A and 13F. This p-type impurity is driven in so as to reach the p ⁻ type semiconductor substrate 1 to form the p ⁺ type isolation diffusion region 11A. At the same time, the n type impurities introduced into the surface of the p ⁻ type semiconductor substrate 1 are also diffused to form the n ⁺ type buried layers 12A and 12F. (First Step) Next, as shown in FIG. 1B, after the silicon oxide film 71 is once removed, a silicon oxide film 72 is uniformly formed. Then, the silicon oxide film 72 is selectively removed on the n ⁻ type epitaxial layers 13A and 13F, respectively. Using this silicon oxide film 72 as a mask, a p ⁻ type channel layer 14A is formed on the surface of the n ⁻ type epitaxial layer 13A and a p ⁻ type channel layer 14A is formed on the surface of the n ⁻ type epitaxial layer 13F using a general method. ^- type well region 14D
And 14E are formed. The p ⁻ type channel layer 14A and the p ⁻ type well regions 14D and 14E are formed to a depth of about 2 to 3 μm. (Second Step) Subsequently, as shown in FIG. 1C, the silicon oxide film 73 is formed.
Are formed uniformly, and the position is formed so as to overlap the end of the p ⁻ type channel layer 14A above the n ⁻ type epitaxial layer 13A,
The field oxide film 73 is selectively removed at a position above the n ⁻ type epitaxial layer 13F and near the ends of the p ⁻ type well regions 14D and 14E. Then, using the field oxide film 73 as a mask, p-type impurities are diffused to form the p ⁺ -type gate region 15A and the p ⁺ -type channel stopper 15F with a depth of about 2 to 3 μm. This depth is p ⁻ type channel layer 14A or p ⁻
It is deeper than the depth of the mold well regions 14D and 14E. The p ⁺ type gate region 15A is formed in the surface portion of the n ⁻ type epitaxial layer 13A so as to surround the p ⁻ type channel layer 14A. (Third Step) Although the second and third steps are separated in the above embodiment, the n ⁻ type epitaxial layers 13A and 13 are separated.
A p-type impurity is introduced at a predetermined position on the surface of F at an appropriate concentration, and at the same time when the field oxide film 23 is formed in the next step, the p ⁻ -type channel layer 14A and the p ⁺ -type gate region 15A, And p ^- type well regions 14D, E and p ⁺
The mold channel stopper 15F may be formed.

Next, as shown in FIG. 2A, the n ^-- type epitaxial layers 13A, 13 in which the above-mentioned regions are formed are formed.
A silicon oxide film (field oxide film) 23 is uniformly formed on the surface of F. Then, the field oxide film 23 is selectively removed from the upper portions of the p ⁻ type well region 14E and the p ⁻ type well region 14D. Then, the p ⁻ type well regions 14E and p ⁻ having the field oxide film 23 removed are formed.
The gate oxide film 5 is formed on the surface of the well region 14D.
1 and 61 are formed. (Fourth Step) Subsequently, as shown in FIG. 2B, the field oxide film 2 is formed.
3 and the gate oxide films 51, 61 are uniformly formed with a resist 74, and the field oxide film 23 is selectively removed on the p ⁻ -type channel layer 14A by a general etching method using the resist 74. To do.

Then, as shown in FIG. 2C, a resist 75 is uniformly formed again, and the resist 75 is removed at the upper portion of the p ^-- type well region 14D. After this,
Ion implantation of an n-type impurity (channel doping) is performed using the resist 75 as a mask to form an n-channel 60 on the surface of the p ^- type well region 14D. Here, the acceleration energy of ion implantation is large enough to pass through the gate oxide film 61, and the amount of n-type impurities to be implanted is D-type nM.
It is determined by the characteristics of the OS transistor 6. (7th
Step) If the depletion type MOS transistor is not formed, the seventh step is unnecessary.

Next, as shown in FIG. 3A, on the upper surfaces of the field oxide film 23 and the gate oxide films 51 and 61,
Polysilicon 18 'is uniformly deposited. The method of depositing the polysilicon 18 'is, for example, the CVD method. Since the field oxide film 23 is selectively removed on the p ⁻ type channel layer 14A, the polysilicon 1
8 ′ is directly connected to a part of the surface of the p ⁻ type channel layer 14A. Subsequently, as shown in FIG. 3B, the polysilicon 18 'is selectively removed by etching. By this etching, the source polysilicon electrode 18A connected to the p ⁻ type channel layer 14A, the gate electrode 18E located above the center of the p ⁻ type well region 14E on the surface of the gate oxide film 51, and the gate oxide film 61.
A gate electrode 18D is formed on the upper surface of the p ⁻ type well region 14D near the center thereof. (Fifth Step) Further, in FIG. 3B, after the fifth step,
Ions are implanted into the entire surface with n-type impurities. The ion implantation acceleration energy at this time is such that the n-type impurities can pass through the gate oxide film 51, but cannot pass through the field oxide film 23. Also, the acceleration energy is
The size is such that the n-type impurities after passing through the gate electrode 18E cannot pass through the gate oxide film 51. When n-type impurities are ion-implanted with such acceleration energy,
The n-type impurity that has passed through the source polysilicon electrode 18A is injected into the surface portion of the p ⁻ type channel layer 14A. Further, the n-type impurities that have passed through the gate oxide film 51 are injected into the surface portion of the p ⁻ type well region 14E where the gate electrode 18E is not formed on the surface thereof, and the n-type impurities that have passed through the gate oxide film 61 are Gate electrode 18D is implanted into the surface portion of p ⁻ type well region 14D not formed on the surface thereof. Then, n injected into the surface of each of these regions
By thermally diffusing the type impurities, an n ⁺ type source region 16A is formed on the surface of the p ⁻ type channel layer 14A, and an n ⁺ type source region 16E and an n ⁺ type drain region 16E ′ are formed on the surface of the p ⁻ type well region 14E. , P ⁻ type well region 14
An n ⁺ type source region 16D and an n ⁺ type drain region 16D ′ are formed on the surface of D.

[0032] p ^- n ⁺ -type source region 16A of the surface of the mold channel layer 14A is, p ^- the p ⁺ -type gate region 15A, which is formed so as to surround the mold channel layer 14A, at a 1~2μm It is formed. This is shown in FIG.
In (b), it can be realized by appropriately designing the mask shape for selectively removing the field oxide film 23 on the p ⁻ type channel layer 14A. (Sixth Step) The source polysilicon electrode 18A, the gate electrode 18E, and the gate electrode 18 are formed by the ion implantation.
Since a large amount of n-type impurities are injected into D, each has an appropriate resistance value as an electrode.

Further, as shown in FIG. 4, the formation of the n ⁺ type source region 16A may be performed in a separate step from the formation of the n ⁺ type source regions 16E and 16D and the n ⁺ type drain regions 16E 'and 16D'. . In the example of the figure, n ⁺ type source region 1
6A is formed first, and the SIT side on which the n ⁺ type source region 16A is formed is protected by a resist 76, and then the n ⁺ type source regions 16E and 16D and the n ⁺ type drain regions 16E ′ and 16D ′ are formed on the MOS side. Ion implantation for forming is performed. The order of formation may be reversed.

As described above, the manufacturing process in which the ion implantation is performed in two steps is performed when it is necessary to perform different ion implantation acceleration energies on the SIT side and the MOS side.

After the step of FIG. 3B or FIG.
As shown in (c), an interlayer insulating film 24 such as PSG is uniformly formed. Then, the source polysilicon electrode 18A
Of the p ⁺ -type gate region 15A, the n ⁺ -type source regions 16E and 16D, and the n ⁺ -type drain regions 16E 'and 16D'. The oxide films 51 and 61 are selectively removed.

After this, as shown in FIG. 5, electrodes are formed of aluminum or aluminum-silicon, respectively, connected to the corresponding regions. That is, the source electrode 20 is connected to the source polysilicon electrode 18A.
Is formed. In addition, n ⁺ type source regions 16E and n
Connected to the ⁺ type drain region 16E ', each of the E type n
The source electrode 52 and the drain electrode 53 of the MOS transistor 5 are formed, and the n ⁺ type source regions 16D and n are formed.
Connected to the ⁺ -type drain region 16D ', each of the D-type n
The source electrode 62 and the drain electrode 63 of the MOS transistor 6 are formed.

Next, a description will be given of the parts of the manufacturing process diagrams of FIGS. The n ⁺ drain region 17 of the nSIT2 is formed simultaneously with the n ⁺ type source region 16A in the sixth step. In addition, the n ⁺ drain region 17
The drain polysilicon electrode 19 connected to the
In the step of, the source polysilicon electrode 18A is formed at the same time. Then, the drain electrode 21 is formed by connecting to the drain polysilicon electrode 19.

The p ⁺ type semiconductor region 31 of the capacitor 3 is
In the third step, it is formed simultaneously with the p ⁺ type gate region 15A of nSIT2. Further, the capacitor oxide film 33 is formed simultaneously with the gate oxide film 51 of the E-type nMOS transistor 5 in the fourth step. Further, the polysilicon electrode 35 on the capacitor oxide film 33 is formed at the same time as the source polysilicon electrode 18A of nSIT2 in the fifth step. Then, an electrode 36 is formed by connecting to the polysilicon electrode 35, and p ⁺
An electrode 32 is formed in contact with the surface of the type semiconductor region 31.

NSIT2 formed as described above
It is, n is shown as an example ^- in response to the impurity concentration of the type epitaxial layer 13A, the distance between the depth and the p ⁺ -type gate region 15A and the n ⁺ -type source region 16A of p ⁺ -type gate region 15A is designed It Then, by forming the structure shown in the above embodiment, the characteristics of the SIT can be obtained while performing the bipolar operation. That is, the amplification factor is improved by forming the impurity concentration of the p ⁻ type channel layer 14A lower than the impurity concentration of the base region of a normal bipolar transistor. In general, p
^If the impurity concentration of the ⁻ type channel layer 14A is lowered, punch-through easily occurs between the source and the drain, and the breakdown voltage decreases. However, the nSI of the above structure
At T2, the p ⁻ type channel layer 14A is formed so as to surround the p ⁻ type channel layer 14A and deeper than the p ⁻ type channel layer 14A (in the cross-sectional view of FIG. 5, the p ⁻ type channel layer 14A is formed).
The depletion layers extending from the p ⁺ -type gate region 15A (formed on the left and right sides of each other) reach each other to secure the above breakdown voltage.

In the semiconductor device shown in this embodiment,
Since the formation of the nSIT 2 having the above characteristics and the formation of the E-type nMOS transistor 5 and the D-type nMOS transistor 6 are performed in the same steps as much as possible, manufacturing can be performed with a small number of steps.

Further, n E-type nMOS transistor 5 and the D-type nMOS transistor 6 is formed ^- but connected to the lower -type epitaxial layer 13F n ⁺ -type buried layer 12F is formed, the n ⁺ -type Buried layer 12F
Prevents the depletion layer extending from the p ⁻ type well region 14E or 14D from reaching the p ⁻ type semiconductor substrate 1 and punching through the p ⁻ type well region 14E or 14D, and the p ⁻ type semiconductor substrate 1, the n ⁻ type epitaxial layer 13F, and the p ⁻ type semiconductor substrate 1. The parasitic pnp transistor formed of the type well region 14E or 14D is prevented from being turned on.

As described above, in the above embodiment, the n-type SIT is used.
Although the n-channel MOS transistor and the n-channel MOS transistor are formed on the same semiconductor substrate, the present invention is not limited to this, and is applicable to the case where the p-type SIT and the p-channel MOS transistor are formed on the same semiconductor substrate. Is.

[0043]

According to the present invention, when a transistor and a logic circuit for analog operation are formed on the same semiconductor substrate, the transistor constituting the logic circuit is constituted by a MOS transistor, so that the chip area is reduced. to shrink.

Further, since the formation of the transistor for performing the analog operation and the formation of the MOS transistor are made common in many steps, the number of manufacturing steps is reduced.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram (1) for explaining an embodiment of a semiconductor device of the present invention.

FIG. 2 is a manufacturing process diagram (2) for explaining an embodiment of a semiconductor device of the present invention.

FIG. 3 is a manufacturing process diagram (3) for explaining an embodiment of the semiconductor device of the invention.

FIG. 4 is a manufacturing process diagram illustrating a step in the case where the ion implantation step is performed in two steps in FIG.

FIG. 5 is a cross-sectional view of an embodiment of the semiconductor device of the present invention formed by the manufacturing process shown in FIGS.

FIG. 6 is a cross-sectional view of a semiconductor device, which is an example of a conventional semiconductor device, in which a static induction transistor and a lateral pnp transistor are formed on the same semiconductor substrate.

[Explanation of symbols]

1 p ⁻ type semiconductor substrate 2 n type static induction transistor (nSIT) 3 capacitor 5 enhancement type n channel MOS transistor (E type nMOS transistor) 6 depletion type n channel MOS transistor (D type nMOS transistor) 11A, B p ⁺ type Isolation diffusion region 12A, F n ⁺ type buried layer 13A, F n ⁻ type epitaxial layer 14A p ⁻ type channel layer 14E, D p ⁻ type well region 15A p ⁺ type gate region 15F p ⁺ type channel stopper 16A n ⁺ type source Region 16E, D n ⁺ type source region 16E ', D'n ⁺ type drain region 18A Source polysilicon electrode 18E, D Gate electrode 51, 61 Gate oxide film 60 n Channel

Claims (6)

[Claims] 1. A first conductivity type low impurity concentration semiconductor region and a first conductivity type high impurity concentration semiconductor region formed so as to surround the first conductivity type low impurity concentration semiconductor region and the first conductivity type. And a MOS transistor having a second conductivity type semiconductor region formed on the surface of the low impurity concentration semiconductor region and a second conductivity type polysilicon electrode connected to the surface of the second conductivity type semiconductor region. A low-impurity-concentration semiconductor region of the first conductivity type and the MO device.
The well region of the S transistor is formed in the same step, and the high-concentration semiconductor region of the first conductivity type and the MO region are formed.
A semiconductor device, wherein a channel stopper of an S transistor is formed in the same step, and the polysilicon electrode and a gate electrode of the MOS transistor are formed in the same step. 2. A semiconductor region of the second conductivity type and the M
The semiconductor device according to claim 1, wherein the source region and the drain region of the OS transistor are formed in the same step. 3. A second layer formed on the upper surface of the semiconductor substrate.
2. The semiconductor device according to claim 1, wherein a well region of the MOS transistor is formed on a surface portion of a conductive type epitaxial layer, and a second conductive type buried layer is formed below the well region. 4. The plurality of MOS transistors are formed, and the plurality of MOS transistors include both enhancement type MOS transistors and depletion type MOS transistors.
Or the semiconductor device according to 3. 5. A low-impurity concentration semiconductor region of the first conductivity type and a high-impurity concentration semiconductor region of the first conductivity type formed so as to surround the low-impurity concentration semiconductor region of the first conductivity type and the first conductivity type. And a MOS transistor having a second conductivity type semiconductor region formed on the surface of the low impurity concentration semiconductor region and a second conductivity type polysilicon electrode connected to the second conductivity type semiconductor region. In a method of manufacturing a semiconductor device formed on the same semiconductor substrate, a first step of forming an epitaxial layer of a second conductivity type on an upper surface of the semiconductor substrate and forming an isolation diffusion region at a predetermined position of the epitaxial layer, The first conductivity type low impurity concentration semiconductor region and the MOS
A second step of simultaneously forming a well region of a transistor, the first conductivity type high impurity concentration semiconductor region, and the MOS
A third step of simultaneously forming a channel stopper of the transistor, and a fourth step of forming the gate oxide film of the MOS transistor.
The fifth step of simultaneously forming the polysilicon electrode and the gate electrode of the MOS transistor, and the sixth step of forming the semiconductor region of the second conductivity type and the source and drain regions of the MOS transistor. A method of manufacturing a semiconductor device, comprising: 6. When a depletion type MOS transistor is formed as the MOS transistor, a seventh step of performing channel doping on the surface of the well region below the gate oxide film of the MOS transistor is performed. The method for manufacturing a semiconductor device according to claim 5, wherein the method is performed after the step.