JPS60187048A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable to constitute a capacitor of relatively large capacity without increasing the size of a chip by a method wherein the junction capacitance between a substrate and the buried layer of conductive type different from that of the substrate is properly utilized. CONSTITUTION:An N<+> buried layer 2 is partially formed on a P type semiconductor substrate 1, and an N<+> epitaxial layer 3 is formed thereon. Then, a U- groove is formed in such a manner that it penetrates the layers 2 and 3, and an insulating film 5 is formed inside the U-groove, and a U-groove isolation region 8 is provided by filling poly silicon in the U-groove. Also, an N<+> region 11 to be turned to the pulling-up hole of the layer 2 is formed at one end of the layer 2, and a P<+> region 10 to be turned to the pulling-up hole of the substrate 1 surrounded by the region 8 is formed at an arbitrary position on the substrate 1 which is separated a little from the layer 2. Electrodes 4a and 4b are formed on pulling-up holes 10 and 11, and the junction capacitance which is parasitic between the layer 2 and the substrate 1 is properly utilized as the bypass capacitor of an internal source circuit. As a result, the bypass capacitor can be constituted without increasing the chip size.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to semiconductor technology, and, for example, to a technology effective for use in forming capacitors in semiconductor integrated circuits.

[Background Art] Figure 1: ECL consisting of a current inch circuit C8, a reference voltage generation circuit VG, and an emitter follower EF.
An example of a (emitter coupled logic) circuit is shown.

In this ECL circuit, current switch circuit C8
When the frequency of the input signal Vin applied to the base of the differential type transistor Q1 constituting the circuit increases, the other one-herald transistor Q2, to which the reference voltage vbb supplied from the reference voltage generation circuit VG is applied, receives the input signal V. It becomes impossible to respond to changes in in. Therefore, the input signal V i
When n changes, a large base current may suddenly flow through transistor Q2. In this case, if the reference voltage generation circuit VG is an ideal power supply, the impedance is considered to be zero, so a large base current can be sufficiently and quickly supplied to the transistor Q2.
This does not cause the reference voltage vbb to fluctuate.

However, in an actual ECL circuit implemented as a semiconductor integrated circuit, the reference voltage generation circuit VG is not an ideal power source;
It has a certain finite value of impedance. Therefore,
There is a drawback that the reference voltage vbb fluctuates and the logic threshold of the ECL circuit changes because it cannot follow sudden changes in current. In this case, as shown by the broken line in FIG. 1, by connecting a bypass capacitor cb between the output node nO of the reference voltage generation circuit VG and the power supply voltage vEE, the impedance of the reference voltage generation circuit VG can be lowered. The reference voltage vbb can be stabilized by being able to follow rapid fluctuations in the base current of the transistor Q2.

By the way, as described above, the larger the capacitance of the bypass capacitor Cb connected to the output node of the reference voltage generation circuit VG, the lower the impedance of the power supply. However, as is well known, in semiconductor integrated circuits, it is difficult to fabricate a large capacitance capacitor on a chip, resulting in an increase in chip size.

[Object of the Invention] An object of the present invention is to provide a semiconductor technology that allows a capacitor of relatively large capacity to be formed in a semiconductor integrated circuit without increasing the chip size.

Another object of the present invention is to provide a technique that allows the junction capacitance of a diffusion layer to be effectively used as a capacitor.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

In other words, the present invention makes it possible to configure a capacitor with a relatively large capacitance without increasing the chip size by utilizing the junction capacitance between the N+ buried layer and the substrate. By arranging a pull-up port for pulling up the substrate and the substrate onto the main surface of the substrate, and electrodes connected to the pull-up ports in pairs at the same location on the substrate, the gap between the N+ buried layer and the substrate is reduced. By reducing the equivalent resistance connected in series with the junction capacitance of
This achieves the above object of making it possible to effectively utilize junction capacitance as a capacitor.

[Embodiment 1] FIG. 2 shows a first embodiment in which the present invention is applied to a bipolar integrated circuit.

In this embodiment, although not particularly limited, an N+ buried Wj2 is partially formed on a semiconductor substrate 1 made of P-type silicon, and an N- epitaxial layer 3 is formed thereon. In this case, the N0 buried layer 2 is formed by forming an oxide film on the semiconductor substrate 1, for example, and then drilling holes in the buried diffusion pattern at appropriate positions of the oxide film, and using the oxide film as a mask. It is formed by selectively thermally diffusing N-type impurities. Further, the N- epitaxial layer 3 is formed by vapor phase growth over the entire surface of the substrate 1 after removing the oxide film that served as a mask for forming the N+ buried WJ2.

Then, an oxide film, a nitride film, etc. are formed on the surface of the N-epitaxial layer 3, and using this as a mask, a U-groove is formed that penetrates the N-epitaxial layer 3 and the N-buried layer 2. After forming an insulating film 5 such as an oxide film on the inside of the
A U-groove isolation region 8 is provided by filling the trench 6 and forming an oxide film 7 on its surface.

Although not particularly limited, in this embodiment, aluminum wirings 9a, 9b, 9c...
The N+ buried layer 2 is formed in advance below the wiring region 9 in which .
An N+ region 11, which serves as a pull-up port for the N+ buried layer 2, is formed at one end.

Although not particularly limited, this N+ region 11 is formed at the same time as the formation of an N+ diffusion layer which becomes a collector pull-up port of a bipolar transistor (not shown).

Furthermore, a P+ region 10, which is surrounded by the U-groove isolation region δ and serves as a substrate pull-out port, is formed at an arbitrary position on the substrate slightly apart from the N+ buried layer 2 under the wiring region. This P+ region 10 is formed, for example, by performing ion implantation and thermal diffusion after the formation of the N- type epitaxial layer 3 and before the formation of the U-groove isolation region 8, although this is not particularly limited.

Wires 9a, 9 are connected to each pull-up port 11 and lO.
b, . . . simultaneously, aluminum electrodes 4a and 4b are formed. These electrodes 4a and 4b are connected to an output node n0 and a power supply voltage Vk and 9 of an internal power supply circuit such as a reference voltage generation circuit VG as shown in FIG. 1 through aluminum wiring. .

That is, in this embodiment, the parasitic junction capacitance between the N+ buried layer 2 under the wiring region and the substrate 1 is used as a bypass capacitor for the internal power supply circuit. Therefore, according to this embodiment, the bypass capacitor cb can be configured without increasing the chip size.

However, in a capacitor that utilizes the junction capacitance between the N+ buried layer 2 and the substrate 1, as shown in FIG. 1
1 and the pull-up port 10 of the substrate 1 are formed at locations apart from each other, and when the capacitors 4@4a and 4b of the bypass capacitor cb are formed in each pull-up port 11 and 10, respectively, the sheet of the substrate ① and the N+ buried layer 2 is formed. Depending on the resistance, the junction capacitance (
A resistor is isometrically connected in series with the bypass capacitor (bypass capacitor). Therefore, there is a disadvantage that the equivalent resistance connected in series with the junction capacitance reduces the effectiveness of the bypass capacitor. Therefore, an embodiment that solves this problem will be described next.

[Embodiment 2] A second embodiment of the present invention is shown in FIGS. 3 and 4.

In this embodiment, an N+ buried layer 2 is formed in advance in a region where a capacitor is to be formed, and the U-groove isolation region 8 is formed so as to penetrate through this N+ buried layer 2.
This is similar to the embodiment. In this embodiment, the U-groove isolation region 8 is formed in an annular shape, and an N+ buried layer 2 is provided in the N- epitaxial layer surrounded by the annular U-groove isolation region 8 and separated from the surrounding epitaxial layer 3. An N+ region 11 that serves as a pull-up port for the N+ buried layer 2 is formed so as to reach . As in the previous embodiment, this N+ region 11 is formed by diffusion of N-type impurities simultaneously with the formation of the collector pull-up port.

Although not particularly limited, an N-type impurity is further implanted into the surface of the N″′ region 11, which serves as a pull-up port for the N+ buried layer 2, by an N-type impurity diffusion process for forming an emitter region, and the concentration is increased. It's expensive.

In addition, in this embodiment, a P
A region 10 is formed. This p-L region lO is
As in the embodiment described above, for example, after the formation of the N-type epitaxial layer 3 and before the formation of the U-groove isolation region 8, it is formed by ion implantation and thermal diffusion.

The surface of the base region 11 surrounded by the U-groove isolation region 8 and the P+ region 10 outside the U-groove isolation region 8
Aluminum electrodes 4a and 4b that serve as terminals of the capacitor are on the surface of the
is formed and connected to a desired element region of a circuit (not shown) via aluminum wiring.

As a result, as shown in FIG. 4, a rectangular aluminum electrode 4a is formed on the pull-up port (11) of the N+ buried layer 2, and an annular aluminum electrode 4b is formed to surround this. A part of the annular aluminum electrode 4b is cut, and this cut portion 14
An aluminum wiring 14a for connecting the aluminum electrode 4a inside the aluminum wiring 4b to other elements is drawn out from the aluminum wiring 4b.

Then, the junction capacitance between the N-1 buried layer 2 surrounded by the U-groove isolation region 8 and the substrate 1 is used, for example, as a bypass capacitor cb in a reference voltage generation circuit VG as shown in FIG. be made into According to such a configuration, N
+ Connect the pull-out opening (11) of the buried layer 2 to the pull-out opening (11) of the board 1 (
10) are provided close to each other so as to take in the aluminum electrodes 4a and 4b, so that the value of the equivalent resistance connected in series with the junction capacitance between the aluminum electrodes 4a and 4b decreases. This prevents the series resistance from reducing the effectiveness of the junction capacitor as a capacitor.
A very pure capacitor is obtained.

As a result, the above-mentioned junction capacitance increases when the bypass capacitor cb in the reference voltage generation circuit VG as shown in FIG.
When used as a reference voltage generating circuit, the impedance of the reference voltage generating circuit can be effectively lowered, and fluctuations in the reference voltage vbb due to changes in the input signal can be suppressed.

Note that, although not particularly limited in the above embodiment, a U-groove isolation region 18 is also provided around the P+ region 10 that serves as the pulling port of the substrate 1.
is provided and separated from the wiring area and element area. However, N-1-J! l! Closing layer 2 opening (11)
The U-groove isolation region 8 between the substrate 1 and the pull-up port (1o) of the substrate 1 and the U-groove isolation region 18 outside the P+ region 10 do not necessarily have to be provided, and can be omitted in relation to the process.

Further, in the above embodiment, as shown in FIG. 3, the pull-up port (11) of the N+ buried layer 2 and its electrode 4a are arranged inside the pull-up port (Ho) and electrode 4b of the substrate 1 which are formed in an annular shape. However, the present invention is not limited to this, and for example, as shown in FIG. Alternatively, as shown in FIG. 5(B), a structure in which rectangular electrodes 4a and 4b are simply arranged side by side may be used.

[Embodiment 3] Figure 6 shows that the present invention was applied to a bipolar transistor formed on a semiconductor substrate, with parasitic capacitance 0 between the collector and the substrate.
In this example, a U-groove isolation region 8 is formed around a transistor Q formed for measuring the collector capacitance C1s. A P+ region 10, which serves as a pull-up port for the substrate 1, is formed in an annular shape around the P+ region 10 so as to surround it. Aluminum electrodes 4a and 4b are formed on the surface of this I]4' region IO and on the surface of N+ region 21, which serves as a collector pull-up port, respectively. In addition,
In the figure, 22 is P, which is the base region of the transistor.
The type diffusion layer 23 is an N type diffusion layer which becomes an emitter region.

According to this embodiment, since the opening (10) of the substrate 1 is formed around the transistor Q formed for collector capacitance measurement, measurement probes are applied to the electrodes 4c and 4b, respectively. , when measuring the collector capacitance CTs, the resistance of the substrate 1 connected in series with the collector capacitance CT3 becomes smaller. Therefore, only the pure collector capacitance CTs can be directly measured, and the 41 measurement error is reduced.

In other words, conventionally, substrate pulling ports are formed at multiple appropriate locations on the main surface of a semiconductor substrate on which a semiconductor integrated circuit is formed, and these arbitrarily formed substrate pulling ports can be used. The collector capacitance Co8 was measured. Therefore, the pull-up port of the substrate used for measurement is often located far from the measurement element, and as a result, the resistance of the substrate connected in series with the collector capacitance Crs becomes large, resulting in a large measurement error. However, by applying this embodiment, the equivalent series resistance is reduced, which has the effect of reducing measurement errors.

[Effects] (1) Since the junction capacitance between the N+ buried layer and the substrate is used as a capacitor, the chip size can be reduced by providing a capacitor electrode with a relatively small area on the substrate. There is an effect that a capacitor with a relatively large capacity can be formed within the semiconductor substrate without increasing the capacitance.

(2) A pull-up port that pulls up the N+ buried layer and the substrate to the main surface of the board, and electrodes that are respectively connected to the pull-up ports are arranged in pairs at the same location on the board. Therefore, since the equivalent resistance connected in series with respect to the junction capacitance between the N+ buried layer and the substrate is reduced, the junction capacitance can be effectively used as a capacitor.

(3) A pull-up port for lifting the N+ buried layer and the substrate onto the main surface of the substrate, and an electrode connected to each pull-up port are arranged at the same location on the board so as to form a pair with each other. , by reducing the equivalent resistance connected in series with the junction capacitance between the N+ buried layer and the substrate, when this junction capacitance is used as a bypass capacitor in a power supply circuit such as a reference voltage generation circuit. Another advantage is that the impedance of the power supply circuit is reduced and voltage fluctuations are reduced.

(4) Since the substrate pull-up port is provided around the transistor provided for measuring the collector capacitance, etc., the equivalent resistance connected in series with the collector capacitance is reduced. This has the effect of reducing measurement errors such as capacitance.

Hereinafter, the invention made by the present inventor has been specifically explained based on examples, but the present invention is not limited to the above examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say. For example, in the above embodiment, the N+ buried layer pull-up port and the substrate pull-up port are separated by the U-groove isolation region, but instead of the U-groove isolation region, a field oxide film using isoplanar technology or
-〇They may be separated by an insulating film such as CO8.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to bipolar integrated circuits, which is the field of application that formed the background of the invention, but the invention is not limited thereto. It can be used in all semiconductor integrated circuit devices that require capacitors.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of an ECL circuit to which the present invention is applied, and FIG. 2 is a circuit diagram showing an example of an ECL circuit to which the present invention is applied. FIG. 3 is a sectional view of main parts showing an embodiment of the present invention, and FIG. 3 is a sectional view taken along line ■-■ in FIG. 4, and FIG. 4 is a layout of capacitor electrodes. 5(A) and 5(B) are planar explanatory views showing another example of the layout of capacitor electrodes; FIG. 6 is an explanatory plan view showing an example of the layout of a capacitor electrode; FIG. 6 is an explanatory plan view showing an example of the layout of a capacitor electrode; FIG. 3 is a sectional view showing an example of the case. C8... Karen 1-switch circuit, VG... Power supply circuit (reference voltage generation circuit), EF... Emitter follower, Ql, Q2... Differential transistor, vbb
...J4% r (14 voltage, 1... semiconductor planting board, 2... N+ buried layer, 3... N- type epitaxial shop, 4'a, 4b... Capacitor electrode, 4c・
...TJL/Kuta electrode, 5...Insulating film, 6...
・Polysilicon, 7... Oxide film, 8, 18...
U groove separation area, 10...P+ area (substrate pull-up port)
, 11...N''-area (N0 buried layer pull-up port), 1
4a... Aluminum wiring, 14b... Cutting part, 21
...N10 area (collector pull-up port), 22...
P-type diffusion layer (base region), 23...N-type diffusion layer (
emitter region), Q... measurement transistor, cl
s...Collector capacity. Figure 1 Figure 3 Figure 4

Claims (1)

[Claims] 1. A buried layer of a conductivity type different from that of the semiconductor substrate is partially formed on a semiconductor substrate, an epitaxial layer is formed on the buried layer, and a circuit is formed on the main surface of this epitaxial layer. In a semiconductor device in which an element is formed,
A pull-up port is provided to pull up the buried layer and the substrate above the main surface of the epitaxial layer, and electrodes are formed in each of the pull-up ports, so that the junction capacitance between the buried layer and the substrate can be increased to A semiconductor device characterized in that it is used as a constituting capacitor. 2. Claim 1, characterized in that the pulling ports of the buried layer and the substrate, and the electrodes connected to the pulling ports are formed in pairs at the same location on the substrate. The semiconductor device described. 3. The junction capacitance between the buried layer and the substrate is used as a bypass capacitor of a power supply circuit configured on the main surface of the semiconductor substrate. The semiconductor device according to item 2.