JPH0258367A - Semiconductor device - Google Patents

Abstract

PURPOSE:To decrease fluctuation of resistance values in polysilicon resistance so as to avoid generation of operation failure, etc., to improve reliability by thinning an isolation film partially and providing resistance at this thinned part. CONSTITUTION:An isolation film 2 consisting of SiO2 to isolate a bipolar transistor 1 from other circuit elements and an active region inside the bipolar transistor 1 from a collector pullingup part is partially made thin, and polysilicon resistance 3 is formed at that thinned part. By the action that the heat resistance of the isolation film 2 below the polysilicon resistance 3 becomes small, the temperature rise of the polysilicon resistance 2 on the isolation film 2 becomes small as compared with a conventional one. As a result, the fluctuation of resistance values at the polysilicon resistance 2 becomes small, and generation of operation failure of a circuit, etc., is avoided, and in return, a semiconductor device high in reliability can be made.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a technique that is effective when applied to forming a resistor on an isolation film.

[Prior Art] Conventionally, a diffused resistor has been used as a resistor in a semiconductor integrated circuit. However, in the case of a diffused resistor, it is necessary to separate the diffused resistor forming region by LOGO 8 or the like, and in this case, there is a problem in that a large margin must be provided for the diffused resistor forming region in anticipation of the occurrence of bird's beak. Therefore.

In today's world where semiconductor integrated circuits are required to be highly integrated and miniaturized, polysilicon resistors are increasingly being adopted in place of conventional diffused resistors. In addition, in that case.

A polysilicon resistor is usually formed on an isolation oxide film (SiO2 film) to reduce the capacitance to the substrate.

A semiconductor integrated circuit device having a polysilicon resistor as described above is described in, for example, Japanese Patent Laid-Open No. 11644/1983.

[Problem to be solved by the invention] However, since the isolation oxide film (Sin film) has a thermal conductivity of 1.9 W/m"c and has poor thermal conductivity, polysilicon The temperature of the isolation film under the resistor increases.

As a result, the resistance value of the polysilicon resistor on the isolation film fluctuates, resulting in a problem that one-circuit current no longer flows or one-circuit current deviates from the designed value.

The present invention has been made in view of this point, and an object of the present invention is to provide a highly reliable semiconductor device.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

In the semiconductor device of the present invention, the isolation film is partially thinned and a resistor is provided in the thinned portion.

[Function] According to the above-mentioned means, the isolation film is made thinner and a resistance is provided in this thinner portion, so that the thermal resistance of the isolation film becomes smaller than that of the conventional method. The temperature rise of the resistance on the isolation film can be suppressed to a smaller level than in the past. the result.

Fluctuations in the resistance value of the resistor are reduced, the occurrence of malfunctions, etc. is avoided, and a highly reliable semiconductor device can be realized.

[Example] Hereinafter, an example of a semiconductor device according to the present invention will be described based on the drawings.

1 and 3 show an embodiment of a semiconductor device according to the present invention.

In FIG. 1, the reference numeral 1 represents an NPN bipolar transistor, and the reference numeral 2 represents an S i O transistor for separating the bipolar transistor 1 from other circuit elements, and the active region and collector pull-up portion within the bipolar transistor 1.
, this isolation film 2 is partially made thin, and a polysilicon resistor 3 is formed in the thinned part.

Next, details of the structure of the semiconductor device shown in FIG. 1 will be explained together with its manufacturing method.

First, an N+ type buried layer 5 is partially formed on a P type silicon substrate 4.
An N-type epitaxial layer 6 is formed over the entire surface of the silicon substrate 4 on which the buried layer 5 is formed. continue,
An oxide film (SiO8 film) 7 and a nitride film (Si, N4 film) 8 are formed on the epitaxial layer M6 in a region other than the active region and collector pull-up portion of the bipolar transistor 1.
Next, after forming an oxide film 9 of about 500 layers on the substrate surface, boron ions are implanted using the photoresist 10 as a mask to form a P1 type channel stopper region 11. Thereafter, the photoresist 10 serving as a mask is removed, and an isolation film (S i O film) 12 is further formed by thermal oxidation. Next, the area where the resistor is to be formed in the isolation film 12 is shaved until the substrate surface is exposed, and after the photoresist 10 is removed, a deformed oxide film 13 of about 500 layers is formed in the area where the isolation film 2 has been scraped. Then, for example, phosphorus is ion-implanted into the region where the resistor is to be formed through the oxide film 13 to form an N+ type semiconductor region 14, and annealing is performed.
As a result, phosphorus in the N+ type semiconductor region 14 is diffused and N
The + type semiconductor region 14 changes to an N- type semiconductor region. Next, thermal oxidation is performed to form an isolation film 12 (for convenience) in a region where a resistor is to be formed.

(The same reference numerals as the above-mentioned isolation eye film are used) have a thickness of about 0.3 to 0.7 μm. after that.

After depositing polysilicon 3, selective etching is performed to form polysilicon resistor 3. Thereafter, a base region 16 and an emitter region 17 of transistor 1 are formed in one conventional process. Note that in FIGS. 1 and 3, reference numerals 18, 19, and 20 represent a base electrode, an emitter electrode, and a collector electrode, respectively. Further, reference numeral 21 represents an AI2 electrode that contacts the polysilicon resistor 3.

It goes without saying that the manufacturing order does not have to be the above order.

According to the semiconductor device configured as described above, the following effects can be obtained.

That is, according to the semiconductor device of the above embodiment, the isolation film 2 is made thinner and the polysilicon resistor 3 is provided on the thinned portion, so that the lower isolator of the polysilicon resistor 3 is Due to the effect that the thermal resistance of the isolation film 2 becomes smaller, the isolation film 2
The temperature rise in the upper polysilicon resistor 3 is smaller than in the conventional case.

As a result, fluctuations in the resistance value of the polysilicon resistor 2 are reduced, and malfunction of one circuit can be avoided, and a highly reliable semiconductor device can be realized.

A concrete explanation of this is as follows.

Now, assuming that the thickness of the isolation film is t, the width of the polysilicon resistor is W, and the length of the polysilicon resistor is L, the thermal resistance R is expressed by the following equation.

Here, to take an example of a conventional semiconductor device, the thickness L of the isolation film is 1 μm, and the width W of the polysilicon resistor is
is 5 μm, the length of the polysilicon resistor is 20 pm, and the thermal conductivity of SiO2 used as the isolation film 12 is 1.9 W/m°C, so the thermal resistance R of the isolation film is 5263°C/ It becomes W.

On the other hand, if the current I flowing through the resistor is 15 mA and the resistance R1 of the polysilicon resistor is 400 Ω, the power P (= zR1)
is 90mW and the temperature rise ΔT (=PXR) is 474℃
becomes.

In contrast, in the semiconductor device of this embodiment.

If the thickness t of the isolation film is, for example, 0.5 μm, the thermal resistance R' of the isolation film 3 will be 1/2 of the thermal resistance R of the conventional semiconductor device, and as a result, the temperature increase T will be 237°C. Become.

When the isolation membrane is used in this way.

This means that the temperature rise of the polysilicon resistor 3 can be significantly reduced.

Further, according to the semiconductor device of the above embodiment, since the PN junction capacitor is formed below the isolation film 2, an increase in capacitance when the isolation film 2 is made thinner can be avoided.

That is, the insulating film capacitance C is expressed by the following equation, where the dielectric constant is ε, the dielectric constant of the isolation film (Sin) is E, and the thickness of the isolation film is t.

c= E・X'・ Here, the permittivity of vacuum is ε. is 8.86 x 10-14F
/a11. Since the specific If ratio ε1 of SiO□ is 3.9 and the thickness of conventional Sio2 is 1 μm, the conventional insulating film capacitance C is as follows.

=0.0346 fF/μm" On the other hand, in the insulating film capacitance C1 of the semiconductor device of this embodiment, the thickness of the isolation film 3 is 1/2 that of the conventional one (0,
5 μm), which is twice that of the conventional method, or 0.0692 f
F/pm".

In this way, if only the insulating film capacitance is considered, the capacitance will be twice that of the conventional one, but in the semiconductor device of the embodiment, a PN junction is formed under the isolation film 2. Therefore, the state is the same as when the insulating film capacitor C1 and the PN junction capacitor C2 described below are connected in series as shown in FIG.

In this case, the PN junction capacitance C2 is: q: charge per electron, E6 + dielectric constant, E2 = specific inductivity of silicon, φ: built-in potential V, NA: acceptor impurity concentration, Nn: donor impurity concentration. expressed.

Here, the charge amount q of one electron is 1.6X]O-'' coulombs, and the 1ffi rate E0 is 8.86X10-14F/c+n.

The dielectric constant ε2 of silicon is 11.7, and the built-in potential φ
If it is 0.8V, the acceptor impurity a degree NA is 1015, and the donor impurity 1 degree No is 1017.

The PN junction capacitance nc is 0.1 fF/μm.

Therefore, the total capacitance C' is expressed as follows, so by substituting the above C1 and C2, the total capacitance ic' becomes 0.041 F/)tm''.

Therefore, the overall capacitance can be suppressed to approximately the same level as the conventional parasitic capacitance.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In the semiconductor device of the present invention, the isolation film is partially thinned and a polysilicon resistor is provided in this thinned part, so that the thermal resistance of the isolation film is reduced, and the polysilicon resistor on the isolation film is The temperature rise of the resistor can be suppressed to a smaller level than in the past. As a result, fluctuations in the resistance value of the polysilicon resistor are reduced, malfunctions, etc. can be avoided, and a highly reliable semiconductor device can be realized.

Furthermore, if a PN junction is formed under the isolation film, the insulating film capacitance and the PN junction capacitance will be connected in series, suppressing the increase in capacitance due to the thinning of the isolation film. be able to.

[Brief explanation of the drawing]

FIG. 1 is a vertical cross-sectional view of an embodiment of the semiconductor device according to the present invention, FIGS. 2(A) to (D) are vertical cross-sectional views showing the manufacturing method of the semiconductor device of FIG. 1 in order of steps, and FIG. FIG. 2 is a plan view showing the layout of the semiconductor device of FIG. 1; 2...Isolation film, 3...Polysilicon resistor.

Claims (1)

[Claims] 1. In a semiconductor device in which a resistor is formed on an isolation film, the isolation film is partially thinned,
A semiconductor device characterized in that the resistor is provided in this thinned portion. 2. The semiconductor device according to claim 1, wherein the resistor is made of polysilicon. 3. The semiconductor device according to claim 1 or 2, wherein a PN junction capacitor is formed under the isolation film.