JPH04213856A - Fail-safe operation integrated circuit - Google Patents

Abstract

PURPOSE:To enable a fail-safe operation integrated circuit to be protected against malfunction caused by the effect of noises or the like by a method wherein an insulating layer is provided between a semiconductor board and elements formed on the semiconductor board and between the elements respectively to insulate them from each other, and a thin film resistor is made to serve as a resistive element. CONSTITUTION:A well 31 is provided to a P semiconductor substrate 1, a transistor region is formed in the well 31, and for instance an NPN transistor element is provided to the transistor region. A thin film resistor 40 is formed on the P substrate 1. That is, an insulating layer is provided between the P substrate 1 and the transistor element and the resistive element formed on the P substrate 1. The well 31 is provided to the P substrate 1 with an insulating layer, where the insulating layer is formed of a silicon oxide layer 32 and a spinel epitaxial layer 33 or only the silicon oxide layer 32 formed through an ion implantation method or anodization and thermal oxidation. By this setup, even if a P layer is changed in potential bias to the P substrate due to the effect of noises or the like, a transistor can be protected against malfunction.

Description

[Detailed description of the invention]

0001

FIELD OF INDUSTRIAL APPLICATION The present invention relates to the structure of integrated circuits.
In particular, it relates to the structure of fail-safe arithmetic integrated circuits used for safety control (control that permits work only when safety is confirmed).

0002

[Prior Art] Conventionally, in fields where safety control is required, such as signal safety systems in railways, etc., fail-safe systems have been developed to control output signals to the safe side in the event that a component fails. Design philosophy is applied. Fail-safe relays have been used for a long time as a physical means to realize this design concept, and are still used as important components today.

[0003] Furthermore, the field in which such safety control is required is expanding not only to the railway field, but also to the factory automation (FA) field, such as robots and press machines, security, and home automation (HA) fields. . In recent years, in fields where such safety control is required, the use of microelectronics has been progressing to increase speed, miniaturization, and multifunctionality. For example, fail-safe operation circuits using semiconductors such as logic operation oscillators, etc. was proposed (Electrical Testing Institute Report No. 695, JAN.
(See 1969 “Research on Fail-Safe Logic Methods,” etc.)
Furthermore, various improvements have been made to, for example, thick-film hybrid ICs that are now being used (Japanese Patent Application Laid-Open No. 1983-1960).
(Refer to Publication No.-68719, etc.).

Furthermore, the above-mentioned logic operation oscillators and the like have been made into monolithic ICs in which all the circuit components of one integrated circuit are fabricated on one silicon crystal substrate, and further miniaturization and high integration are being promoted. (“Failsafe logical AND I
"C and its Applications", Institute of Electronics, Information and Communication Engineers Research Report FTS86
-3, 1986). In such a monolithic IC, elements such as resistors, transistors, etc. are separated by pn junction isolation in which a p layer (a layer with few electrons) and an n layer (a layer with many electrons) are joined together. Element isolation by pn junction isolation is achieved by thermally diffusing impurities during the manufacturing process to separate p-layer, n-layer
Because layers can be formed and elements can be integrally formed,
Even if the degree of integration of elements is increased, costs can be reduced,
It has the advantage of being excellent in mass production, and has been widely adopted as a general method.

The resistance region of a conventional fail-safe arithmetic integrated circuit constructed of such a monolithic IC, NPN
Cross-sectional views of the transistor region and the PNP transistor region are shown in FIGS. 4A, 4B, and 4C, respectively. First, in FIG. 4A, which is a resistance region, for example, a p-type silicon substrate (hereinafter referred to as p-substrate) 1 which is generally commercially available.
In the figure, an n-type layer is formed on a p-substrate 1 by epitaxial growth. Further, in this n-type layer, a p-type impurity is thermally diffused and separated so as to surround the resistor formation region until it is connected to the p-substrate 1, thereby forming an n-layer 3. A p-type impurity is thermally diffused from the surface of this n-layer 3 to form a p-layer 4. When forming the p-layer 4 for surface protection, the surface is simultaneously thermally oxidized to form a silicon oxide film 5. Here, p-n junction isolation is formed between the p-substrate 1 and the n-layer 3, and the p-layer 4 is used as a resistor. Therefore, a thin film pattern 6 of aluminum (hereinafter referred to as "aluminum") is wired to the parts 4a and 4b from which a part of the silicon oxide film on the surface has been removed by etching, for example. Further, aluminum 2 is formed on the back surface of the p-substrate 1 as a ground electrode. In this way, a resistive region is formed.

Next, FIG. 4 (
In B), an n-type impurity is thermally diffused from the surface of the p-substrate 1 to form an n+ buried layer 7. Thereafter, an n-type layer is formed by epitaxial growth. Furthermore, in this n-type layer, a p-type impurity is thermally diffused to surround the transistor formation region until it is connected to the p-substrate, and the n-type impurity is separated.
Form layer 8. Here, a p-type impurity is thermally diffused to form a p-layer 10 that will serve as a base, and then an n-type impurity is further thermally diffused to form n+ layers 9 and 11 that will be a collector and an emitter. For surface protection, when forming the n+ layers 9 and 11, the surface is simultaneously thermally oxidized to form a silicon oxide film 12. In the silicon oxide film 12, a portion of each layer serving as the collector, base, and emitter terminals is removed by etching, and wiring is formed from the etched portions 9a, 10a, and 11a using a pattern 13 made of aluminum, for example.

FIG. 4 (
In C), an n-type layer is formed on the p-substrate 1 by epitaxial growth. Furthermore, this n
The p-type impurity is thermally diffused to surround the transistor formation region in the form layer until it is connected to the p-substrate 1, and the n-type impurity is separated.
Form layer 14. An n-type impurity is thermally diffused from the surface of this n-layer 14 to form an n+ layer 15 serving as a base. Furthermore, p-type impurities are thermally diffused to form p+ layers 16 and 17 which will serve as collectors and emitters. p for surface protection
+ When forming the layers 16 and 17, the surfaces are simultaneously thermally oxidized to form a silicon oxide film 18. In the silicon oxide film 18, a portion of each layer that will become the collector, base, and emitter terminals is removed by etching, and wiring is formed from the etched portions 16a, 15a, and 17a using, for example, an aluminum pattern 19.

Next, the operation will be explained. In such a fail-safe arithmetic integrated circuit, when in use, the n-layer 3 of the diffused resistance region, the n-layer 8 of the NPN transistor region, and the n-layer 14 of the PNP transistor are placed in a reverse bias state with respect to the p-substrate 1. By putting each region in a reverse bias state in this way, a depletion layer lacking electrons and holes is created at the pn junction, and the depletion layer has a high resistance value, which makes it possible to connect each element and the p-substrate 1. Each element is separated by pn junction.

[0009]

However, in conventional fail-safe arithmetic integrated circuits, elements are separated by pn junction isolation, which causes various problems, particularly with respect to fail-safe performance. First, in an NPN transistor, when in use, it is reverse biased to separate the pn junction, but when the potential of the p-substrate 1 becomes higher than the collector potential due to noise etc., the pn junction isolation changes from reverse bias to forward bias. Since current flows into the transistor from the p-substrate 1, the element and the p-substrate 1 become electrically connected, and there is a very high possibility of malfunction. For this reason, a diode with the anode on the collector side had to be connected between the collector and emitter to prevent malfunction.

[0010] Furthermore, in a PNP transistor, p
When the potential of the substrate 1 becomes higher than the potential of the n+ layer 15 which is the base and becomes a forward bias state, the n+ layer 15 which is the base
A parasitic transistor is formed of the layer 15, the p+ layer 16 as the collector, and the p substrate 1, and this parasitic transistor brings conduction between the collector and the emitter.
There is a risk of malfunction.

When such a parasitic transistor is formed, circuit analysis and failure analysis at the integrated circuit level are complicated and extremely difficult, and it is also difficult to control the characteristics of the parasitic transistor. Further, problems caused by parasitic transistors occur not only in bipolar transistors but also in field effect transistors (MOSFETs).

Next, it is difficult to make the diffused resistance in the resistance region high in resistance. Therefore, a constant current circuit must be provided to replace the diffused resistor. However, when a constant current circuit is provided to achieve a high resistance value, the number of elements increases significantly as the degree of integration increases, and as the number of elements increases, there is a risk that the probability of failure increases accordingly. Furthermore, silicon has a large temperature coefficient, and the diffused resistance formed on the p-substrate 1 changes greatly due to temperature fluctuations, resulting in low accuracy, stability, and linearity of the resistance value.

[0013] When such a fail-safe arithmetic integrated circuit is used for safety control, the operating conditions are extremely strict, and there is a possibility that it may not necessarily be safe in normal use. The present invention has been made in view of such conventional problems, and an object of the present invention is to provide a fail-safe arithmetic integrated circuit that has extremely few malfunctions due to the influence of noise and the like.

[0014]

[Means for Solving the Problems] Therefore, the present invention provides a fail-safe arithmetic integrated circuit in which a large number of elements are integrated on a semiconductor substrate, and the elements are separated from each other and between the elements and the semiconductor substrate. In this method, an insulating layer made of an insulating material was provided between the semiconductor substrate and the elements formed on the semiconductor substrate and between the elements for insulation isolation, and the resistance element was formed of a thin film resistor.

[0015]

[Operation] According to the above structure, the elements formed on the semiconductor substrate are completely insulated and separated from the semiconductor substrate and other elements by the insulator of the insulating layer, except for the wiring between the elements. . Therefore, malfunction of the element due to the influence of the bias state between the semiconductor substrate and the element can be prevented. In addition, by forming the resistance element with a thin film resistor, a high resistance value can be obtained without providing a constant current circuit, the number of elements on the semiconductor substrate can be reduced, circuit analysis is easy, and there is a high probability of failure. It is also possible to reduce the

[0016]

Embodiments Hereinafter, embodiments of the present invention will be explained based on FIGS. 1 to 3. Incidentally, the same elements as those in FIG. 4 are given the same reference numerals, and the description thereof will be omitted. Figure 1 for the first embodiment
The explanation will be based on. This is a semiconductor substrate p
A well is provided on a type substrate (or an n-type substrate), a transistor region is formed in the well, and a thin film resistor is provided on a p-type substrate.

In FIG. 1, the transistor region will be explained using an NPN transistor element as an example. First p
A well 31 is provided on the substrate 1 by, for example, etching, and the surface is oxidized to form a silicon oxide layer 32 in the well 31. For example, a silicon oxide (SiO2) layer 32 is formed by thermal oxidation in an oxidizing atmosphere. For example, CVD (chemical vapor depot) is applied to the well 31 in which the silicon oxide layer 32 is formed.
A spinel epitaxial layer 33, an n+ layer 34, and an n layer 35 are sequentially formed by a method such as a sintering method. Here, the insulating layer made of an insulator is composed of a silicon oxide layer 32 and a spinel epitaxial layer 33, and the spinel epitaxial layer 33 is made of, for example, Al2 O3 .MgO, etc., and serves as an insulating layer and relieves stress. Also n+
Layer 34 is a buffer layer that improves crystallinity and achieves matching. After the well 31 is filled, a p layer 36 that will serve as a base and an n+ layer 37 that will serve as a collector are formed by, for example, a diffusion method.
After forming a layer 38 and oxidizing the surface of the p-substrate 1 to form a silicon oxide layer 39, the collector, emitter, and base electrode portions 37a, 38a, and 36a are etched, for example, and wired with an aluminum pattern 19. In this way, an NPN transistor element is formed in the NPN transistor region on the p-substrate 1 via the insulating layer of the silicon oxide layer 32 and the spinel epitaxial layer 33.

Next, to form the thin film resistor 40 as a resistance element, a material such as silicon chromium or tantalum nitride is formed on the silicon oxide layer 39 on the p-substrate 1 by vapor deposition or sputtering. A second insulating layer 41 is provided thereon. Next, the effect will be explained. Even if the potential of the n+ layer 37, which is the collector layer, becomes forward biased due to noise or the like with respect to the p-substrate 1, the p-substrate 1 and the transistor region are completely insulated and separated by the silicon oxide layer 32. , current will not flow from the p-substrate 1 to the n-layer 35, and the transistor will not malfunction. In addition, the material used for the thin film resistor 40 in the resistance region has a small temperature coefficient, so the resistance value changes very little with temperature changes. can be obtained with high accuracy, and therefore there is no need to provide a constant current circuit to obtain a predetermined resistance value.

According to this configuration, the p-substrate 1 and the p-substrate 1
By providing a silicon oxide layer 32, a spinel epitaxial layer 33, and a silicon oxide layer 39, which are insulators between the transistor element and resistance element formed above, an n+ layer 37, which is a collector, is provided for the p-substrate 1. Even if the bias state of the potential changes due to noise or the like, the transistor will not malfunction. In addition, since the resistance element is a thin film resistor, there is little temperature fluctuation, and it is possible to obtain a resistance with excellent accuracy and stability.Also, the constant current circuit required to obtain a high resistance value can be saved, and the constant current No circuit elements are needed, and the probability of failure is reduced. In this way, it is possible to prevent malfunctions of the transistor elements formed on the p-substrate 1 and reduce the probability of failure, thereby further improving fail-safe properties and improving the reliability of the fail-safe arithmetic integrated circuit. I can do it.

Next, a second embodiment will be explained based on FIG. 2. In this device, the transistor region is covered with an insulating layer using an ion implantation method. In FIG. 2, oxygen is implanted into the p-substrate 1 by ion implantation,
A silicon oxide layer 51 is formed, and an n-layer 35, which is an epitaxial layer, is formed thereon by, for example, vapor phase growth.
A silicon oxide layer 53 is provided by selective oxidation, and a transistor element is formed in a region surrounded by the buried silicon oxide layer 51 and the silicon oxide layer 53. Thereafter, a resistance element is formed of a thin film resistor 40 in the same manner as in the first embodiment.

Next, a third embodiment will be explained based on FIG. 3. In this method, a silicon substrate is anodized to form porous silicon, and the porous silicon is thermally oxidized to form a porous silicon oxide layer. In FIG. 3, the surface of the transistor formation region on the p-substrate 1 is masked, porous silicon is formed by anodization except for the transistor formation region, and the porous silicon is thermally oxidized to form a porous silicon oxide layer. 61 is formed. Thereafter, a transistor element is formed in the region where a transistor is to be formed. As a result, the transistor elements in the transistor region are insulated and isolated by the porous silicon oxide layer 61 between the p-substrate 1 and the transistor elements. After the transistor element is formed, a resistance element is formed using a thin film resistor 40 in the same manner as in the first embodiment.

In the first to third embodiments, bipolar NPN transistors have been described as transistor elements, but even in the case of PNP transistors, parasitic transistors can be prevented by providing an insulating layer made of an insulator. Furthermore, not only bipolar transistors but also field effect transistors can be prevented from malfunctioning and from generating parasitic transistors. Furthermore, the method of forming the insulating layer is not limited to the methods of the three embodiments described above, and other forming methods may be used.

[0023]

Effects of the Invention As explained above, according to the present invention, the insulation layer between the semiconductor substrate and the elements and between the elements can be improved except for the wiring area between the elements by the insulation layer of the insulator. Since the transistors are completely isolated, malfunctions of the transistors due to changes in bias conditions are prevented. Furthermore, by forming the resistance element with a thin film resistor, it is possible to obtain a resistor with a high resistance value without providing a constant current circuit, which reduces the number of elements used in the constant current circuit and reduces the probability of failure. Therefore, the reliability of the fail-safe arithmetic integrated circuit can be improved.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a first embodiment of a fail-safe arithmetic integrated circuit according to the present invention.

FIG. 2 is a sectional view showing a second embodiment of the fail-safe arithmetic integrated circuit according to the present invention.

FIG. 3 is a sectional view showing a third embodiment of the fail-safe arithmetic integrated circuit according to the present invention.

FIG. 4 is a cross-sectional view of a conventional fail-safe arithmetic integrated circuit.

[Explanation of symbols]

1 P-type silicon substrate (p substrate) 2 Aluminum (aluminum) 31 Well 32 Silicon oxide layer 33 Spinel epitaxial layer (buffer layer) 34
n+ layer (buffer layer) 39 silicon oxide layer 40 thin film resistor 51 silicon oxide layer 52 n+ layer 53 silicon oxide layer

Claims (1)

[Claims] Claim 1: A large number of elements are integrated on a semiconductor substrate,
In the fail-safe arithmetic integrated circuit configured such that the elements are separated from each other and between the elements and the semiconductor substrate, between the semiconductor substrate and the element formed on the semiconductor substrate,
and a fail-safe arithmetic integrated circuit, characterized in that an insulating layer made of an insulating material is provided between the elements for insulation isolation, and the resistive element is formed of a thin film resistor.