JPS62252972A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve breakdown strength against noise pulses, in a semiconductor device having a series resistor at the input or output terminal of an MISFET, by constituting the resistor with a resistor having a positive temperature coefficient. CONSTITUTION:A resistor 10, which is constituted by a polycrystalline silicon film, is formed in series with a gate electrode 9 of an MIS type FET. The doping concentration of the polycrystalline silicon film constituting the resistor 10 is selected so that the temperature coefficient of the value of electric resistance is positive. The resistor 10 acts to decrease the peak value of the high voltage pulses of noises, which enter from the outside. Since the resistance value has the positive temperature coefficient during this action, current concentration due to the pulses is not generated. Therefore, strength against thermal breakdown becomes high. Therefore, the breakdown strength against the input noise pulse voltage can be improved to a large extent.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a protection circuit for MIS type field effect transistors.

[Conventional technology]

FIG. 2 shows a schematic diagram of the cross-sectional structure of a conventional MIS field effect transistor. In FIG. 2, 41 is a P-type (or N-type) semiconductor substrate, and 42 and 46 are impurity diffusion layers formed in a part of the semiconductor substrate 41 by ion implantation. is a source 4 formed by a diffusion layer of Pa)
2 and drain 46, 44 are channel regions formed on the surface of the semiconductor substrate sandwiched between these source 42 and drain 43, 45 is a gate insulating film formed on this channel region 44 (7), and 46 is a further A gate electrode is formed on this gate insulating film 45 using a metal film such as aluminum. Since this gate electrode 46 is an input terminal of the MIS type field effect transistor, this terminal is an output terminal of another MIS type field effect transistor made on the same semiconductor substrate or is configured by these MIS type field effect transistors. Connected to the input terminal of the semiconductor integrated circuit. MI connected to the input terminal of the semiconductor integrated circuit
A pulsed high voltage due to static electricity or the like may be applied from the outside to the gate electrode 46 of the S-type field effect transistor during assembly work, but as is clear from the structural diagram shown in FIG. The high voltage is applied to the gate insulating film 45.
Since a voltage is applied to the gate insulating film 45, dielectric breakdown often occurs in the gate insulating film 45. Also, if this high voltage is applied to the output terminal, the PN junction of the drain 46 or the source 42 will be destroyed. can also lead to permanent destruction of semiconductor integrated circuits.

For this reason, a protection circuit is usually provided at the input/output terminals of a semiconductor integrated circuit in order to protect the internal MIS type field effect transistors from these external high voltages. In order to explain the operating principle of this protection circuit, an equivalent circuit thereof is shown in FIG.

In FIG. 3, diodes 66 and 34 are inserted in reverse connection between the positive power supply VDD and negative power supply VSS of the semiconductor integrated circuit and the gate electrode 65 of the MIS field effect transistor, and the MIS field effect transistor A resistor 62 is connected in series to the gate electrode 35 .

When a high voltage is applied to the input terminal 61 of the semiconductor integrated circuit, the diodes 36 and 64 operate to short-circuit the high voltage to the positive power source VDD or the negative power source VSS due to their forward characteristics.

Further, the resistor 32 connected in series with the gate electrode 65 constitutes an integrating circuit with the junction capacitance of the diodes 66 and 64, and functions to blunt the peak value of the externally applied pulse-like high voltage.

[Problem that the invention seeks to solve]

However, in the conventional protection circuit, a large current momentarily flows through the resistor 62 when a high voltage is applied from the outside, but since the resistor 32 has a negative temperature coefficient, current concentration occurs once in a part of the resistor 62. Then, the temperature of this current concentrated part rises more than other parts, and the resistance of this concentrated part becomes lower than other parts, so the current is further concentrated in this current concentrated part, which further increases the temperature and causes even more current. cause concentration. This also brings about the next stage of temperature rise and the next stage of current concentration. In this way, there is a drawback that a positive thermal feedback is generated, which ultimately leads to thermal destruction of the resistor 62.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate such drawbacks and to provide a semiconductor device in which a resistor connected in series to an input terminal or an output terminal of an MIS type field effect transistor has a high thermal breakdown strength.

[Means for solving problems]

According to the present invention, the resistor connected in series to the input terminal or output terminal of the MIS field effect transistor is constituted by a resistor having a positive temperature coefficient.

〔Example〕

Next, embodiments of the present invention will be described in order of steps with reference to the drawings. As shown in FIG. 1(a), a silicon oxide film 2 with a thickness of 5,000 to xooo is formed on an N-type semiconductor substrate 1 by a method such as thermal oxidation.
Next, as shown in FIG. 1(b), an opening 6 is formed in the silicon oxide film 2 by photoetching, and P-type impurities are diffused through this opening 6 to create a MIS type electric field. A P-type diffusion layer 4 constituting a P-type region of a diode connected between the gate electrode of the effect transistor and the negative power supply VSS is formed.

Next, as shown in FIG. 1(C), the silicon oxide film 2 is completely removed, and a silicon oxide film 5 is again formed to a thickness of 5000 to 5000 mm by a method such as thermal oxidation. An opening 6 is provided to expose the silicon surface, and a silicon oxide film 7 is formed on the exposed portion to a thickness of approximately 500A by thermal oxidation or the like. A polycrystalline silicon film 8 is formed over the entire surface of the semiconductor substrate 1 by a growth method or the like.

Next, as shown in FIG. 1(d), this polycrystalline silicon film 8 is etched into a desired shape by photo-etching, and the gate electrode 9 of the MIS type field effect transistor and the polycrystalline silicon film 8 inserted in series with the gate electrode are etched. A resistor 10 made of a crystalline silicon film is formed.

At this time, the doping concentration of impurities in the polycrystalline silicon film that will become the gate electrode and the polycrystalline silicon film that will make up the resistor will be changed so that the temperature coefficient of the electrical resistance value will be positive for the polycrystalline silicon film that will make up the resistor. Choose a suitable concentration.

Next, using an oxide film 5.7 or a photoresist film as a mask, P-type impurities are diffused into desired portions to form P-type diffusion layers 11 and 12, which form the source and drain of the MIS field effect transistor; A P-type diffusion layer 13 forming a P-type head region of the diode connected between the gate electrode 9 of the MIS field effect transistor and the positive power supply VDD, and an electrical contact between the P-type diffusion layer 4 and VSS. A P-type diffusion layer 15 is formed for each MI layer, and then an N-type impurity is diffused into a desired portion in the same manner as the P-type impurity.
The gate electrode 9 of the S-type field effect transistor and the negative power supply V
An N-type diffusion layer 14 forming an N-type region of the other diode connected between the SSO, an N-type semiconductor substrate 1 and a V
N-type diffusion layer 1 for making electrical contact with DD
6 each.

Next, as shown in FIG. 1(e), a phosphorous glass film which will become the interlayer insulating film 17 is formed on the entire surface of the semiconductor substrate 1 by vapor phase growth or the like, and the desired thickness of the glabellar insulating film 17 and the oxide film 7 is formed. A contact hole 18 is formed in the area by photo-etching, then a conductive metal film such as an aluminum film is formed on the entire surface of the glabella insulating film 17, and then unnecessary parts are removed by photo-etching to form an MIS. The source electrode 19, the drain electrode 21, the gate electrode wiring 20, the terminal wiring 22, 23 of the resistor 10, the positive power supply VDD and the negative power supply Vss of the MIS field effect transistor, and the gate electrode 90 of the MIS field effect transistor are connected in opposite directions, respectively. A wiring 24 connecting the two diodes inserted in a directional connection, an electrode 25 for the negative power source VSS, and an electrode 26 for the positive power source VDD are formed, respectively.

〔Effect of the invention〕

As described above, according to the present invention, the resistor 10 is connected in series to the gate electrode 9 of the MIS field effect transistor and blunts the peak value of the noise high voltage pulse applied from the input/output terminal of the semiconductor integrated circuit. Since the resistance value has a positive temperature coefficient, current concentration due to this pulse current does not occur and the current is distributed uniformly, so the thermal breakdown strength is greater than that of the conventional one (therefore, the input noise pulse voltage The withstand voltage can be greatly improved.

In the embodiment, the semiconductor substrate is of N type, but it goes without saying that the same effect can be obtained even if a P type semiconductor substrate is used.

[Brief explanation of drawings]

1(a) to (e) are schematic cross-sectional views explaining the manufacturing process of the conductor device of the present invention, FIG. 2 is a schematic cross-sectional view explaining the structure of an MIS field effect transistor, and FIG. 3 is a protection circuit. FIG. 2 is an equivalent circuit diagram illustrating the operation of FIG. 1... Semiconductor substrate. (C) 1 4, I am type P 4
λChi-X flash (d) (e) Figure 2 Figure 3

Claims (1)

[Claims] A semiconductor having at least one metal-insulator-semiconductor (hereinafter referred to as MIS) type field effect transistor provided on a substrate and at least one resistor connected in series to the input terminal or output terminal of the transistor. In the device,
A semiconductor device characterized in that the resistor is constituted by a resistor having a positive temperature coefficient.