JPS63137478A - Manufacture of semiconductor device having protective circuit - Google Patents

Abstract

PURPOSE:To manufacture a semiconductor device with a protective circuit without increasing manufacturing processes by forming a first-conductivity type region for isolating an element onto a first-conductivity type substrate, an insulating film for isolating the element into the region and a second-conductivity type region including source and drain regions onto the substrate and implanting impurity ions into a predetermined region. CONSTITUTION:A P<+> region 18 for isolating an element and a field oxide film 20 are shaped onto a P-type substrate 10. An N<+> diffusion resistance region 12 corresponding to an input protective resistor, an N<+> diffused region 14 for a drain constituting a MOSFET for protecting an input and an N<+> diffused region 16 for a source are formed simultaneously. A contact hole is shaped to a gate oxide film 22 on the source region 16, and polysilicon 24 functioning as a gate electrode in combination is formed. A resist pattern 28 is shaped, B ions are implanted into the junction region of the regions 12 and 18 and a region for controlling the threshold voltage of a ROM memory Tr, using the resist pattern as a mask, and P<++> regions 30, 32 are formed. A gate oxide film 22 is shaped, a contact hole is bored and a metallic wiring 26 is formed, and the regions 12 and 14 are connected.

Description

Detailed Description of the Invention (Technical Field) The present invention is applicable to MOSFETs such as mask ROM memory ICs.
The present invention relates to a method of manufacturing a semiconductor device including a PN diode for a protection circuit, and particularly to a method of manufacturing a semiconductor device including a PN diode for a protection circuit.

(Conventional technology) MOSFET has an insulated gate electrode.

MO5 type semiconductor devices with integrated MOSFETs are particularly susceptible to electrostatic discharge damage, so a protection circuit is generally inserted between the input terminal and the input circuit to absorb overvoltage.

The protection circuit can be inserted with a resistor, a PN diode, a combination of a resistor and a PN diode, or a resistor and MOSF
There are combinations of ET, etc.

FIG. 4 shows an example of a protection circuit.

Input protection resistor 6 is connected between input pad 2 and first stage inverter 4.
is inserted, and a MOSFET 8 whose gate and source are short-circuited is inserted between the node between the input protection resistor 6 and the first-stage inverter 4 and the substrate.

Figure 5 shows the input protection resistor 6 and MOSFET in Figure 4.
8 is shown.

10 is a P-type silicon substrate, 12 is N+ corresponding to resistor 6
The diffused resistance region 14.16 is a drain region and a source region made up of N+ diffusion regions constituting the N08FET8. 18 is a P+ region for element isolation, 20 is a field oxide film, and 22 is a gate oxide film.

24 is a polysilicon layer that short-circuits the gate and source of MOSFET 8. N+ diffused resistance region 12 and MOSFE
The drain region 14 of T is connected by a metal wiring 26, and the metal wiring 26 is connected to the inverter 4 (FIG. 4).

In the protection circuit shown in FIG. 5, the impurity concentration of the PN junction is approximately 1016/cm3 in the P" region 18, and
Since it is about 10''/am3 in the regions 12, 14, and 16, the breakdown voltage can only be lowered to about 20V at most.

Therefore, in order to further reduce the breakdown voltage of the PN junction,
A protection circuit has been proposed in which a region with high impurity concentration is formed at the PN junction (see Japanese Patent Publication No. 34270/1983).

However, the protection circuit proposed in that cited document requires one manufacturing process to form a region with high impurity concentration.
There are additional problems and manufacturing disadvantages.

(Objective) An object of the present invention is to provide a method of manufacturing a semiconductor device having a PN diode with a low breakdown voltage as a protection circuit without increasing the number of manufacturing steps.

(Structure) The manufacturing method of the present invention includes the steps ('A) to (D) shown below.

(A) forming a first conductivity type region for element isolation on one main surface of a semiconductor substrate of a first conductivity type; (B) forming a first conductivity type region for element isolation on one main surface of the semiconductor substrate; (C) forming a second conductivity type region including at least a source region and a drain region on one main surface of the semiconductor substrate; (D) the predetermined second conductivity type region; and implanting impurity ions at a higher concentration than the 14th conductivity type region for element isolation using the same mask into a region in contact with the predetermined first conductivity type region for element isolation and a region for controlling the threshold voltage. Process.

Hereinafter, an embodiment in which the present invention is applied to a mask ROM semiconductor device will be specifically described.

FIGS. 1A to 1E are cross-sectional views of a semiconductor device showing one embodiment in the order of steps.

(1) As shown in FIG. 1A, a P'' region 18 for element isolation and a field oxide film 20 are formed on a P-type substrate IO by a conventional method.

(2) As shown in the same figure (B), the N+ diffused resistance region 12 corresponding to the input protection resistor and the MOSFE for input protection
The N'') diffusion region 14 for the drain and the N+ diffusion region 16 for the source, which constitute T, are formed at the same time.

A contact hole is opened in the gate oxide film 22 on the source region 16, and a polysilicon layer 24 which also serves as a gate electrode is formed.

(3) As shown in FIG. 2C, a resist pattern 28 is formed, and boron ions are implanted using this resist pattern 28 as a mask. The regions where boron ions are implanted are the junction between the N+ diffused resistance region 12 and the element isolation P'') region 18, the drain region 14 and the element isolation P+
The joining area of region 18 and although not shown in the figure,
This is a region for controlling the threshold voltage of the ROM memory transistor.

In mask ROM, memory transistors “1” and “0”
In order to make a transistor that does not operate even at the power supply voltage, boron ions are implanted into the channel to increase the threshold voltage. The boron ion implantation shown in FIG. 3C is performed simultaneously with threshold voltage control using a boron ion implantation mask for threshold voltage control. This boron ion implantation is carried out at 1×
This is carried out under conditions of approximately 10"/am".

(4) By this boron ion implantation, as shown in FIG. A P + + region 32 is formed between the P'' regions 18 . The impurity concentration of the P+" region 30.32 is about 1017/am3.

After this, a gate oxide film 22 is formed again.

(5) As shown in Figure (E), the gate oxide film 22
By forming a contact hole and forming a metal wiring 26 in the
Connect the drain region 14 of the ET.

The area surrounded by the chain line in FIG. 2 represents the equivalent circuit of the semiconductor device shown in FIG. 2(E).

One end of the resistor 6 corresponding to the N+ diffused resistor region 12 has a P
A PN diode 34 is formed by the + + region 32 and the N+ diffused resistance region 12, and a P+1 diode is formed in parallel with the N08FET8.
PN diode 36 with region 32 and drain region 14
is formed. The breakdown voltage of the PN diode 34, 36 is about 7 to 9V.

Only one of the PN diodes 34 and 36 according to this embodiment may be formed. Such a protection circuit can be used as an input protection circuit as shown in FIG.

FIG. 3 shows the operation when the input signal 38 is input to this embodiment.

Since the breakdown voltage of the protection diodes 34 and 36 is 7 to 9 V, if a surge as shown by symbols 40-1 to 40-4 comes into the input signal 38, the 7 to 9 V line L
The surge in the positive region can flow toward the substrate side by breakdown of the protection diodes 34 and 36.

The method of the present invention can be applied not only to mask ROM semiconductor devices but also to methods of manufacturing semiconductor devices that include a step of performing high-concentration ion implantation to control threshold voltage.

(Effects) In the PN diode formed according to the present invention, its breakdown voltage can be lowered to close to 7V, which is the guaranteed power supply voltage. In addition, the method of the present invention does not require a special process for forming a protection diode with a low breakdown voltage, and is performed simultaneously with the process for controlling the threshold voltage, so that the number of manufacturing steps is not increased.

[Brief explanation of the drawing]

1A to 1E are cross-sectional views of a semiconductor device showing one embodiment in the order of steps, FIG. 2 is an equivalent circuit diagram mainly showing a protection circuit formed in the same embodiment, and FIG. FIG. 4 is a waveform diagram showing the operation of the same embodiment, FIG. 4 is a circuit diagram showing a conventional protection circuit, and FIG. 5 is a sectional view of a device implementing the protection circuit of FIG. 4. 10...P-type substrate, 12...N+ diffused resistance region, 14...Drain region, 16...Source region, 18... P” region for element isolation, 30.32...
...High concentration impurity region.

Claims (1)

[Claims] (1) A method for manufacturing a semiconductor device that includes the following steps (A) to (D) to form a protection circuit. (A) forming a first conductivity type region for element isolation on one main surface of a semiconductor substrate of a first conductivity type; (B) forming a first conductivity type region for element isolation on one main surface of the semiconductor substrate; (C) forming a second conductivity type region including at least a source region and a drain region on one main surface of the semiconductor substrate; (D) the predetermined second conductivity type region; and implanting impurity ions at a higher concentration than the first conductivity type region for element isolation using the same mask into a region in contact with the predetermined first conductivity type region for element isolation and a region for controlling the threshold voltage. Process.