JPS6360547B2 - - Google Patents
Info
- Publication number
- JPS6360547B2 JPS6360547B2 JP55077736A JP7773680A JPS6360547B2 JP S6360547 B2 JPS6360547 B2 JP S6360547B2 JP 55077736 A JP55077736 A JP 55077736A JP 7773680 A JP7773680 A JP 7773680A JP S6360547 B2 JPS6360547 B2 JP S6360547B2
- Authority
- JP
- Japan
- Prior art keywords
- mos
- fet
- type
- breakdown voltage
- impurity concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000015556 catabolic process Effects 0.000 claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 16
- 239000012535 impurity Substances 0.000 claims description 13
- 239000000758 substrate Substances 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 230000003071 parasitic effect Effects 0.000 description 5
- 101100484930 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) VPS41 gene Proteins 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は、MOS型集積回路デバイスに係り、
さらに詳しくは、該集積回路デバイスの各端子に
印加される過電圧から回路デバイスを保護するよ
うにしたMOS型集積回路デバイスに関するもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a MOS type integrated circuit device,
More particularly, the present invention relates to a MOS type integrated circuit device that protects the circuit device from overvoltage applied to each terminal of the integrated circuit device.
MOS型集積回路（以下MOS・ICと略す）は、
入力端子にMOS・FETが接続され、構成してあ
るがこのMOS・FETのゲートには極めて薄いシ
リコン酸化膜が使用されている。そこで、入力端
子に印加される過電圧により前記シリコン酸化膜
が絶縁破壊するのを防止するために、第１図に示
すようにダイオード、抵抗から成る保護回路を接
続している。第１図において、１１は入力端子、
１２は電源端子、１３は接地端子、１４ａ，１４
ｂはゲート端子を共通にして直列接続した２個の
MOS・FETである。また、１５は入力端子に直
列接続した入力保護抵抗、１６はMOS・FETの
ゲートとソース間に挿入した入力保護ダイオード
でこれらは入力端子１１に印加される過電圧から
MOS・FETを保護するために設けてある。１８
ａ，１８ｂは前述のMOS・FET１４ａ，１４ｂ
と同様に電源と接地間に接続した最終段の
MOS・FETで、これら、MOSFET１４ａ，１
４ｂと１８ａ，１８ｂとの間（端子ＡとＢの間）
には複数のMOS・FETが形成されている。１９
はこのMOS型集積回路デバイスの出力端子であ
る。 MOS type integrated circuit (hereinafter abbreviated as MOS/IC) is
A MOS/FET is connected to the input terminal, and an extremely thin silicon oxide film is used for the gate of this MOS/FET. Therefore, in order to prevent dielectric breakdown of the silicon oxide film due to overvoltage applied to the input terminal, a protection circuit consisting of a diode and a resistor is connected as shown in FIG. In FIG. 1, 11 is an input terminal;
12 is a power terminal, 13 is a ground terminal, 14a, 14
b is two pieces connected in series with a common gate terminal.
It is MOS/FET. Also, 15 is an input protection resistor connected in series to the input terminal, 16 is an input protection diode inserted between the gate and source of the MOS/FET, and these are protected from overvoltage applied to the input terminal 11.
It is provided to protect the MOS/FET. 18
a, 18b are the aforementioned MOS/FETs 14a, 14b
Similarly, the final stage connected between the power supply and ground
With MOS/FET, these are MOSFET14a, 1
Between 4b and 18a, 18b (between terminals A and B)
Multiple MOS/FETs are formed in the . 19
is the output terminal of this MOS type integrated circuit device.
第１図に示すように、入力端子１１に印加され
る過電圧対策としては保護回路が備えてあるもの
の、出力端子１９および電源端子１２に接続され
るMOS・FETのゲート酸化膜には保護回路は特
に設けられていない。また、これらMOSFETの
ソースおよびドレイン電極とシリコン基板との間
には、寄生的なp+nおよびn+p接合（破線で示す
寄生ダイオード１７）が形成されるが、この寄生
ダイオードの耐電圧は何ら管理されることなく製
造されているため、その耐電圧はゲートシリコン
酸化膜の絶縁破壊電圧より大きい場合があり、出
力端子１９や電源端子１２に前記した降伏電圧以
下の小さなサージ電圧が印加してもMOS・FET
１４ａ，１４ｂや１８ａ，１８ｂのゲートシリコ
ン酸化膜を絶縁破壊に至らしめる。市場における
MOS・ICの不良の過半数数は、入力端子１２に
接続されたMOS・FET以外のゲートシリコン酸
化膜の絶縁破壊によるものである。 As shown in FIG. 1, although a protection circuit is provided as a countermeasure against overvoltage applied to the input terminal 11, the gate oxide film of the MOS/FET connected to the output terminal 19 and the power supply terminal 12 is not equipped with a protection circuit. Not specifically provided. Additionally, parasitic p + n and n + p junctions (parasitic diodes 17 shown by broken lines) are formed between the source and drain electrodes of these MOSFETs and the silicon substrate, but the withstand voltage of these parasitic diodes is Because it is manufactured without any control, its withstand voltage may be higher than the dielectric breakdown voltage of the gate silicon oxide film, and a small surge voltage below the breakdown voltage mentioned above may be applied to the output terminal 19 and power supply terminal 12. Even MOS/FET
This causes dielectric breakdown of the gate silicon oxide films 14a, 14b and 18a, 18b. in the market
The majority of defects in MOS/ICs are due to dielectric breakdown of gate silicon oxide films other than MOS/FETs connected to input terminal 12.
本発明は前述従来技術の欠点に鑑み、MOS・
ICの全ての端子いずれに過電圧が印加された場
合でも、そのMOS型集積回路デバイスを絶縁破
壊から防止することにある。 In view of the drawbacks of the prior art described above, the present invention
The purpose is to prevent dielectric breakdown of the MOS type integrated circuit device even if an overvoltage is applied to any of the terminals of the IC.
本発明のMOS・ICは、前記の従来のMOSICの
性能を維持し、チツプサイズも同一でありなが
ら、MOS・ICの入力端子はもちろん電源端子お
よび出力端子の各端子に過電圧が印加されたとき
の該デバイスの破壊強度を大きくしたことが特徴
である。これをもう少し詳しく述べるp+nあるい
はn+p接合の降伏電圧はその高比抵抗側の不純物
濃度により決定されることは周知の事である。出
力あるいは電源端子に接続されたすべてのMOS
FETのソース及びドレイン電極とこの電極と極
性が反対のシリコン基板の間で形成される寄生的
なp+nあるいはn+p接合の降伏電圧（VBｊ）を該
MOS・FETのゲートシリコン酸化膜の絶縁破壊
電圧（Vox）よりも低く設定し、ドレインあるい
はソース電圧に隣接するチヤネル部分以外の高比
抵抗側シリコン基板表面付近の領域の不純物濃度
を、上記設定した接合の降伏電圧（VBｊ＜Vox）
を実現する値に、イオン注入、拡散等により不純
物をドープして作る。このようにして得られた
MOS・ICは、電源あるいは出力端子に過電圧が
印加されたとき、上記MOS・FETのドレインあ
るいはソース電極と異極性のシリコン基板との間
に形成されたp+nあるいはn+p接合が定電圧素子
として動作し、そのゲートシリコン酸化膜にはこ
れらの接合部の降伏電圧しか印加されない。これ
によつてMOS・FETすなわち、MOS・ICを過電
圧から保護したものである。 The MOS/IC of the present invention maintains the performance of the conventional MOSIC described above and has the same chip size. The device is characterized by increased breaking strength. To explain this in more detail, it is well known that the breakdown voltage of a p + n or n + p junction is determined by the impurity concentration on the high resistivity side. All MOS connected to output or power supply terminals
Determines the breakdown voltage (V B j) of the parasitic p + n or n + p junction formed between the source and drain electrodes of the FET and the silicon substrate with opposite polarity.
It is set lower than the dielectric breakdown voltage (Vox) of the gate silicon oxide film of the MOS/FET, and the impurity concentration in the region near the silicon substrate surface on the high resistivity side other than the channel part adjacent to the drain or source voltage is set as above. Junction breakdown voltage (V B j＜Vox)
It is made by doping impurities by ion implantation, diffusion, etc. to a value that achieves this. obtained in this way
When an overvoltage is applied to the power supply or output terminal of a MOS/IC, the p + n or n + p junction formed between the drain or source electrode of the MOS/FET and a silicon substrate of different polarity maintains a constant voltage. It operates as a device, and only the breakdown voltage of these junctions is applied to its gate silicon oxide film. This protects the MOS/FET, that is, the MOS/IC from overvoltage.
以下、第２図〜第４図に従つて本発明の一実施
例を詳述する。 Hereinafter, one embodiment of the present invention will be described in detail with reference to FIGS. 2 to 4.
第２図はMOS・ICのチツプ断面構造を示すも
ので、第３図はその等価回路を示すものである。
第２図において、２８はn-のシリコン基板を示
し、この基板２８にはn+、ｐ＋並びにp-の不純
物が拡散してある。すなわち、２４ａは基板２８
のp-形領域２９に、２４ｂはn-領域に拡散処理
したMOS・FETを示し、２２は夫々の
MOSFETのソース電極、２３はドレイン電極、
２１は夫々の電極に接合したAl配線、２５ａ，
２６ｂはゲートシリコン酸化膜、２６ａ，２６ｂ
はチヤネルを示しこの場合は２チヤネルを示して
いる。また、２７ａ，２７ｂ，２７ｃは高比抵抗
側ドープ領域（ｎ形領域）を示し、この高比抵抗
側ドープ領域２７ａ〜２７ｃの不純物濃度を本発
明においては適宜選定し、MOS・IC２４ａ，２
４ｂのシリコン酸化膜の絶縁破壊電圧より低い降
伏電圧を有するダイオードとして機能させてい
る。これを第３図の等価回路により説明する。 Figure 2 shows the cross-sectional structure of a MOS/IC chip, and Figure 3 shows its equivalent circuit.
In FIG. 2, reference numeral 28 denotes an n - silicon substrate, into which n + , p + and p - impurities are diffused. That is, 24a is the substrate 28
In the p - type region 29, 24b shows the MOS/FET diffused in the n -type region, and 22 shows the respective MOS/FETs.
MOSFET source electrode, 23 is drain electrode,
21 is an Al wiring connected to each electrode, 25a,
26b is a gate silicon oxide film, 26a, 26b
indicates a channel, and in this case indicates 2 channels. Further, 27a, 27b, and 27c indicate high resistivity side doped regions (n-type regions), and in the present invention, the impurity concentrations of these high resistivity side doped regions 27a to 27c are appropriately selected.
It functions as a diode having a breakdown voltage lower than the dielectric breakdown voltage of the silicon oxide film 4b. This will be explained using the equivalent circuit shown in FIG.
第３図において、第１図と同一符号を付してあ
るものは同一のものを示すものであるが、同実施
例においては、第１図の破壊で示す寄生的なダイ
オード１７を、実際に出力端子１９並びに電源端
子１２に印加された過電圧からMOS・FET１４
ａ，１４ｂを保護することのできる降伏電圧を有
するダイオード３７ａ〜３７ｃとして機能を果す
ようにしてある。すなわち、電源端子１２および
出力端子１９に接続された全てのMOS・FET２
４ａ，２４ｂのソース電極２２あるいはドレイン
電極２３と異極性のシリコン基板２８とのp+n接
合、およびp-形領域とのn+p接合による寄生ダイ
オードの耐圧VBｊを、このMOS・ICに使用され
るゲートシリコン酸化膜２５ａ，２５ｂの絶縁破
壊電圧Voxより低目に設定する。この設定した接
合の降伏電圧を与える高比抵抗側の不純物濃度
Ntを第４図より求める。すなわち、MOS・FET
のソース電極２２あるいはドレイン電極２３と隣
接するチヤネル部２６ａ，２６ｂを除いた異極性
の領域２７の不純物濃度を第４図に示すNtの値
にする。この結果、上記ソース電極２２あるいは
ドレイン電極２３を高濃度側領域としたシリコン
酸化膜の絶縁破壊電圧Voxより低い降伏電圧VB
を有するダイオード３７ａ〜３７ｃが得られる。 In FIG. 3, the same reference numerals as in FIG. MOS/FET 14 from overvoltage applied to output terminal 19 and power supply terminal 12.
The diodes 37a to 37c have a breakdown voltage capable of protecting the diodes 37a and 14b. In other words, all MOS/FET2 connected to the power supply terminal 12 and the output terminal 19
The withstand voltage V B j of the parasitic diode due to the p + n junction between the source electrode 22 or drain electrode 23 of 4a, 24b and the silicon substrate 28 of different polarity, and the n + p junction with the p - type region is determined by this MOS IC. The dielectric breakdown voltage Vox is set lower than the dielectric breakdown voltage Vox of the gate silicon oxide films 25a and 25b used for the gate silicon oxide films 25a and 25b. Impurity concentration on the high resistivity side that gives the breakdown voltage of this set junction
Find Nt from Figure 4. In other words, MOS・FET
The impurity concentration of the region 27 of different polarity excluding the channel portions 26a and 26b adjacent to the source electrode 22 or the drain electrode 23 is set to the value Nt shown in FIG. As a result, the breakdown voltage V
Diodes 37a to 37c having the following values are obtained.
したがつて、このようにして得られたMOSIC
は、電源端子１２あるいは出力端子１９に過電圧
が印加されたとき、上記MOS・FET２４ａ，２
４ｂのドレイン電極２３、ソース電極２２と異極
性のシリコン基板２８並びにp-領域２９との間
に形成されたp+nあるいはn+p接合で成る保護ダ
イオード３７ａ〜３７ｃが定電圧素子として動作
し、その結果、MOS・FET２４ａ，２４ｂのゲ
ートシリコン酸化膜には、これらの接合部の降伏
電圧しか印加されず、MOS・FETすなわち
MOS・ICは入力端子１１より印加される過電圧
はもちろん、出力端子１９並びに電源端子１２か
らの過電圧からも保護される。 Therefore, the MOSIC obtained in this way
When an overvoltage is applied to the power supply terminal 12 or the output terminal 19, the MOS/FETs 24a, 2
Protection diodes 37a to 37c, which are p + n or n + p junctions, formed between the drain electrode 23 and source electrode 22 of 4b, the silicon substrate 28 of different polarity, and the p - region 29 operate as constant voltage elements. As a result, only the breakdown voltage of these junctions is applied to the gate silicon oxide films of the MOS/FETs 24a and 24b, and the MOS/FETs, that is,
The MOS IC is protected not only from overvoltage applied from the input terminal 11 but also from overvoltage from the output terminal 19 and the power supply terminal 12.
なお、上記の不純物濃度を第４図のNt値とす
る領域（ダイオード形成２７）はMOS・FETの
チヤネル部２６の領域とは異なる部位にあり、
MOS・FETの特性を害することはない。 Note that the region (diode formation 27) where the above impurity concentration has the Nt value in FIG.
It does not harm the characteristics of MOS/FET.
上述の実施例からも明らかなように本発明によ
れば、従来のMOS・ICの性能を維持し、かつチ
ツプサイズを大きくすることなく、MOS・ICの
各端子に過電圧が印加されたときの該デバイスの
破壊強度を大きくとることができ、過電圧印加に
よるMOS・FETのゲートシリコン酸化膜の絶縁
破壊を確実に防止できる。 As is clear from the above-mentioned embodiments, the present invention maintains the performance of conventional MOS/IC and eliminates the problem when overvoltage is applied to each terminal of MOS/IC without increasing the chip size. The breakdown strength of the device can be increased, and dielectric breakdown of the gate silicon oxide film of MOS/FET due to overvoltage application can be reliably prevented.
第１図は従来のMOS・ICの入力端子に接続さ
れたMOS・FETのゲートシリコン酸化膜の保護
回路を示す図、第２図は本発明によるMOS・IC
のチツプ断面構造を示す図であつて、第３図は第
２図の等価回路、第４図はp+nおよびn+p接合の
高比抵抗側の不純物濃度とその降伏電圧の関係を
示す図である。
１１……入力端子、１２……電源端子、１３…
…接地端子、１４ａ，１４ｂ，１８ａ，１８ｂ，
２４ａ，２４ｂ……MOS・FET、１５……入力
保護抵抗、１６……入力保護ダイオード、１９…
…出力端子、２０……Al配線、２２……ソース
電極、２３……ドレイン電極、２５ａ，２５ｂ…
…ゲートシリコン酸化膜、２６ａ，２６ｂ……
FETのチヤネル部、２７ａ〜２７ｃ……高比抵
抗側ドープ領域、２８……シリコン基板、２９…
…p-形領域（ウエル）３７ａ〜３７ｃ……電源、
出力端子用の保護ダイオード。
Figure 1 shows a protection circuit for the gate silicon oxide film of a MOS/FET connected to the input terminal of a conventional MOS/IC, and Figure 2 shows a MOS/IC according to the present invention.
Fig. 3 shows the equivalent circuit of Fig. 2, and Fig. 4 shows the relationship between the impurity concentration on the high resistivity side of the p + n and n + p junctions and their breakdown voltage. It is a diagram. 11...Input terminal, 12...Power terminal, 13...
...Ground terminal, 14a, 14b, 18a, 18b,
24a, 24b...MOS/FET, 15...Input protection resistor, 16...Input protection diode, 19...
...output terminal, 20...Al wiring, 22...source electrode, 23...drain electrode, 25a, 25b...
...Gate silicon oxide film, 26a, 26b...
FET channel portion, 27a to 27c...high resistivity side doped region, 28...silicon substrate, 29...
...p - shaped area (well) 37a to 37c...power supply,
Protection diode for output terminal.
Claims (1)
出力端子に接続される全てのMOS・FETのドレ
イン電極およびソース電極のp+形あるいはn+形
領域の不純物濃度と、これら両電極とは逆極性
で、前記MOS・FETのチヤネル部を含まない電
極近傍のｎ形あるいはｐ形領域の不純物濃度とに
よつて決まるp+nあるいはn+p接合の降伏電圧を、
前記、MOS・FETのゲートシリコン酸化膜の絶
縁破壊電圧より低く設定し、ｎ形あるいは、ｐ形
領域の不純物濃度をその設定した降伏電圧を実現
できる不純物濃度とし、前記MOS型集積回路デ
バイスの出力端子および電源端子に接続される全
てのMOS・FETのゲート酸化膜に対し、過電圧
保護がなされるようにしたことを特徴とする
MOS型集積回路デバイス。1 The impurity concentration of the p + type or n + type region of the drain electrode and source electrode of all MOS/FETs connected to the power supply terminal and output terminal of the MOS type integrated circuit device, and the polarity of these two electrodes are opposite, The breakdown voltage of the p + n or n + p junction, which is determined by the impurity concentration of the n-type or p - type region near the electrode that does not include the channel part of the MOS/FET, is
The output of the MOS type integrated circuit device is set lower than the dielectric breakdown voltage of the gate silicon oxide film of the MOS/FET, and the impurity concentration of the n-type or p-type region is set to an impurity concentration that can realize the set breakdown voltage. It is characterized by overvoltage protection for the gate oxide films of all MOS/FETs connected to terminals and power supply terminals.
MOS type integrated circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7773680A JPS574151A (en) | 1980-06-11 | 1980-06-11 | Mos integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7773680A JPS574151A (en) | 1980-06-11 | 1980-06-11 | Mos integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS574151A JPS574151A (en) | 1982-01-09 |
| JPS6360547B2 true JPS6360547B2 (en) | 1988-11-24 |
Family
ID=13642186
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7773680A Granted JPS574151A (en) | 1980-06-11 | 1980-06-11 | Mos integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS574151A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58159363A (en) * | 1982-03-17 | 1983-09-21 | Nec Corp | Input/output protecting device for semiconductor integrated circuit |
| JPS5969957A (en) * | 1982-10-15 | 1984-04-20 | Nec Corp | Protective device for output |
| JPS59191371A (en) * | 1983-04-14 | 1984-10-30 | Nec Corp | Complementary type metal oxide semiconductor field-effect device |
| JPS6010767A (en) * | 1983-06-30 | 1985-01-19 | Fujitsu Ltd | Semiconductor device |
| JP2508826B2 (en) * | 1987-11-24 | 1996-06-19 | 日本電気株式会社 | Semiconductor device |
| JP2009099679A (en) * | 2007-10-15 | 2009-05-07 | Mitsumi Electric Co Ltd | Mos transistor, and semiconductor integrated circuit device using the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55132065A (en) * | 1979-04-02 | 1980-10-14 | Sharp Corp | Cmos circuit |
-
1980
- 1980-06-11 JP JP7773680A patent/JPS574151A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55132065A (en) * | 1979-04-02 | 1980-10-14 | Sharp Corp | Cmos circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS574151A (en) | 1982-01-09 |
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