JPS59191371A - Complementary type metal oxide semiconductor field-effect device - Google Patents
Complementary type metal oxide semiconductor field-effect deviceInfo
- Publication number
- JPS59191371A JPS59191371A JP58065824A JP6582483A JPS59191371A JP S59191371 A JPS59191371 A JP S59191371A JP 58065824 A JP58065824 A JP 58065824A JP 6582483 A JP6582483 A JP 6582483A JP S59191371 A JPS59191371 A JP S59191371A
- Authority
- JP
- Japan
- Prior art keywords
- diode
- resistance
- drain
- diodes
- protection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
Abstract
Description
【発明の詳細な説明】
本発明はＭＯ８集積回路、特に相補型ＭＯ８（０ＭＯ８
）構造を有する外積回路の保護装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to MO8 integrated circuits, particularly complementary MO8 (0MO8) integrated circuits.
) structure for an outer product circuit.
ＭＯ８集積回路の入力端子は通常ＭＯＳトランジスタの
ゲート電極に接続されておシ、静電気による高電圧から
ゲート酸化膜を保護するため各種の保護回路が実用化さ
れている。特に、ＣＭＯ８集積回路の場合には、静電気
による影響のみならず、寄生ＰＮＰＮ効果によるラッチ
アップ現象に対する考慮が必要である。すなわち、出力
端子（もしくは電源端子）に異常な電位が加わることに
よってＮ型基板とＰウェルとの間の接合に順方向電流が
流れ、この電流がＰチャンネルＭＯ８ＦＥＴのドレイｙ
−基板−ｐウェルーＮチャンネルＭＯ８ＦＥＴのドレイ
ンで寄生的に構成されるＰＮＰＮサイリスタをトリガー
してしまう現象である。The input terminal of an MO8 integrated circuit is usually connected to the gate electrode of a MOS transistor, and various protection circuits have been put into practical use to protect the gate oxide film from high voltage caused by static electricity. In particular, in the case of a CMO8 integrated circuit, it is necessary to consider not only the effects of static electricity but also the latch-up phenomenon caused by parasitic PNPN effects. In other words, when an abnormal potential is applied to the output terminal (or power supply terminal), a forward current flows through the junction between the N-type substrate and the P-well, and this current flows through the drain y of the P-channel MO8FET.
- Substrate - P-well - This is a phenomenon that triggers the PNPN thyristor parasitically constructed at the drain of the N-channel MO8FET.
以下に、近年の微細加工技術の進展を背景とする集積密
度の向上に、性能および機能の多様化の動向において、
従来の保護回路のもつ問題点を示し、同時に本発明のよ
り具体的な目的を述べる。Below, we will discuss the trends in performance and function diversification as well as improvements in integration density against the background of recent advances in microfabrication technology.
Problems with conventional protection circuits will be shown, and at the same time, more specific objectives of the present invention will be described.
従来、各種の保護装置が実用化されているが、集＠度の
向上に伴い、ゲート酸化膜厚およびトランジスタを構成
する不純物層の厚さが著しく減少し、保護装置の重要性
が増大している。たとえば、微細加工プロセスによる入
力保護装置は、保護装置を構成する不純物層が浅いため
、入力保護装置自体の静電気による破壊が問題となる。Conventionally, various protection devices have been put into practical use, but with the improvement in density, the thickness of gate oxide films and the thickness of impurity layers that make up transistors have decreased significantly, and the importance of protection devices has increased. There is. For example, in an input protection device manufactured by a microfabrication process, since the impurity layer constituting the protection device is shallow, damage to the input protection device itself due to static electricity becomes a problem.
またＭＯ８集積回路の出力端子は通常ＭＯＳトランジス
タのドレインに接続されるため、従来は特別な採種をし
なくとも実用上充分な静電気破壊耐量が確保されていた
が、微細加工の進展によシ、出力ドレイン接合の破壊１
直が低下し、特別な考慮が必要となった。In addition, since the output terminal of an MO8 integrated circuit is usually connected to the drain of a MOS transistor, it used to be possible to ensure sufficient electrostatic breakdown resistance for practical use without any special seeding, but with advances in microfabrication, Destruction of output drain junction 1
The stability was reduced and special consideration was required.
本発明の第１の目的は、この様な微細加工プロセスによ
多形成される集積回路の入力および出力の保護装置を実
現することにある。A first object of the present invention is to realize an input and output protection device for an integrated circuit formed by such a microfabrication process.
一般に静電破壊に対する保護装置は、高抵抗とダイオー
ド又はトランジスタの組合せによシ構成される。第１図
に従来の入力保護回路の例を示す。Generally, protection devices against electrostatic discharge damage are constructed from a combination of high resistance and diodes or transistors. FIG. 1 shows an example of a conventional input protection circuit.
第１図の回路では、抵抗只の抵抗値は通常１〜２Ωが用
いられ、静電ストレスを緩和すると同時に入力に過電圧
が印加された場合の入力電流の制限がはかられている。In the circuit shown in FIG. 1, the resistance value of the resistor is usually 1 to 2 Ω, which is intended to alleviate electrostatic stress and at the same time limit the input current when an overvoltage is applied to the input.
抵抗Ｒの出力側には電源ＶＤＤとＶＳ３との間にそれぞ
れ逆方向接続されたダイオードＤ、、 、 Ｄ７．が接
続されている。しかし、この様な方式、すなわち高抵抗
を用いる入力保護は今日のＩＣの多様な用途、性能の上
で充分なものではない。On the output side of the resistor R, there are diodes D, , , D7, connected in opposite directions between the power supplies VDD and VS3, respectively. is connected. However, this type of input protection using high resistance is not sufficient for the various uses and performances of today's ICs.
第１の問題は、最近実用化の途にある高速ＣＭＯＳロジ
ックＩＣへの応用である。高速ＣＭＯＳロジックの特に
ゲート品種においては、入力系路に挿入される高抵抗に
よる入力信号の時間的遅れが、ＩＣ全体の遅延の数１０
％に達し、大きな損失となる。第２の問題は、前述の出
力に対する保護としては、高抵抗値を用いること自体が
できない点である。すなわち、高抵抗値によって出力電
圧の損失が生じ、実際に得られる出力電圧が低下してい
た。このため、ＩＣの性能が大きくそこなわれる。The first problem is the application to high-speed CMOS logic ICs, which are currently in the process of being put into practical use. In high-speed CMOS logic, especially gate types, the time delay of the input signal due to the high resistance inserted in the input path is several tens of times the delay of the entire IC.
%, resulting in a large loss. The second problem is that a high resistance value cannot be used as protection against the above-mentioned output. In other words, a high resistance value causes a loss in output voltage, resulting in a decrease in the actually obtained output voltage. As a result, the performance of the IC is greatly impaired.
本発明の第２の目的は、入力に対する保護にも、出力に
対する保護にも適用でき、また高速ＣＭＯＳロジックへ
の応用も可能な高抵抗を用いない保護装置を実用化する
ことである。この点は、新しいＬＳＩの製造システムと
して注目を集めているゲートアレイ方式においては保護
装置は配線前の基板にあらかじめ形成されており、さら
に入力と出力に割シ当てられる端子が決まっていないた
め、入力と出力の保護装置を同一の構成とすることが都
合が良い。A second object of the present invention is to put into practical use a protection device that does not use high resistance and can be applied to both input protection and output protection, and can also be applied to high-speed CMOS logic. In this respect, in the gate array method, which is attracting attention as a new LSI manufacturing system, the protection device is pre-formed on the board before wiring, and furthermore, the terminals assigned to inputs and outputs are not determined. It is advantageous for the input and output protection devices to have the same configuration.
次にＣＭＯ８構造をもつＩＣに重要な、ラッチアップに
対する保護において、従来の保護思想は満足できるもの
ではなかった。一般にＣＭＯ８ＩＣのラッチアップには
３つのモードが知られている。Next, with respect to protection against latch-up, which is important for ICs having a CMO8 structure, conventional protection ideas have not been satisfactory. Generally, three modes are known for latch-up of CMO8IC.
第１は出力端子からのトリガによるもの、第３は電源間
に高電圧のノイズパルスが印加される場合である。従来
の保護思想は、第１のモードに対しては、出力のＰチャ
ネルトランジスタブロックとＮチャネルトランジスタブ
ロックを分離し、ＮチャネルトランジスタブロックのＰ
ウェルとＮ壓基板およびＰチャネルトランジスタのソー
スで構成されるＰＮＰ寄生トランジスタの寛流垢巾率を
低下させることであった。このためにＰチャネルシトラ
ンジスタブロックとＮチャネルトランジスタブロックの
間隔を拡げ平面的に分離する方法とか、間隔を実効的に
広げるために両ブロック間に電源電位に固定され九Ｐ＋
領域あるいは１−領域を設置し、またその深さを制御す
るなどの多くの工夫が公知である。しかしながら結局の
ところ工程が複雑になったり、ペレット面積が大きくな
る等の欠点がある。また高抵抗を用いることは避けるべ
きものである。The first case is due to a trigger from the output terminal, and the third case is when a high voltage noise pulse is applied between the power supplies. The conventional protection concept for the first mode is to separate the output P-channel transistor block and N-channel transistor block, and to
The objective was to reduce the current clearance rate of a PNP parasitic transistor consisting of a well, an N-type substrate, and a source of a P-channel transistor. For this purpose, there are methods to increase the distance between the P-channel transistor block and the N-channel transistor block and separate them in a plane, and to effectively widen the distance between the two blocks, the power supply potential is fixed to 9P+.
Many techniques are known, such as setting a region or one-region and controlling its depth. However, there are drawbacks such as the process becomes complicated and the pellet area becomes large. Also, use of high resistance should be avoided.
第２のモードに対し、現在検討されている対策は、エピ
タキシャル基板あるいけ埋込み層の導入によるシリーズ
抵抗の低減とか、極めて細い溝による分離であるが、こ
れらも原価が割高とならざるを得す、安価に信頼性の高
いＩＣを提供することができなし１゜
従って、本発明の第３の目的は、保護装置の適切な構成
によシ、内部回路に依存せずラッチアップ耐量を確保す
ることである。Countermeasures currently being considered for the second mode include reducing the series resistance by introducing a buried layer in the epitaxial substrate, and separating by extremely thin grooves, but these also have to be expensive. Therefore, the third object of the present invention is to ensure latch-up resistance without depending on the internal circuit by appropriately configuring the protection device. That's true.
本発明の特徴は、入力端子と電源端子間に内部のＭＯＳ
）ランリスタのソース・ドレイン間耐圧より逆方向耐圧
の低い第１の保護ダイオードを挿入することおよび出力
端子および電源端子間Ｉ／ｃ２棟の異なる特性を有する
ダイオードを並列に接続することとであり、２種のダイ
オードを内部のＭＯＳトランジスタのソース・ドレイン
間耐圧よシ低い耐圧を有するダイオードと、よシ高耐圧
のダイオードとすることである。The feature of the present invention is that an internal MOS is connected between the input terminal and the power supply terminal.
) Inserting a first protection diode with a reverse breakdown voltage lower than the source-drain breakdown voltage of the Lanristor, and connecting in parallel diodes with different characteristics for the two I/C blocks between the output terminal and the power supply terminal, The two types of diodes are one having a lower breakdown voltage than the source-drain breakdown voltage of the internal MOS transistor and the other having a higher breakdown voltage.
以下に図面を参照し本発明の詳細な説明する。The present invention will be described in detail below with reference to the drawings.
第２図は本発明による第１の実施例で、ＣＭＯＳインバ
ータに適用した場合である。図において、Ｑｌはインバ
ータを構成するＰチャネルトランジスタ、Ｑ２ＨＮチャ
ネルトランジスタ、Ｄｉ、Ｄ２゜Ｄ３．Ｄ４．Ｄ５は逆
方向耐圧がトランジスタのソース・ドレイン間耐圧よシ
低いダイオード特に逆方向でレイクダウン領域で安定し
た導電が可能である意味でツェナーダイオードの記号を
用いたまだ、Ｄ６．Ｄ７．Ｄ８．Ｄ９．Ｄｌｏは逆方向
耐圧がトランジスタのソース・ドレイン間耐圧よシ高９
ダイオード、Ｄｌｌ、Ｄｌ２．Ｄ１３１ｄＣＭＯ８構造
に寄生するダイオードである。FIG. 2 shows a first embodiment of the present invention, which is applied to a CMOS inverter. In the figure, Ql is a P channel transistor constituting an inverter, Q2HN channel transistor, Di, D2°D3 . D4. D5 is a diode whose reverse breakdown voltage is lower than the source-drain breakdown voltage of a transistor.The symbol of Zener diode is used to mean that stable conduction is possible in the breakdown region, especially in the reverse direction.D6. D7. D8. D9. Dlo has a reverse breakdown voltage that is higher than the source-drain breakdown voltage of the transistor9.
Diode, Dll, Dl2. D131dThis is a diode parasitic to the CMO8 structure.
まず静電破壊に対する上記ダイメートの効果を示す。Ｃ
ＭＯＳ インバータの入力端子Ａに印加される静電破
壊が問題となるのは、次の４つのケースを典捜的なモデ
ルとすることができる。印加される電圧が正又は負、接
地されると考えられる電源端子がＶＤＤ又はＶＳＳで他
方は開放状態である場・合の組合せである。これらをそ
れぞれ対ＶＤＤ正。First, we will show the effect of the above-mentioned Dimate on electrostatic discharge damage. C
The following four cases can be considered as standard models in which electrostatic discharge damage applied to the input terminal A of a MOS inverter becomes a problem. This is a combination in which the applied voltage is positive or negative, the power supply terminal considered to be grounded is VDD or VSS, and the other is in an open state. These are respectively vs. VDD positive.
対■ＤＤ負、対ＶＳＳ正、対ＶＳＳ負と略記することと
する。尚電源端子ＶＤＤおよびＶＳＳがいづれも接地又
は電源電位を与えられている時には、入力端子Ａの静電
荷はダイオードＤＩ、Ｄ６又はダイオードＤ２．Ｄ７の
いづれか順方向バイアスとなる方を介して放電されるの
で問題はない。They will be abbreviated as vs. DD negative, vs. VSS positive, and vs. VSS negative. Note that when power supply terminals VDD and VSS are both grounded or supplied with a power supply potential, the static charge at input terminal A is transferred to diodes DI, D6 or diode D2. There is no problem because the discharge is carried out through whichever of D7 is forward biased.
まず、対ＶＤＤ正の静電荷が存在する場合、ＶＤＤ側に
接続されたダイオードＤ１およびＤ６が順方向となシ、
これらのダイオードを介して静電エネルギーの放出が行
なわれ実用上充分な破壊耐量が確保される。次に対ＶＤ
Ｄ負の静電荷が存在する場合はダイオードＤ１およびＤ
６が逆バイアスされるが、ダイオードＤ６の逆方向耐圧
が低いため、ダイオードＤ６を通して静電荷が流れる。First, if there is a positive static charge with respect to VDD, the diodes D1 and D6 connected to the VDD side are in the forward direction.
Electrostatic energy is discharged through these diodes, and a practically sufficient breakdown strength is ensured. Next vs. VD
D If a negative electrostatic charge is present, the diodes D1 and D
6 is reverse biased, but since the reverse breakdown voltage of the diode D6 is low, static charges flow through the diode D6.
ダイオードＤ６を逆方向ブレイクダウン領域で安定した
導電が可能なダイオードとすることによシ、この時の破
壊耐量を向上させることができる。ダイオードＤ６の耐
圧としては、ゲート酸化膜の絶縁破壊耐力〜７ Ｘ １
０’Ｖ／ｃｒｒＬを考慮する必要があるが、数１０ＯＡ
以上のゲート酸化膜に対しては内部のＭＯＳ）ランリス
タのソース・ドレイン間耐圧よシ低くしておくと問題な
い。特に後述のラッチアップ耐量向上のためには内部の
ＭＯＳ）ランリスタのソース・ドレイン間耐圧よシ低く
しておく必要があり、製造上も同じ構成にするとゲート
アレイ製品等のように保護ダイオードを入力保護として
も出力保護としても使いたい場合に有利である。By making the diode D6 a diode capable of stable conduction in the reverse breakdown region, the breakdown resistance at this time can be improved. The breakdown voltage of the diode D6 is the dielectric breakdown strength of the gate oxide film ~7 x 1
It is necessary to consider 0'V/crrL, but several tens of OA
For the above gate oxide film, there is no problem if the breakdown voltage between the source and drain of the internal MOS (Run Lister) is made lower than that. In particular, in order to improve the latch-up resistance (described later), it is necessary to lower the withstand voltage between the source and drain of the internal MOS (MOS) runlister, and if the same configuration is used in manufacturing, a protection diode will be input as in gate array products. This is advantageous when you want to use it both as protection and as output protection.
この点従来の′入力保護装置においては、ダイオードの
順方向’ｌで保護していたので、ダイオードＤ６に相当
する逆方向特性が考慧されたダイオードが存在しないた
め特に負ストレスに対する耐量が劣っていた。In this regard, in conventional input protection devices, protection was provided by the forward direction of the diode, and as there was no diode that was designed with reverse characteristics equivalent to diode D6, the ability to withstand negative stress was particularly poor. Ta.
以上ＶＤＤに対する正、負ストレスが印加された場合を
説明したが、対Ｖ８ＳストレスについてもダイオードＤ
２．Ｄ７が前述のＤｌ、Ｄ６と同様の役割を果す。また
出力側の保護回路についても同様の効果があることはい
うまでもない。尚、静電破壊防止のためだけの場合、特
に入力保護に対してはダイオードＤＩ 、 Ｄ７ は
あえて必要はない。ただ設けておくと、入力保護として
も利用でき、出力保護としても利用できるのでゲートア
レイ製品に便利である。The case where positive and negative stresses are applied to VDD has been explained above, but the diode D
2. D7 plays the same role as Dl and D6 described above. It goes without saying that the output side protection circuit also has a similar effect. It should be noted that the diodes DI and D7 are not necessary for the purpose of preventing electrostatic discharge damage, especially for input protection. However, if provided, it can be used as input protection and output protection, which is convenient for gate array products.
次にラッチアップ現象を制限する効果について述べる。Next, the effect of limiting the latch-up phenomenon will be described.
たとえば出力端子ＹＫ電源電圧以上の過電圧が印加され
る場合、ダイオードＤ３．Ｄ８および寄生ダイオードＤ
１２が順方向にバイアスされて電流が流れる。出力側に
ラッチアップが誘起される原因は、出力トランジスタに
寄生するダイオードＤ１２に大′亀流が流れることによ
る。しかし本発明によるダイオードＤ８ 、 Ｄ９
の耐圧は内部のソース・ドレイン間耐圧よシ高く、いい
かえればＰＮ接合のビルトインポテンシャルが低く順方
向電圧が寄生ダイオードＤ１２．Ｄ１３よυ低く設計さ
れてお９、出力端子よシ流入する電流が比較的小さい時
は、電流はすべてダイオードＤ８を通ってＶＤＤに放出
されラッチアップを起こさない。電流が大きくなりダイ
オードＤ８のシリーズ抵抗のため、寄生ダイオードＤ１
２にも電流が流れはじめると通常の場合と同様にラッチ
アップに至ると考えられるがダイオードＤ８のバイパス
効果によりラッチアップ耐電流は大巾に向上する。すな
わち、耐圧の低いダイオードＤ３ 、 Ｄ４ のみの
場合には高不純物濃度の接合で形成されるが、この時順
方向電圧は高くなる。従って、順方向バイアス時にダイ
オードＤ８．Ｄ９がないと電流はダイオードＤ３．Ｄ４
ではなく寄生ダイオードＤＩ ２ 、 Ｄｉ３を通して
流れてしまう。この点耐圧の高いダイオードＤ８．Ｄ９
の順方向電圧は寄生ダイオードＤ１２゜Ｄｉ３の順方向
電圧よシ低く、順方向バイアス時有効にラッチアップを
防止できる。For example, when an overvoltage higher than the output terminal YK power supply voltage is applied, the diode D3. D8 and parasitic diode D
12 is forward biased and current flows. The reason why latch-up is induced on the output side is that a large current flows through the diode D12 parasitic to the output transistor. However, the diodes D8, D9 according to the invention
The breakdown voltage of D12. It is designed to be lower than D139, and when the current flowing into the output terminal is relatively small, all the current is discharged to VDD through diode D8 and no latch-up occurs. As the current increases and due to the series resistance of diode D8, parasitic diode D1
When current begins to flow through the diode D8, it is thought that latch-up will occur as in the normal case, but the latch-up withstand current is greatly improved due to the bypass effect of the diode D8. That is, in the case of only diodes D3 and D4 having a low breakdown voltage, a junction with a high impurity concentration is formed, but in this case, the forward voltage becomes high. Therefore, when forward biased, diode D8. Without D9, the current flows through diode D3. D4
Instead, it flows through the parasitic diodes DI 2 and Di3. In this respect, the diode D8. has a high withstand voltage. D9
The forward voltage of the parasitic diode D12°Di3 is lower than that of the parasitic diode D12°Di3, and latch-up can be effectively prevented during forward bias.
次に電源間に過電圧が印加された場合の効果について述
べる。この場合に重要な保護装置は、本発明によるダイ
オードＤ５である。ダイオードＤ５の耐圧は内部トラン
ジスタのソース・ドレイン間耐圧よシ低く、又ＩＣの使
用電源電圧より高く設定されなければならない。Next, we will discuss the effect when overvoltage is applied between power supplies. An important protection device in this case is the diode D5 according to the invention. The breakdown voltage of the diode D5 must be set lower than the source-drain breakdown voltage of the internal transistor and higher than the power supply voltage used by the IC.
今日の４μルール又は３μルールにおいて設計されたＳ
ｉゲー）０ＭＯ８ＩＣのＰチャネルトランジスタおよび
Ｎチャネルトランジスタの耐圧は通常１５〜２０Ｖｅ度
であり、Ｎチャネルトランジスタに大きな電流を流しだ
場合のサスティン電圧は１０〜１２Ｖ程度である。また
ＩＣ使用時の電源電圧として１ｄ５Ｖが通常用いられる
ので、ダイオードＤ５の耐圧は６ｖ〜ＩＯＶの範囲に設
定するのが望ましい。このクランプダイオードＤ５によ
シ、電源間の過電圧はダイオードＤ５の耐圧でクランプ
され、内部のどのトランジスタもブレイクダウンに至ら
ず、ラッチアップが防止される。S designed in today's 4μ rule or 3μ rule
The breakdown voltage of the P-channel transistor and N-channel transistor of i-game) 0 MO8 IC is usually 15 to 20 Ve degrees, and the sustain voltage when a large current is passed through the N-channel transistor is about 10 to 12V. Further, since 1d5V is normally used as the power supply voltage when using an IC, it is desirable to set the withstand voltage of the diode D5 in the range of 6V to IOV. This clamp diode D5 clamps the overvoltage between the power supplies to the withstand voltage of the diode D5, preventing any internal transistor from breaking down and preventing latch-up.
尚、ダイオードＤ１０！−ｔラッチアップ防ｔ［Ｉｄそ
れほど有効でなく、なくても良いが、ゲートアレイ製品
等保護装置の用途が定まらないものにあっては設けてお
く方が便利である。In addition, diode D10! -t Latch-up prevention t[Id Although it is not so effective and may not be necessary, it is convenient to provide it for products such as gate array products where the use of the protection device is uncertain.
以上の低耐圧のダイオードＤＩ、Ｉ）２．Ｄ３．Ｄ４゜
Ｄ５はＳ！ゲートＣＡ４０ＳＩＣの通常の工種１で容易
に形成フ”ることかできる。ＳｉゲートＣＭＯ８ＩＣの
通常の工程に従いＰウェルを形成后、Ｐ原子をたとえば
エネルギー５０に’ｅｖでドーズ量４Ｘ１０１ａ儂 〜
２ Ｘ １０”ｃｍ−２をイオン注入し、引きつづき１
１５０℃１時間の熱処理を行なう。以後は通常の工程に
よ、９ＣＭＯ８ＩＣを形成する。この時、上記の条件に
よって形成されたＮ型不純物層とＰチャネルトランジス
タのソースおよびドレインと同時罠形成されるＰ１型不
純物層とによって実現されるＰＮ接合は本発明に関する
低耐圧ダイオードの要件を満たず。この時のＰＮ接合付
近のＮ型不純物ｄＫは２ Ｘ １０１７ｃｍ、−”であ
る。Low breakdown voltage diode DI, I) 2. D3. D4゜D5 is S! It can be easily formed using the usual process 1 for gate CA40SIC.After forming the P well according to the usual process for Si gate CMO8IC, P atoms are heated to an energy of 50'EV at a dose of 4X101a~.
Ion implantation of 2 x 10”cm-2 followed by 1
Heat treatment is performed at 150° C. for 1 hour. Thereafter, 9CMO8IC is formed by normal steps. At this time, the PN junction realized by the N-type impurity layer formed under the above conditions and the P1-type impurity layer formed simultaneously with the source and drain of the P-channel transistor satisfies the requirements for a low voltage diode according to the present invention. figure. At this time, the N-type impurity dK near the PN junction is 2 x 1017 cm, -''.
以上説明したように、本発明による入力保護装置は微細
加工プロセスによる８ｉゲ一トＣＭＯ８ＩＣの静電スト
レス耐量の向上、ラッチアップ耐量の向上に有用であり
、しかも１工程を追加するだけで容易に形成される利点
をもつ、したがって安価で信頼性の窩いＩＣを提供する
ことができる。As explained above, the input protection device according to the present invention is useful for improving the electrostatic stress resistance and latch-up resistance of 8i gate CMO8IC through microfabrication process, and can be easily achieved by adding one process. It is therefore possible to provide an inexpensive and reliable cavity IC having the advantage of being formed.
なお、実施例において最も単純なＣＭＯ８インバータを
例としたが、内部回路がいかに複雑かつ大規模な回路で
あっても本発明による効果があることはいうまでもない
。Although the simplest CMO8 inverter is used as an example in the embodiment, it goes without saying that the effects of the present invention can be obtained no matter how complex and large-scale the internal circuit is.
第１図は従来の入力保護装置の回路図である、第２図は
本発明による入力保護回路を示す回路図である。
Ｑｌ・・・・・・インバータを構成するＰチャネルトラ
ンジスタ、Ｑ２・・・・・・インバータを構成するＮチ
ャネルトランジスタ、Ｄｉ 、 Ｄ２ 、 Ｄ３ 、
Ｄ４ 、 Ｄ５・・・・・・低耐圧のダイオード、Ｄ６
．Ｄ７．Ｄ８．Ｄ９．Ｄｌｏ・・・・・・高耐圧のダイ
オード、Ｄｌｌ、Ｄｉ２．Ｄｉ３・・・・・・ＣＭＯＳ
構造に寄生するダイオード。FIG. 1 is a circuit diagram of a conventional input protection device, and FIG. 2 is a circuit diagram showing an input protection circuit according to the present invention. Ql... P-channel transistor forming the inverter, Q2... N-channel transistor forming the inverter, Di, D2, D3,
D4, D5...Low breakdown voltage diode, D6
．． D7. D8. D9. Dlo...High voltage diode, Dll, Di2. Di3...CMOS
A diode parasitic to the structure.
Claims (1)
ドレイン間耐圧よシも低い逆方向耐圧をもつダイオード
を保護装置として用いたことを特徴とする相補型ＭＯ８
電界効実装置。 ２）前記保護装置は入力を保護するのに使用される特許
請求の範囲第１項記載の相補型ＭＯ８電界効実装置。 ３）前記保護ダイオードは前記ダイオードと並列に前記
ＭＯ８電界効果トランジスタのソース・ドレイン間耐圧
より高い逆方向耐圧をもつダイオードを接続してなる特
許請求の範囲第１項記載の相補型ＭＯ８ｔ界効実装置。 ４）前記保瞼ダイオードは出力を保護するのに使用され
る特許請求の範囲第１項記載の相補型ＭＯ８電界効実装
置。[Claims] 1) MO8 field effect transistor source used
Complementary MO8 characterized in that a diode with a reverse breakdown voltage that is lower than the drain-to-drain breakdown voltage is used as a protection device.
Field effect device. 2) A complementary MO8 field effect device according to claim 1, wherein said protection device is used to protect an input. 3) The complementary MO8t field effect transistor according to claim 1, wherein the protection diode is a diode having a reverse breakdown voltage higher than the source-drain breakdown voltage of the MO8 field effect transistor connected in parallel with the diode. Device. 4) The complementary MO8 field effect device of claim 1, wherein the eyelid protection diode is used to protect the output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58065824A JPS59191371A (en) | 1983-04-14 | 1983-04-14 | Complementary type metal oxide semiconductor field-effect device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58065824A JPS59191371A (en) | 1983-04-14 | 1983-04-14 | Complementary type metal oxide semiconductor field-effect device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59191371A true JPS59191371A (en) | 1984-10-30 |
| JPH0313754B2 JPH0313754B2 (en) | 1991-02-25 |
Family
ID=13298157
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58065824A Granted JPS59191371A (en) | 1983-04-14 | 1983-04-14 | Complementary type metal oxide semiconductor field-effect device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59191371A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02150072A (en) * | 1988-11-30 | 1990-06-08 | Fuji Electric Co Ltd | Semiconductor device using input protecting circuit |
| EP0637843A1 (en) * | 1993-08-06 | 1995-02-08 | STMicroelectronics S.A. | Integrated circuit protection against electrostatic discharges |
| US5936288A (en) * | 1997-07-08 | 1999-08-10 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device and low breakdown voltage zener diode |
| JP2020080500A (en) * | 2018-11-14 | 2020-05-28 | ローム株式会社 | Driver circuit |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102607375A (en) * | 2012-03-22 | 2012-07-25 | 王建 | Radial play measuring device for bearing |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51147187A (en) * | 1975-06-12 | 1976-12-17 | Fujitsu Ltd | Semiconductor device |
| JPS5491067A (en) * | 1977-12-28 | 1979-07-19 | Nec Corp | Input protective circuit |
| JPS574151A (en) * | 1980-06-11 | 1982-01-09 | Hitachi Ltd | Mos integrated circuit device |
| JPS58162054A (en) * | 1982-03-19 | 1983-09-26 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| JPS58197870A (en) * | 1982-05-14 | 1983-11-17 | Hitachi Ltd | Semiconductor device |
-
1983
- 1983-04-14 JP JP58065824A patent/JPS59191371A/en active Granted
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51147187A (en) * | 1975-06-12 | 1976-12-17 | Fujitsu Ltd | Semiconductor device |
| JPS5491067A (en) * | 1977-12-28 | 1979-07-19 | Nec Corp | Input protective circuit |
| JPS574151A (en) * | 1980-06-11 | 1982-01-09 | Hitachi Ltd | Mos integrated circuit device |
| JPS58162054A (en) * | 1982-03-19 | 1983-09-26 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| JPS58197870A (en) * | 1982-05-14 | 1983-11-17 | Hitachi Ltd | Semiconductor device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02150072A (en) * | 1988-11-30 | 1990-06-08 | Fuji Electric Co Ltd | Semiconductor device using input protecting circuit |
| EP0637843A1 (en) * | 1993-08-06 | 1995-02-08 | STMicroelectronics S.A. | Integrated circuit protection against electrostatic discharges |
| FR2708788A1 (en) * | 1993-08-06 | 1995-02-10 | Sgs Thomson Microelectronics | Protection of an integrated circuit against electrostatic overloads. |
| US5515225A (en) * | 1993-08-06 | 1996-05-07 | Sgs-Thomson Microelectronics S.A. | Integrated circuit protected against electrostatic overvoltages |
| US5936288A (en) * | 1997-07-08 | 1999-08-10 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device and low breakdown voltage zener diode |
| JP2020080500A (en) * | 2018-11-14 | 2020-05-28 | ローム株式会社 | Driver circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0313754B2 (en) | 1991-02-25 |
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