JPH04343262A - Integrated circuit - Google Patents

Abstract

PURPOSE:To provide an integrated circuit provided with an electrostatic protective circuit where an input current is prevented from increasing in intensity even if the potential of input signals is larger than that of a power supply. CONSTITUTION:An input protective section is composed of NMOSs 301 and 302 provided with a thick gate film, an input section is composed of a PMOS 303 and an NMOS 306 both provided with a thick gate film, and an inner circuit containing a PMOS 305 and an NMOS 306 is composed of MOSFETs provided with a thin gate film. Even if an input voltage is higher than a power supply voltage, a current is prevented from flowing in through an input terminal. A thick gate film is used in a part to which a high input voltage is applied, and a thin gate film is used in an inner circuit which operates by a power supply of low voltage, whereby an integrated circuit high in dielectric breakdown strength and excellent in high speed operation can be realized.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to integrated circuits, and more particularly to integrated circuits incorporating input protection devices.

0002

[Prior Art] A conventional integrated circuit, as shown in FIG.
A P-channel MOSFE whose source and gate are connected to the first power supply terminal VDD and whose drain is connected to the input terminal I.
An input protection unit consisting of a T (hereinafter abbreviated as PMOS) 501 and an N-channel MOSFET (hereinafter abbreviated as NMOS) 502 whose drain is connected to the input terminal I and whose gate and source are connected to the second power supply terminal VSS, and to VDD. PMOS503 whose source is connected and whose gate is connected to input terminal I
and NMOS504 whose drain is connected to the drain of PMOS503, whose gate is connected to the input terminal and whose source is connected to VSS.
and an internal circuit made up of a plurality of PMOSs and NMOSs, including a PMOS 505 and an NMOS 506 in which the drain of the PMOS 503 is connected to the gate. The input protection section consisting of PMOS 501 and NMOS 502 is provided to protect the input section PMOS 503 and NMOS 504 from breakdown of the gate insulating film due to static electricity. Since breakdown occurs in the drain junction of the NMOS 502 and a large amount of holes are injected into the silicon substrate, the lateral NPN bipolar transistor consisting of the drain, substrate, and source of the NMOS 502 becomes conductive and discharges the charge to VSS. When a high voltage positive with respect to VDD is applied to input terminal I, PMOS50
VD is passed through the N-well from the P-N diode consisting of the drain of 1 and the N-well which is the base of PMOS501.
By discharging to D, breakdown of the gate insulating films of the PMOS 503 and NMOS 504 in the input section is prevented. VSS
Alternatively, when a high voltage negative with respect to VDD is applied to the input terminal I, it is discharged from the N-P diode formed by the drain of the NMOS 502 and the substrate to VSS through the substrate to protect the input section. PMOSFET 503 and NMOSFET 504 in the input section constitute an inverter circuit, which shapes the waveform of the input signal from input terminal I during normal operation and transfers it to the internal circuit as an inverted signal. The transferred inverted signal is inverted again by an inverter circuit consisting of PMOS 505 and NMOS 506 in the internal circuit, and converted into a signal in phase with the input terminal.
A group of logic gates consisting of S is used for logic operations.

0003

[Problem to be Solved by the Invention] In this conventional integrated circuit, when the high level of the signal input to the input terminal I is higher than the power supply voltage of the integrated circuit, current flows from the input terminal side to the integrated circuit. However, there is a problem in that the power consumption becomes extremely large. For example, in FIG. 5, when the signal input to the input terminal I has an amplitude of 0V to 5V, and the power supply terminal VDD of the integrated circuit is 3.3V and VSS is 0V, when the input signal reaches 5V, the input terminal I The drain (P type) of the connected PMOS501 and P
A forward bias of 5-3.3=1.7V is applied to a PN junction diode formed of an N-well (N-type) that is the base of the MOS 501, and a current flows from the input terminal I toward VDD. This poses a major problem when connecting inputs and outputs of integrated circuits having different power supply voltages in the process of decreasing power supply voltages due to miniaturization of design rules.

0004

[Means for Solving the Problems] The integrated circuit of the present invention has a drain connected to a first power terminal, a second power terminal, an input terminal, and the first power terminal, and a gate connected to the second power terminal. a first NMOS connected and having a source connected to an input terminal;
and an input protection unit consisting of a second NMOS whose drain is connected to the input terminal and whose gate and source are connected to the second power supply terminal, and whose source is connected to the first power supply terminal and whose gate is connected to the input terminal. the first PMOS and the first PMO
A third circuit whose drain is connected to the drain of S, whose gate is connected to the input terminal, and whose source is connected to the second power supply terminal.
The input section includes an input section consisting of an NMOS, and a signal line connected to the drain of the first PMOS as input, and an internal circuit consisting of a plurality of PMOS and NMOS.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention, in which a drain is connected to a first power supply terminal VDD, a gate is connected to a second power supply terminal VSS, and a source is connected to an input terminal I. an input protection unit consisting of a first NMOS 101 whose drain is connected to the input terminal I, a second NMOS 102 whose gate and source are connected to VSS, whose source is connected to VDD, and whose gate is connected to the input terminal A first PMOS 103 connected to I, and a third NMOS 1 whose drain is connected to the drain of PMOS 103, whose gate is connected to the input terminal I, and whose source is connected to VSS.
If it is from 04, it includes an input section, PMOS105 and NMOS106 whose gate is supplied with a signal line connected to the drain of PMOS103, and multiple NMOS and PMOS
It consists of an internal circuit consisting of. When an excessive voltage is applied due to static electricity, etc., the drain junction of NMOS 102 breaks down and holes are injected into the substrate due to a positive voltage with respect to VSS, and the drain, substrate, and source of NMOS 102 are connected to the emitter, base, and collector. Discharging the charge through the NPN transistor is the same as in the conventional example shown in FIG. - Discharge the charge to VDD by turning on the NPN transistor on the substrate and drain. In this case, the potential of VSS is floating, but the charge discharging ability of NMOS101 is different from that of NMOS102 (gate is VSS) when a positive voltage is applied to VSS.
Since it is connected to SS, it was found that the charge discharging ability is equivalent to that of 0V), leading to the present invention. VSS or VDD
When a negative high voltage is applied to NMO
The input PMO is discharged to VSS through the source junction of S101 and the drain junction of NMOS102.
This prevents destruction of the gate insulating films of S103 and NMOS104. The functions of the PMOS 103 and NMOS 104 in the input section and the PMOS 105 and NMOS 106 in the internal circuit are similar to those of the PMOS 503 and NMOS in the conventional example shown in FIG.
504 and internal circuit PMOS505 and NMOS506
The function is the same as that of In this embodiment, the input terminal I
If the input signal voltage is greater than the potential difference between VDD and VSS, for example, the input signal is 5V and VDD is 3.3V.
, even when VSS is 0V, both NMOS101 and NMOS102 are non-conductive because their gates are at 0V, and the junction connected to the input terminal is NMOS
Both the source junction of S101 and the drain junction of NMOS102 have the structure of an N-type diffusion layer on a P-type substrate, and because they are in a reverse bias state with 5V applied to the N-type region, there is an advantage that no current flows from the input terminal. .

FIG. 2(a) is a plan view of the circuit of the embodiment shown in FIG. 1 formed into an integrated circuit using two layers of metal wiring on a P-type substrate, and FIG. 2(b) is a plan view of the circuit of the embodiment shown in FIG. A in 2(a)
It is a joint view along A'. 2A and 2B, 200 is a P-type silicon substrate, 201 is an N-well, 202 is an N-type diffusion layer, 203 is a P-type diffusion layer, 204 is polysilicon, 205 is a first metal, 206 is the second metal, 207 is the contact hole between the N-type or P-type diffusion layer and the first metal, 208 is the contact hole between the polysilicon and the first metal, and 209 is the through hole between the first metal and the second metal. , 210 indicates an insulating film. The P-type diffusion layer 203a for charge collection, which has the same high impurity concentration as the source/drain region of the PMOS, is used as the input protection part of the NMOS.
By connecting to the VSS terminal using a metal layer provided near the source of NMOS 101 and near the drain of NMOS 102, the series resistance due to the low impurity concentration on the P-type substrate side of the source junction of NMOS 101 and the drain junction diode of NMOS 102 is minimized. , when a high voltage negative with respect to VDD or VSS is applied to input terminal I, N
Charges injected into the P-type substrate through the source junction of MOS 101 and the drain junction of NMOS 102 are quickly converted to V.
Since it can be discharged to SS, the protection ability is improved.

FIG. 3 is a circuit diagram of a second embodiment of the present invention. NMOS301, NMOS302, PMOS in Figure 3
303, NMOS304, PMOS305, NMOS3
06 are NMOS101 and NMOS102 in Fig. 1, respectively.
, PMOS103, NMOS104, PMOS105,
However, in the second embodiment, the gate insulation film thickness of NMOS 301 and NMOS 302 in the input protection section and PMOS 303 and NMOS 304 in the input section is the same as that of the PMOS and NMOS forming the internal circuit including PMOS 305 and NMOS 306. The difference is that it is thicker than the film. Generally, the conductance of a MOSFET increases in proportion to the reciprocal of the gate insulating film thickness, so the thinner the gate insulating film of the internal circuit is, the better it can operate at high speed. It is known that in order to maintain insulating properties, it is necessary to suppress the electric field in the gate insulating film to 3 to 4 MV/cm or less, and a thicker gate insulating film is desirable in terms of maintaining insulating properties.

Therefore, when the high level of the input signal supplied to the input terminal I is higher than the power supply voltage supplied to the integrated circuit, as shown in the second embodiment of FIG. NMOS302, PMOS3
03. Thickening the gate insulating film of NMOS 304 and thinning the gate insulating films of multiple PMOS and NMOS including PMOS 305 and NMOS 306 that make up the internal circuit can realize an integrated circuit that can operate at high speed and has good long-term reliability. is appropriate. For example, VDD=3.3V, VSS=
When the high level of the input terminal is 5V at 0V, NMO
S301, NMOS302, PMOS303, NMOS
The gate insulating film thickness of 304 is about 15 nm, and PMOS
Appropriately, the gate insulating film thickness of the PMOS and NMOS of the internal circuit including the NMOS 305 and NMOS 306 is about 10 nm.

FIGS. 4(a) and 4(b) respectively show cross-sectional views of NMOSs with different gate insulating film thicknesses.
is a P-type silicon substrate, 402a and 402b are gate insulating films, 403 is a polysilicon gate electrode, 404 is an N-type diffusion region, and 405 is an insulating film. In order to separate the NMOS with a thick gate insulating film in FIG. 4(a) and the NMOS with a thin gate insulating film in FIG. 4(b) on the same substrate 401, first heat the gate insulating film 402a over the entire surface of the substrate 401. After forming the film to a predetermined thickness by oxidation, etc., cover the planned region of NMOS (a) with a thick gate insulating film with photoresist,
The insulating film (silicon oxide film) in the intended area of the NMOS (b) with a thin gate insulating film is removed using hydrofluoric acid or the like. Next, after removing the photoresist, a gate insulating film is formed over the entire surface of the substrate by thermal oxidation or the like to a thickness matching the thin NMOS (b) of the gate insulating film. Thereafter, NMOSs having different gate insulating film thicknesses can be formed by going through normal manufacturing steps. It is clear that PMOSs having different gate insulating film thicknesses can be created by applying the same method to the PMOS gate insulating film at the same time as forming the NMOS gate insulating film.

[0011] In both the circuit configuration of the first embodiment shown in FIG. 1 and the circuit configuration of the second embodiment shown in FIG.
By inserting a resistor between the input terminal I and the connection point of the input protection NMOS 101, 102 or NMOS 301, 302, the peak voltage of the pulsed voltage due to static electricity can be effectively reduced, so the protection ability can be strengthened. Therefore, it is effective to provide an N-type diffusion layer resistance with a value within a range that does not impair high speed performance.

0012

[Effects of the Invention] As explained above, in the present invention, since the input protection section is composed of an NMOS whose gate is connected to VSS, when the high level of the input signal at the input terminal is higher than the power supply voltage of the integrated circuit, This also has the effect that no current flows from the input terminal to the integrated circuit side. Further, by making the gate insulating film thickness of the MOSFET in the input protection section and the input section thicker than that of the MOSFET in the internal circuit, an integrated circuit with good long-term reliability and excellent high speed can be provided.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

[Figure 2] An integrated circuit that realizes the circuit in Figure 1, (a)
(b) is a cross-sectional view taken along line AA' in (a).

FIG. 3 is a circuit diagram of another embodiment of the invention.

FIG. 4 is a cross-sectional view of an NMOS, in which (a) shows one with a thick gate insulating film and (b) shows one with a thin gate insulating film.

FIG. 5 is a circuit diagram of a conventional integrated circuit.

Claims (2)

[Claims] 1. A first power supply terminal, a second power supply terminal, an input terminal, a drain connected to the first power supply terminal, a gate connected to the second power supply terminal, and a source connected to the input terminal. a first N-channel MOSFET connected;
a second N-channel MO whose drain is connected to the input terminal, and whose gate and source are connected to the second power supply terminal;
A source is connected to the SFET and the first power supply terminal,
a first P channel M whose gate is connected to the input terminal;
a third N-channel MOSFET whose drain is connected to the drain of the first P-channel MOSFET, whose gate is connected to the input terminal, and whose source is connected to the second power supply terminal; Multiple P-channel MOSFETs and N-channel MOS whose input is the signal line connected to the drain of the P-channel MOSFET.
An integrated circuit characterized by comprising an internal circuit consisting of a FET. 2. The integrated circuit according to claim 1, wherein gate insulating film thicknesses of the first, second, and third N-channel MOSFETs and the first P-channel MOSFET are the same as those of the N-channel MOSFETs and the first P-channel MOSFETs constituting the internal circuit. An integrated circuit characterized by being thicker than a gate insulating film of a P-channel MOSFET.