JPS5814573A - Semiconductor device - Google Patents

Abstract

PURPOSE:To realize a device with its internal circuits protected against a positive or negative abnormal input by a method wherein a well region on a substrate is provided with a transistor and, simultaneously, a region is specified in the well region, and an electrode connected to this specified region is also connected to the transistor gate electrode. CONSTITUTION:A thick field oxide film 38 is formed in the periphery of an n<-> type semiconductor substrate 31 and the part surrounded by the oxide film 38 is provided with a p<-> type well region 32 formed by diffusion. In the region 32, an n channel transistor 33 is built. That is, an n<+> type drain region 34 and source region 35 are formed by diffusion within the region 32. On the part of the region 32 remaining exposed between the regions 34 and 35, a gate electrode 37 made of polycrystalline Si is formed through the intermediary of a gate oxide film 36. Next, a p<+> type region 43 is formed by diffusion in the region 32, adjacent to the region 34 and insulated by an insulating layer. An electrode 42 attached to the region 43 is then connected to a gate electrode 37. When a positive voltage is supplied to the region 34 with the region 35 grounded, the voltage of the region 32, influenced by the source voltage, becomes nearly equal to the ground voltage, creating stability in the presence of an abnormal input.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor devices, particularly for CMO! 1(C(o
pl-mtary mtal 0xld electric 8wales
adm*ter) The present invention relates to a semiconductor device suitable for input storage of an integrated circuit.

In the past, many proposals have been made as input protection circuits for semiconductor integrated circuits, but most of them have focused on preventing electrostatic damage to the input (r-).

However, in such an input protection circuit, destruction may occur during malfunction (due to abnormal external input) before electrostatic discharge damage occurs during normal operation. This will be specifically explained using FIG. 1 and FIG. #I2. In the first IlI, 1 is an input terminal, and this input terminal 1 is connected to a P-channel MoB type field effect transistor (hereinafter referred to as a P-channel transistor) 1 and an N
Channel M08 m field effect transistor (hereinafter referred to as N
The input terminal of a cMog inverter consisting of 4 channel transistors is connected. In addition, input terminal 1
It is grounded via a ballast resistor 2 and an N-channel transistor 5 for input protection. This N-channel transistor 5? -) is connected to its source.

- is an output terminal of the CMOS inverter.

FIG. 2 is a sectional view showing the specific structure of the above circuit.

In the figure, reference numeral 11 denotes an O-type semiconductor substrate, in which a p-type well region 11 is formed, and in this well region 12 the above-mentioned N-channel transistor 5 for manual film maintenance is formed. IS is a nm region which becomes the drain of this transistor 5, 14 is a type 1 region which also becomes a source, 16 is an f-) oxide film of this transistor 5, 1
# is an r-) electrode made of polycrystalline silicon, 1r is a pH region for connecting the well region 12 and the power supply v0, 18 is the P channel transistor (pW region serving as the source), 20
is a transistor 8 (DI'-) oxide film, 21 is an r-) electrode made of polycrystalline silicon, 22 is a field oxide film, 2
3 is an insulating film, and 24 is a metal At layer which becomes an electrode and wiring. Note that in FIG. 2, the N-channel transistor 4 of FIG. 1 is not shown.

In such a conventional input protection circuit, for example, when a negative voltage is applied to the input terminal 1, as is clear from FIG. Since the pm junction with the region 12 is in the forward direction, a large current flows from the n-type semiconductor substrate 11 to the input terminal 1. Therefore, the protective resistor 1 often melts down.

When + is 9 or 9, electrons are injected from the drain Omm region 13 into the p- type well region 1j, flow through the n- type semiconductor substrate 11, and when the voltage ζ is applied to the substrate 11, the well region 12 Nearby power source■1. Holes flow out from the p-type region #19 connected to the well region 12 and cause latch-up.

As described above, conventional input protection circuits work as a protection circuit against high positive voltages, but they tend to malfunction or break down when faced with negative voltages, making them insufficient as input protection circuits.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device that can protect its internal circuitry against abnormal positive and negative inputs.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

In FIG. 3, 31 is a working type semiconductor substrate, and a p''''' deaf well region 12 is provided in this semiconductor substrate S1.
In this well region sj, an N-channel transistor Ll
is formed.

14 companiesThe m+ type region 15 which becomes the drain of this transistor Ll is also the nlI region which becomes the source, and JI is ff.
-) Is the oxide film, SR, made of polycrystalline silicon? -) electrode,
I8 is a field oxide film, 39- is an insulating film, 40-42
are electrodes made of U, for example, and electrode 42 is ? -) connected to electrode 11; 43 is a p-type well region s2
There is a p+ type region for connecting the p-) electrode S1 via the electrode 42. FIG. 4 is an equivalent circuit diagram of the N-channel transistor 370 of FIG.

In the N-channel transistor L with such a configuration, a positive voltage is applied to the drain (11 type region 34),
Ground the source (Sen type domain machine SS). At this time,? - type well region 12 is pulled to the source voltage and is fixed to the ground voltage. In addition, there is a reverse /4 diameter between the drain and the well region 31, and when the drain voltage is low,
No current flows between the drain and the source. When the drain voltage becomes high, the pm junction between the drain's n-type slope 34 and the p-type well region 32 causes a Zenerbe drop ζ and current flows. The drain and source of the ζON channel transistor 3 are equivalent, and the voltage VDI-current is as shown in FIG. ■ Show characteristics.

Figure 6 shows the above element as 8011 (gli*m -On
-Ssphlre) structure when manufactured using the structure. In the figure, 61 is a sapphire substrate, 62
is a single-crystal silicon layer formed on this Naphire substrate 61 by a vapor phase growth method, and 63 and 64 are n+ type transistors formed on this single-crystal silicon layer 62, which serve as the source or drain of the N-channel transistor 1. Region 6- is a p-type region that also forms a channel, and region 61 is ? -) Is the oxide film 68 made of polycrystalline silicon? -) electrode, 6jl is an insulating film, rO,'ll is a U electrode. Note that the dart electrode 61 is connected to the p-type region #σ6.

Figure 7 shows the N-channel transistor 1 shown in Figure 6.
FIG. In the same figure, f2 hiro r-) electrode 68
13 is a contact hole for connecting the Aj electrode 10 and the n+ lid region 64, 14 is the contact hole for connecting the muL electrode 11 and the t-type region 6J.
This is a contact hole for connection.

Like the transistor LL, this N-channel transistor 1 with the BO8 structure also has the equivalent circuit shown in FIG. 4 and the voltage-current characteristics shown in FIG. 5.

Figure 8 shows the N-channel transistor 1 shown in Figure 3.
FIG. 2 is a circuit diagram when the CMOB is applied to an input protection circuit of a transistor. In the same figure, an input terminal 81 is connected to a p-channel transistor 83 and an N
It is connected to the input terminal of a transistor consisting of a channel transistor 84. Further, the drain of the N-channel transistor Ll is connected to the input terminal JJK via the protective resistor 82, and the source of the transistor 3J is grounded. FIG. 9 shows a partial core structure of the protection transistor in the configuration shown in FIG.

In this input protection circuit, when a high positive voltage is applied to the input terminal 81, holes are injected into the one-type drain well region 32. This hole diffuses within the well region 32 and flows out from the source Ot type region 35 to the ground.

Further, a negative high voltage is applied to the input terminal 81 and holes are injected into the well region 32.

The holes in the hole diffuse within the well region 32 and form the hole in the drain/hole.
It flows out from the mold region 34 to the input terminal 81 .

The above also applies to the N-channel transistor 1 shown in FIG.

If the device of the present invention is used in an input protection circuit, as in
Since no current flows unless an abnormal input voltage is applied to the input terminal 81, the protective resistor a1 will not be fused. The main turn area of the circuit shown in FIG. 8 is almost the same as that of the conventional circuit shown in FIG.

□ In the above embodiment, the case where the present invention is applied to an input protection circuit has been described, but the present invention is not limited to this, and various applications can be made using the characteristics shown in FIG. Further, in the above embodiments, the present invention has been described as an N-channel transistor, but it goes without saying that a P-channel transistor may also be used.

[Brief explanation of drawings]

FIG. 1 is a conventional input protection circuit, FIG. 2 is a sectional view showing the element structure of the above circuit, FIG. 3 is a sectional view of a semiconductor device according to an embodiment of the present invention, and FIG. 4 is an equivalent of the above device. circuit, 5th
6 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention, FIG. 7 is a plan view 1 of the device shown in FIG. 6, and FIG. An input protection circuit using the device shown in FIG. 3, and FIG. 9 is a sectional view showing the element structure of the main part of the circuit shown in FIG. J1--n-type semiconductor substrate, SZ--p-type well region, Jj-N-channel MO8g field effect transistor, 14...-type region (drain), 35...-
Mold region (source), gl-/sapphire substrate, 62...
- Single crystal silicon layer, 61. Jj4-11 type so area, Ll
・-N-channel MO8ill field effect transistor,
81--input terminal, 82-protection resistor. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Ii 2 Figure 3 Figure 4 Whistle 6 Figure 7

Claims (4)

[Claims] (1) a semiconductor substrate of a first conductivity type, a well region of a second conductivity type formed in the semiconductor substrate so as to be insulated from a power supply, and r-) formed in the well region; 1. A semiconductor device comprising: an MO811 field effect transistor manufactured by First Conductive Co., Ltd., connected to the semiconductor device. (2) The semiconductor according to claim 1, wherein the drain of the MOa field effect transistor is connected to an external input terminal via a protective resistor, and the source is grounded to form an input protection circuit. Device. (3) an insulating substrate, a second conductivity type semiconductor layer provided on the insulating substrate, and an 'i”-
) comprises a second conductive plate MO[l field effect transistor] connected to the semiconductor layer. (4) The semiconductor device according to claim 3, wherein the drain of the MO8 field effect transistor is connected to an external input terminal via a protective resistor.