JPS6112693Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to preventing destruction of MOS-ICs (insulated gate field effect device integrated circuits) due to external electric fields. The main purpose is to prevent dielectric breakdown of the gate film due to the high voltage that is applied to the IC, and also to reduce manufacturing backlog by incorporating the above protection measures into the IC, as well as to prevent destruction of the protection element itself. shall be.

[Prior art]

An example of a commonly used MOS element has the configuration shown in FIG. Figure 1 shows an example of a P-channel MOS device, in which a source 12 made by high-concentration P-type diffusion is formed on an N-type low-concentration substrate 10, and a metal such as Al is connected to the drain 11 and a thin insulating layer 15 such as _Sio2 . It is composed of the gate electrode 17 thus formed. 18 is a drain electrode connected to the drain 11 through a hole in the oxide film, and 19 is a source electrode, which in the above example is connected to the substrate 1 by the N type high concentration diffusion layer 13.
0 is possible. 16
is a thick insulating layer formed for the purpose of reducing wiring capacitance. In the above device, the current between the drain 11 and the source 12 can be controlled depending on the potential of the gate electrode 17 with respect to the substrate 10.

In addition, CMOS circuits (complementary MOS circuits) that combine P-channel MOS elements and channel MOS elements are being realized in integrated circuits for many purposes as they enable logic circuits that consume power in microamperes. The basic structure is as shown in FIG. 2, for example, a P type low concentration layer 31 is formed in an N type low concentration substrate 30, 32 and 33 are the source and drain of each N channel MOS element, and 3
Reference numerals 6 and 37 are the drain and source of the P-channel MOS device, and the drains 33 and 36 of each are connected by an electrode 44 to serve as the output terminal of the CMOS device, and the gates 42 and 43 of each are also driven by a common potential. This is the input end. The P layer 34 and the N layer 38 are high concentration diffusion layers called guard rings or stoppers for the purpose of preventing coupling between elements and applying potential to each substrate. 45 and 46 are source and substrate electrodes, respectively, where pole 45 is negative and pole 4 is negative.
6 is given a positive potential. 40 is a gate film;
41 is an insulating film. As is clear from the above, C-
The breakdown voltage of the MOS element is the dielectric breakdown voltage of the gate film 40, P
Two types of substrates: layer 31, N layer 30 and drain 33 and P layer 31, drain 36 and N layer 30
It can be considered as the combined breakdown voltage of all the breakdown voltages of each reverse junction.

Of the above breakdown voltages, dielectric breakdown of a reverse bias junction occurs at a constant voltage for breakdown caused by an external electric field with relatively low energy density, such as static electricity.
To a certain extent, it does not cause permanent breakdown and returns to normal when the applied potential is removed. This is called primary breakdown of the junction, but dielectric breakdown of the gate insulating film often occurs when the gate electrode and the gate lower substrate, etc. This will cause a short circuit, resulting in permanent damage to the device. For this reason, a protection mechanism called a gate clamp diode is added for the purpose of absorbing the charge applied to the gate portion and suppressing the potential applied to the gate below the gate dielectric breakdown voltage.

FIG. 3, FIG. 4, and FIG. 5 are schematic diagrams each showing the function of a gate clamp diode in a CMOS device. In FIG. 3, 78 shows a configuration example of a clamp diode, 63 is a common gate of the CMOS element, 80 is a gate stray capacitance, and the common drain 64 of the P-channel and N-channel MOS elements 61 and 62 becomes an output end. 70 is a diode indicating a junction between two substrates, and 65 is a capacitance between both substrates. As shown in FIG. 3, when the power supply 71 is turned off by the switch 72, the potential of one or both of the power supplies 73 and 74 is changed to the positive terminal 75, the negative terminal 77, and the gate terminal 7.
6, the diodes 66, 67,
69 is a forward junction with respect to the power supplies 73 and 74, so the potential depending on the power supply is the same as that of the diodes 66 and 6.
7 and 69, and almost no potential is applied to the gate 63. Low resistance 68 has gate capacity 80
In addition, the diode 63 is given a time constant to absorb the potential applied to the gate 63.
6 and 69 using the resistance of the diffusion layer.

FIG. 4 shows the power supply 111 from the case in FIG.
is connected to the circuit by the switch 112, and the terminals 115 and 1 are connected by the power supplies 113 and 114.
This is a case where the potentials applied to terminals 16 and 117 are reversed from those in FIG. When the power source 114 has a higher potential than the power source 111, the diode 109 becomes a forward junction, and when the power source 113 has a higher potential than the power source 111, the diode 107 becomes a forward junction to transfer the charges of the power sources 114 and 113 to the power source. 111, and as a result, the power supply 11 to the gate 103 is almost
A potential of 1 or more is not applied. Power supply 111 is CMOS
If the system power supply takes into account the withstand voltage of the element, and the power supplies 113 and 114 are power supplies with small capacity such as those based on static electricity, the element will be sufficiently protected from the above results.

FIG. 5 shows a case where the power supply 141 of the system is disconnected by a switch 142 from the case shown in FIG.
At this time, depending on the power supplies 143 and 144, the terminal 14
The potential applied to 5, 146, 147 is diode 1
The potential of the gate 133 is raised until it reaches the reverse breakdown voltage between the substrates indicated by 40 or the reverse breakdown voltage of one or both of the diodes 136 and 137 in series.

Generally, when configuring CMOS, the gate breakdown voltage is 50 to 100V, and the drain or substrate breakdown voltage (reverse breakdown voltage of the junction) is often about several volts to 40V. It can be said that the gate can be protected because it is discharged due to the primary breakdown of the junction before it reaches the gate breakdown voltage, but in reality, the first problem is that the terminal 14
5, 146, and 147, the absorption in the time constant circuit of the resistor 138 and capacitor 150 is insufficient, and the primary breakdown of the reverse junction of the diode 140 between the substrates depends on the substrate capacitor 135. Since the timing is delayed, the gate terminal may exceed the gate breakdown voltage during this time, causing dielectric breakdown of the gate 133.

As a second problem, if the charge applied to the gate terminal 146 is considerably large, the reverse junction near the terminal, that is, the diode 139 or the diode 14
0 passes the primary destruction and often causes secondary destruction, which is permanent destruction.

〔the purpose〕

The present invention aims to improve the above two points at the same time. First, in order to prevent gate breakdown caused by an impulse-like external potential when the gate withstand voltage and reverse junction withstand voltage are relatively close to each other, the reverse junction withstand voltage must be sufficiently compared to the gate withstand voltage within a range that does not cause any problems with the operating voltage. It is to make it lower. Then, for example, terminal 146
The method is to insert a time delay circuit, for example, a resistor 138 and a capacitor 150, within a range that does not hinder operation until the potential applied from the gate 133 is actually applied to the gate 133. Actually, the protection diode 13 in FIG.
9 and a diode 140 representing the board-to-board breakdown voltage.
It has been found through experiments that by controlling the breakdown voltage of the gate to approximately one-fifth or less of the gate breakdown voltage, a sufficient effect can be obtained against the electrostatic field applied during the normal IC assembly process.

As mentioned above, the breakdown voltage of the reverse junction of the MOS device is the second
In the figure, (1) drain N layer 33 and P substrate 31
(2) between the drain 36 of the P layer and the N substrate 30;
(3) This is represented by the breakdown voltage between the P substrate 31 and the N substrate 30. Primary breakdown of a reverse junction occurs when the potential gradient across the width of the depletion layer caused by a reverse electric field applied to the junction exceeds the dielectric breakdown strength (expressed as the electric field strength per unit length) determined by the semiconductor's counterpart material. Due to the difference in quantity, for the same potential difference, the depletion layer in the low concentration diffusion layer expands more than the depletion layer in the high concentration diffusion layer.

Conventionally, in order to partially lower the breakdown voltage of the junction, for example, the drain 33 of the N layer in FIG.
, the stopper 34 of the P layer, and the drain 3 of the P layer
In this method, the distance between the stopper 38 of the N layer and the stopper 38 of the N layer is intentionally made closer to limit the expansion of the depletion layer, thereby lowering the withstand voltage. However, with this method, the spacing is not fixed due to errors in mutual positioning between the P-layer mask and the N-layer mask, and errors in the patterns of the P and N layers, and therefore the withstand voltage that can be obtained also decreases. The results will vary, and a sufficient effect cannot be expected.

The present invention solves this problem by controlling the concentration of the substrate around the target drain, etc., to obtain an accurate and stable reverse breakdown voltage of the junction.

〔Example〕

FIGS. 6 and 7 show the expansion of the depletion layer in the reverse junction constructed according to the principle of the present invention.
The concentration of the entire substrate is determined based on various characteristics such as the overall breakdown voltage and the threshold of the element, but the substrate concentration around junctions such as drains that require a reduction in reverse breakdown voltage is reduced by ion implantation and impurity oxide films. It is increased by methods such as diffusion to lower the reverse breakdown voltage of the junction. Figure 6 shows the case where the increase in substrate concentration around the drain is relatively small, and Figure 7 shows the case where the increase in substrate concentration is relatively large. 201 and 211 are the range of concentration increase due to ion implantation, etc. ,210
are P-type drain diffusion layers, 205 and 21, respectively.
5 is an N type substrate, curves 203 and 213 show concentration curves for each case, and the upper one is the P type;
The lower part shows N type diffusion. Further, 202 and 212 schematically show the width of the depletion layer generated in the above-mentioned reverse junction, but as mentioned above, the depletion layer is difficult to spread during high concentration diffusion, so the increase is larger than the depletion layer 202 when the substrate concentration increase is small. In this case, the depletion layer 212 has a smaller spread and the reverse breakdown voltage of the junction is also smaller.

Based on the above principle, it is possible to arbitrarily and accurately determine the reverse breakdown voltage of a junction such as a drain.

FIG. 8 shows an embodiment in which the present invention is applied to a CMOS integrated circuit, in which an N substrate 230 and a P substrate 231
236, 237, and 243 are the drain, source, and gate electrodes of the P channel transistor, and 233, 232, and 242 are the drain, source, and gate electrodes of the N channel transistor. The N type diffusion layer 249 constitutes a diode between it and the P substrate 231, and corresponds to the diode 67 in FIG. 3 as a gate protection diode. A low concentration P type diffusion layer 251 is formed around the diffusion layer 249 by ion implantation, etc., and the gate protection diode 2
The withstand voltage of 49-231 is controlled. The P type diffusion layer 250 is a guard ring, and the diffusion layer 249
Sufficient spacing is provided so as not to affect the withstand pressure of the Electrodes 248 are connected on one side to the gate electrode of the transistor and on the other side to the input terminal. Similarly, diodes configured on N substrates such as diodes 69 and 66 in FIG. 234,
During the period 238, the low concentration diffusion layer 252 is diffused by ion implantation or the like.

Regarding the second problem, the secondary breakdown of the junction of the protection diode, the secondary breakdown of the junction is due to the primary breakdown of the junction of charges caused by the electrostatic field, and because it occurs locally concentrated, the high current density It is known that this is due to the current being concentrated in a portion of the junction, and this can therefore be prevented by lowering the current density, that is, by causing the primary breakdown of the junction to occur over a relatively wide area. Generally, it is virtually impossible to uniformly cause primary failure in all parts of the bond, but when the concentration gradient is made steeper by increasing the substrate concentration as in the present invention, Electric field concentration due to abnormal diffusion, etc. is reduced, and in addition, the reverse withstand voltage of the junction is lowered, and the impedance up to the junction is lowered, causing primary breakdown of the junction over a wide range due to the rapidly rising potential. ,
[Effect] As mentioned above, in the present invention, a high-concentration diffusion layer for a guard ring is formed at the junction between the second conductivity type diffusion region and the first conductivity type semiconductor substrate. layer and a low concentration diffusion layer on the surface of the semiconductor substrate in the vicinity of the high concentration diffusion layer for the guard ring, it is difficult to connect the input terminal by just reverse bonding due to wiring patterns of various shapes and voltage waveforms caused by static electricity. Even if there is not sufficient electrostatic absorption, complete voltage absorption can be achieved.Also, the diffusion distance is set in advance when creating the mask to form the diffusion layer that forms the guard ring and gate protection diode of the present invention. However, since it can be formed in the same process as that for source/drain diffusion layers, etc., it also has the effect that there is no need to increase the number of processes.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view showing the configuration of a MOS element.
FIG. 2 is a schematic cross-sectional view showing the configuration of a CMOS element. FIGS. 3 to 5 are examples of equivalent circuit diagrams showing the function of gate protection diodes. 6 and 7 are schematic diagrams showing the expansion of the depletion layer due to the difference in concentration gradient of diffusion, and 202 and 212 indicate the width of the depletion layer. FIG. 8 is a schematic cross-sectional view of a CMOS device showing an embodiment of the present invention.

Claims (1)

[Scope of utility model registration request] a first conductivity type semiconductor substrate, a second conductivity type well region formed in the first conductivity type semiconductor substrate, and a second conductivity type well region formed in the first conductivity type semiconductor substrate and the second conductivity type well region, respectively. In the semiconductor integrated circuit comprising a transistor, the first
In the vicinity of the junction between the conductive type semiconductor substrate and the second conductive type well region, a first conductive type high concentration diffusion layer for a first guard ring and a second conductive type high concentration diffusion layer for a second guard ring are provided. A concentration diffusion layer is formed,
The second conductivity type well region includes a first conductivity type diffusion layer forming the second conductivity type well region and a gate protection diode, and a first conductivity type diffusion layer located near the first conductivity type diffusion layer. A second conductive type third guard ring high concentration diffusion layer is formed, and the first conductivity type semiconductor substrate surface between the first and second guard ring high concentration diffusion layers is formed with a first conductive type. A shallow low concentration diffusion layer is formed, and a shallow low concentration diffusion layer of a second conductivity type is formed on the surface of the second conductivity type well region around the first conductivity type diffusion layer. A semiconductor integrated circuit characterized by: