JPS62279675A - Protective circuit for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent a semiconductor integrated circuit from causing a parasitic effect such as a latchup by forming a high density impurity layer in the bottom of a device in which a resistance value alters according to an input to reduce a delay time without loss the performance of a protective circuit for the integrated circuit. CONSTITUTION:A low density P-type source, drain regions 407, 408 are formed deeply in contact with a high density N-type region 302. Thus, when the breakdown voltages of the source, drain and the region 302 of an MOSFET are suitably reduced so that a negative large voltage is applied to the source or the drain, a current flows through a junction between the regions 407, 408 and the region 302 to prevent a protective circuit itself from breaking down. Since the thicknesses of the regions 407, 408 are increased, a conductivity between the source and the drain when the MOSFET is conducted is raised.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a protection circuit that prevents damage caused by abnormal voltage during the operation of a semiconductor integrated circuit.6 [Prior Art] This type of device is known, for example, from Japanese Patent Publication No. 45-3464.
As stated in No. 1, a capacitor and a resistor are provided to protect the elements inside the integrated circuit, and when an excessive voltage is applied to the input signal line, this protection circuit prevents the inside of the integrated circuit from being damaged. , to prevent excessive voltage or current from being applied.

As described in this publication, in order for this circuit to function satisfactorily as a protection circuit, it is necessary that the capacitance and resistance of the protection circuit have a certain time constant. That is, when a protection circuit is provided, the signal itself input to the integrated circuit will also be subject to a certain delay due to the protection circuit.

For this reason, in high-speed integrated circuits, the time constant of the protection circuit must be made small to reduce the delay time.
As a protection circuit, it could not fully achieve its purpose.

In order to solve such problems, Japanese Patent Application Laid-Open No. 51-815
As described in No. 79, a protection circuit using a device whose resistance value changes depending on the input potential has been proposed.

In this circuit, when the input potential exceeds a certain positive value, the potential at the output terminal of the protection circuit will increase.

It has a characteristic that the potential is fixed at a value determined by the threshold voltage of this protection circuit, and a potential higher than that is not transmitted to the output terminal. That is, when a positive overpotential is supplied to the input terminal of the protection circuit.

Acts as a good protection circuit. On the other hand, when a negative overpotential is applied to the input terminal, a current flows to the substrate due to the PN junction diode formed by the grounded substrate and the source region, and this overpotential is prevented from being transmitted to the output terminal of the protection circuit. However, there is a problem in that the resistance of the substrate is large, making it impossible to fully achieve its purpose.

Furthermore, when current flows through this diode, minority carriers are injected into the substrate, which causes a latch-up phenomenon in the integrated circuit.

[Problem that the invention seeks to solve]

As mentioned above, conventional protection circuits have the problem of not being able to transmit input signals to the internal circuits without damaging the internal circuits of integrated circuits or causing parasitic effects such as latch-up, and without delaying input signals. was there.

An object of the present invention is to provide a protection circuit that suppresses an increase in signal delay time due to the provision of a protection circuit and does not cause parasitic effects such as latch-up.

[Means for solving problems]

Recently, it has become possible to form a CMOS device and a bipolar transistor in the same chip, and a protection circuit can also be constructed from a composite circuit of these devices. Under these circumstances, we investigated ways to reduce the time constant of the protection circuit. As a result, instead of the conventional protection circuit consisting of capacitors and resistors as mentioned above, the protection circuit can be configured with a device whose resistance value changes depending on the input potential, without impairing the performance of the protection circuit. It has become clear that the delay time can be reduced.

In addition, by providing a highly concentrated impurity layer at the bottom of such devices, the resistance of the substrate is reduced, making it easier for current to flow through the substrate when a large voltage is applied, and preventing minority carriers from being injected into the substrate. However, it has become clear that parasitic effects such as FET latch-up can be eliminated.In other words, the present invention provides a protection circuit for a semiconductor integrated circuit provided between an external terminal of an integrated circuit and an internal circuit of the integrated circuit. , a device whose resistance value changes depending on the potential applied to the external terminal is provided between the input terminal and the output terminal of the protection circuit, and a voltage having a predetermined range is applied to the input terminal. Sometimes, the external terminal and the internal circuit are electrically connected through the device, and when a voltage other than a predetermined voltage is applied, the external terminal and the internal circuit are electrically disconnected, and the bottom of the device is characterized by having a high degree impurity layer connected to the @ source or ground terminal.

In the present invention, the device constituting the resistance of the protection circuit is a field effect transistor (hereinafter referred to as FET) having a high concentration layer at the bottom of the device.

In particular, we have found that high voltage MOS FETs and junction FETs are optimal.

[Effect]

In the present invention, instead of resistors used in conventional protection circuits, devices such as MOSFETs and junction FETs whose resistance value changes depending on the potential applied to the input terminal are used to realize high-speed integrated circuits. Also, the time constant of the protection circuit can be made small, and the delay time can be reduced.

In addition, by providing a highly concentrated impurity layer at the bottom of this device, it reduces the resistance of the substrate, making it easier for current to flow through the substrate when a large voltage is applied, and preventing minority carriers from being injected into the substrate. Parasitic effects such as FET latch-up can be eliminated.

〔Example〕

FIG. 1 is an equivalent circuit diagram of a protection circuit according to an embodiment of the present invention. The operation of the protection circuit of the present invention will be explained using this circuit diagram.

In the figure, 1 is the input terminal, 3 is the output terminal, and 4 is the PMO
3FET board, 5 is MOSFET, 2 is MOSFET
This is the gate terminal of No. 5. A high concentration N-type impurity layer connected to a power supply or ground terminal is provided at the bottom of the MOSFET 5.

The power supply voltage is -5V, and the gate terminal 2 of MOSFET5
By applying a power supply voltage of -5V to the MOSFET 5 and grounding the substrate, the MOSFET 5 is made conductive. An output terminal 3 is connected to an input terminal of the integrated circuit. This MOS
Assuming that the threshold voltage of FET 5 is ■, from this circuit diagram, when a positive potential is applied to input terminal 1, a current flows through diode 4 to the grounded high concentration N-type impurity layer, and terminals 1 and 3 are Prevents potential rise. Furthermore, even when the voltage applied to the input terminal 1 is large and the current cannot flow sufficiently through the diode 4, the terminals 1 and 3 are shielded by the gate electrode which is AC grounded. The coupling capacitance with terminal 3 is extremely small, and the potential of terminal 1 is not transmitted to terminal 3.

On the other hand, when a negative potential is applied to terminal 1, the MOS
Terminals 1 and 3 are in a conductive state until the threshold voltage of FET 5 reaches (-5V-V), and the potential of terminal 1 is transmitted to terminal 3. When the potential of the terminal 1 becomes even more negative, the MOSFET 5 is cut off, and the potential of the terminal 1 is no longer transmitted to the terminal 3. In other words, only when the potential of terminal 1 is between O■ and (-5V-Vl), terminals 1 and 3 are passed through, and this circuit becomes non-conductive for voltages outside this range, so it is protected. Operates as a circuit. Here, it goes without saying that vl is set depending on the amplitude of the signal potential to be transmitted.

FIG. 2 is a diagram showing the relationship between the voltage applied through a resistor to the input terminal 1 of the protection circuit shown in FIG. 1 and the voltage appearing at the output terminal 3. Input potential is from 1200 to 200
Even if the potential of output terminal 3 changes from 1v to -6■
It shows good transfer characteristics.

FIG. 3 is a sectional view of a protection circuit according to a first embodiment of the invention having the circuit shown in FIG.

In the figure, 301 is a P-type silicon substrate, 302 is a high concentration N shadow region embedded in the P type substrate 301, 303 is a low concentration N shadow region formed on the high concentration N shadow region 302,
304 is a silicon oxide film formed on the surface for surface protection and element isolation, 305 and 306 are high concentration P-type source and drain regions, and 307 and 308 are formed to improve the withstand voltage of the source and train. 309 is a gate oxidation region, 310 is a gate electrode, 312 is a high concentration N shadow region connected to the high concentration N shadow region 302, and 311 is an electrode. Although not shown, in order to control the threshold voltage 1, the gate electrode 3
Of course, conventional MOSFET fabrication techniques may be used, such as ion implantation near the channel region under 10.

With the protection circuit of this embodiment configured in this way, even if an excessive voltage is applied to the external terminal of the integrated circuit, it will not be transmitted to the internal circuit of the integrated circuit, thereby preventing damage to the circuit or change in characteristics. can. Also.

Since this protection circuit has a sufficiently low resistance value and a small time constant, the delay time due to this protection circuit is reduced when a normal voltage is applied. Furthermore, by providing a high-concentration N shadow region 302 connected to the power supply or ground terminal at the bottom of the device constituting the protection circuit, it is possible to prevent minority carriers from being injected into the substrate 301, resulting in problems such as launch-up. Parasitic effects can be prevented.

FIG. 4 is a sectional view of a protection circuit according to a second embodiment of the present invention.

In the first embodiment shown in FIG. 3, low concentration source and train regions 307 and 308 are formed near the surface to have the same depth as the high concentration source and drain regions 305 and 306. However, this embodiment is characterized in that it is formed deeply. The other configurations are the same as in the first embodiment. That is, in this embodiment, the low concentration P-type source and train regions 407 and 408 are formed deep and in contact with the hole concentration N-type region 302.
When the breakdown voltage between the source and drain of the ET and the high concentration N shadow region 302 is appropriately reduced and a large negative voltage is applied to the source or drain, the low concentration P type source and drain regions 407 and 408 High density N shadow area 302
Current flows through the junction, which has the effect of preventing destruction of the protection circuit itself. Furthermore, since the thickness of the low concentration P-type source and drain regions 407 and 408 increases, the MOSFET
Source when ET is conducting.

It also has the effect of increasing the conductivity between the drains. For this purpose, it is desirable that the regions 407 and 408 be formed to be sufficiently smaller than the gate electrode 310.

FIG. 5 is a sectional view of a protection circuit according to a third embodiment of the present invention.

In the first and second embodiments shown in FIGS. 3 and 4,
Although MOSFETs were used as devices constituting the protection circuit, this embodiment is characterized by the use of junction type FETs. A high-a degree N-type region 302 on a P-type silicon substrate 301,
silicon oxide film 304 for surface protection and element isolation;
Low density P shadow area 503, high density N shadow area 512 for connection,
P-type source and drain regions 505 and 506 are formed and electrodes 511 are provided.

Compared to the embodiments shown in FIGS. 3 and 4, this embodiment is characterized in that it does not have a gate electrode. This structure can be formed by the process of fabricating a resistor in a bipolar integrated circuit, and the fabrication process of an integrated circuit is not increased to fabricate the protection circuit.

That is, the use of a junction type FET has the advantage that manufacturing is easier than when a MOSFET is used. In this protection circuit, the junction type FE is
Surrounding T, P shadow areas 505 and 506 are in the forward direction with respect to the high density N shadow area 302, and form a low density P shadow area 503.
Another feature is that the structure is such that even if carriers are injected into the substrate 301, they do not flow out to the substrate 301.

FIG. 6 is a sectional view of a protection circuit according to a fourth embodiment of the present invention.

In FIG. 5, the high-concentration P-type source and drain regions 505 and 506 of the junction FET are surrounded by the high-concentration N shadow region 512, but in the fifth embodiment, there is a high-concentration P shadow region 513 between them.
．． 514 is provided, and when a voltage is applied in the forward direction to the high concentration P shadow region 505 and 506 with respect to the N shadow region 302,
It is characterized in that the injected carriers are absorbed by the P shadow regions 513 and 514. For this purpose, P shadow area 51
3.514 is desirably connected to have the same potential as the N shadow region 302.

In FIGS. 5 and 6, as shown in FIG. 4, a low-density P shadow area 407.
8 is omitted, but it goes without saying that the breakdown voltage can be controlled by forming it in the same manner as in FIG. 4. 6 FIG. 7 is an equivalent circuit diagram of another embodiment of the protection circuit according to the present invention. be. Although only a MOSFET is used as a protection circuit in FIG. 1, this protection circuit may be damaged if a larger voltage is applied to the input terminal. In order to prevent this, this embodiment is characterized in that a resistor 6 is connected to the source terminal of the MOSFET. The resistance value of this resistor 6 was preferably about 50 ohms to 200 ohms in order to prevent an increase in delay time and to prevent damage to the protection circuit.

It goes without saying that the effectiveness of the protection circuit can be further improved by connecting two protection circuits according to the present invention in series, or by using them in series with a conventional protection circuit. However, in this case, it is desirable to select the time constant of the conventional protection circuit to be sufficiently small.

Furthermore, in the above embodiments, the protection circuit for the input signal terminal was described, but if the resistor is designed appropriately, it can also be used for the power supply terminal, etc. ．． -1+fi N type MO3FET, N
The same effect can be achieved even when using a bipolar junction type FET, and furthermore, the highly concentrated impurity layer formed at the bottom of the device can be formed using the thermal diffusion method or ion implantation method used in well-known bipolar LSIs. However, if it is formed using a high-energy ion implantation method, it can be formed more easily and at a much lower cost.

〔Effect of the invention〕

As explained above, according to the present invention, even if an excessive voltage is applied to the external terminal of an integrated circuit, it is not transmitted to the internal circuit of the integrated circuit, and damage to the circuit or change in characteristics can be prevented. When a normal voltage is applied, this protection circuit has a sufficiently low resistance value, so the time constant is small, and the delay time due to this protection circuit is effectively reduced. In addition, by having a highly concentrated impurity layer connected to the power supply or ground terminal at the bottom of the device that constitutes the protection circuit, it is possible to prevent minority carriers from being injected into the substrate, thereby preventing parasitic effects such as latch-up. effective.

[Brief explanation of drawings]

Fig. 1 is an equivalent circuit diagram of a protection circuit according to an embodiment of the present invention, Fig. 2 is a diagram showing the relationship between input voltage and output voltage of the protection circuit of Fig. 1, and Figs. 3 to 6 are respectively FIG. 7 is a sectional view of the protection circuit when the first to fourth protection circuits of the present invention are incorporated into an integrated circuit, and FIG. 7 is an equivalent circuit diagram of the protection circuit of another embodiment of the present invention. 1...Input terminal 2...Gate terminal 3...
- Output terminal 4...Diode 5...MOSFET 301...P type silicon substrate 302...High concentration N shadow region 303...Low concentration N shadow region 304...Surface protection silicon oxide film 305. 306, 505, 506... High concentration P type source, drain region 307. 308... Low concentration P type source, drain region 309... Gate oxide film 310... Gate electrode 311, 511... Electrode 312 .512...High density N shadow area 407.408...Low density P shadow area 503...Low density P shadow area

Claims (1)

[Claims] 1. In a protection circuit for a semiconductor integrated circuit provided between an external terminal of the integrated circuit and an internal circuit of the integrated circuit, the device whose resistance value changes depending on the potential applied to the external terminal is the device concerned. is provided between an input terminal and an output terminal of the protection circuit, and when a voltage having a predetermined range is applied to the input terminal, the external terminal and the internal circuit are electrically connected through the device, When a voltage other than a predetermined voltage is applied, the external terminal and the internal circuit are electrically cut off, and the bottom of the device has a highly concentrated impurity layer connected to a power supply or a ground terminal. A protection circuit for semiconductor integrated circuits. 2. The protection circuit for a semiconductor integrated circuit according to claim 1, wherein the device has a gate electrode, and the gate electrode is connected to a power supply or a ground terminal.