JPS622704B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a gate protection circuit for preventing gate breakdown due to surge voltage during operation and handling of a MOS field effect transistor.

Generally, in a MOS field effect transistor, the insulating layer under the gate electrode is formed thinly, so if a steep surge voltage is applied between the gate and the source, this insulating layer will break down and become inoperable. becomes. Conventionally, in order to prevent this dielectric breakdown, a gate protection circuit as shown in Figure 1A was used, and this was incorporated into the same semiconductor substrate together with a MOS field effect transistor as shown in Figures B and C. There is. That is, in these figures A to C, 1 indicates the MOS to be protected.
2 is an input terminal; 3 is a time constant delay resistor connected between the gate of the MOS field effect transistor 1 and the input terminal 2;
4 and 5 are the input terminal 2 and the high potential side 6 of the power supply.
and a clamp diode connected between the low potential side 7 and the low potential side 7 to prevent gate destruction.
are aluminum wiring, 9 is an insulating layer, and 10 is a high concentration N
11 is a high concentration P type impurity diffusion region, 12 is a low concentration P type impurity diffusion region, and 13 is a low concentration N type semiconductor substrate.

Now, if a steep positive or negative surge voltage is applied to the input terminal 2, the time constants of the clamp diodes 4 and 5 are changed by the delay resistors 3 and 5.
By making the time constant of the circuit smaller than that determined by the MOS type field effect transistor 1, the clamp diodes 4 and 5 operate before the MOS type field effect transistor 1, and this surge voltage is transferred to the MOS type field effect transistor. This allows it to be prevented from being applied to the gate of transistor 1.

However, in this conventional configuration, the time constants of the clamp diodes 4 and 5 must be made smaller than the time constants of the MOS field effect transistor 1 and the delay resistor 3. It is necessary to carefully consider the size of the time constant delay resistor 3. In particular, the size of the time constant delay resistor 3 is greatly related to the surge breakdown voltage, and the larger the size, the more effective it is.
There is a natural limit to the size of field-effect transistors because they interfere with the normal operation of field-effect transistors, and also because of high-density integration.

This invention improves these conventional disadvantages by using a junction field effect transistor.Hereinafter, one embodiment of this invention will be explained in detail with reference to FIGS. 2A to 2C. do.

FIG. 2A shows the gate protection circuit of the MOS field effect transistor according to this embodiment, and FIG.
C indicates the structure of each substrate. In these FIGS. 2A to C, the same reference numerals as in FIGS. 1A to C represent the same or corresponding parts, and in this embodiment, the time constant delay resistor 3 is replaced by a junction field effect transistor 14 The source of this junction field effect transistor 14 is connected to the input terminal 2, and the gate is connected to the high potential side 6 of the power source.
In addition, the drains are connected to the gates of the MOS field effect transistors 1, and since the gates are at a high potential due to the structure of the pattern, a capacitor 15 is connected to cut the gates from the source side in a DC manner. In addition, the clamp diodes 4 and 5 are connected in the same manner as described above, and furthermore, these are formed on the same semiconductor substrate 13.

Therefore, in the configuration of this embodiment, when a negative pulse surge voltage is applied to the input terminal 2, the same operation as the conventional circuit described above is performed, but when a positive pulse surge voltage is applied, In the P ^- region directly under the gate of the junction field effect transistor 14,
Due to the resistance component, the positive pulse surge voltage is applied with a delay, and the area between the n ⁺ region and the p ^- region is reverse biased at the moment the surge voltage is applied, creating a depletion layer in this region 6-1. occurs, forcing the p ^- region between the source and drain into a complete cutoff region,
Application of a surge voltage to the gate of the MOS field effect transistor 1 can be prevented. On the other hand, since this p ^- region is in a conductive state during normal times, the input signal passes through a certain resistance component to this MOS.
It is transmitted to the gate of the field effect transistor 1.

Although the above embodiments have been explained using an n ^- , that is, a low concentration N type semiconductor substrate, it goes without saying that exactly the same operation and effect can be obtained when a low concentration P type semiconductor substrate is used. be.

As detailed above, according to this invention,
By using a junction field effect transistor in the gate protection circuit of a MOS field effect transistor, the gate can be protected particularly against positive pulse surge voltages and sufficiently against negative pulse surge voltages. It has the feature of preventing dielectric breakdown.

[Brief explanation of the drawing]

Figures 1A, B, and C are a circuit diagram, a schematic top view, and a sectional view, respectively, of a conventional gate protection circuit for a MOS field effect transistor, and Figures 2A, B, and C are respectively a circuit diagram, a schematic top view, and a sectional view of a conventional gate protection circuit for a MOS field effect transistor. According to one embodiment of the invention
1A and 1B are a circuit diagram, a schematic top view, and a cross-sectional view, respectively, of a gate protection circuit of a MOS field effect transistor. 1...MOS type field effect transistor, 2...
Input terminal, 4, 5...clamp diode, 6,
7... High potential side, low potential side of power supply, 14... Junction field effect transistor, 15... Capacitor.

Claims (1)

[Claims] 1 The source of the junction field effect transistor is the input terminal, the gate is the high potential side of the power supply, and the drain is the input terminal.
are connected to the gates of the MOS field effect transistors, and the source and gate of the junction field effect transistor are connected via a capacitor, and between the input terminal and the high potential side and the low potential side of the power supply. A gate protection circuit for MOS type field effect transistors, characterized in that each clamp diode is connected.