JPS6187357A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS6187357A JPS6187357A JP59195313A JP19531384A JPS6187357A JP S6187357 A JPS6187357 A JP S6187357A JP 59195313 A JP59195313 A JP 59195313A JP 19531384 A JP19531384 A JP 19531384A JP S6187357 A JPS6187357 A JP S6187357A
- Authority
- JP
- Japan
- Prior art keywords
- input
- output circuit
- circuit
- channel mos
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11898—Input and output buffer/driver structures
Abstract
Description
【発明の詳細な説明】
イ）産業上の利用分野
本発明は半導体集積回路装置に関し、特にマスタースラ
イス方式（ゲートアレイ方式）ＫよるＭＯＳ型大規模集
積回路に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a semiconductor integrated circuit device, and particularly to a MOS type large-scale integrated circuit using a master slice method (gate array method).
口〕従来技術
近年、特公昭５４−９３３７５号公報に開示されている
様に、一つの半導体チップ中に基本素子集合体を予め大
量に作成しておき開発品種に応じて配線マスクを作成し
て、所望の電気回路動作を有する大規模集積回路を完成
させるマスタースライス方式の半導体装置製造技術が開
発されている。[Background Art] In recent years, as disclosed in Japanese Patent Publication No. 54-93375, a large number of basic element assemblies are prepared in advance in one semiconductor chip, and wiring masks are prepared according to the developed product. 2. Description of the Related Art A master slicing semiconductor device manufacturing technique has been developed to complete a large-scale integrated circuit having a desired electrical circuit operation.
この種マスタースライス方式の半導体集積回路例えば、
ゲートアレイの場合には集積化にともない、そのトラン
ジスタサイズが大巾に縮小されつつある。この為にトラ
ンジスタのドレイン・ソース間耐圧が低下し、動作電源
電圧も下げられる方向にある。This kind of master slice type semiconductor integrated circuit, for example,
In the case of gate arrays, the transistor size is being reduced significantly as integration increases. For this reason, the withstand voltage between the drain and source of the transistor is lowered, and the operating power supply voltage is also being lowered.
而して、この様なゲートアレイは論理回路のみならす様
々な機能回路として構成され、マイコンの周辺回路とし
て高圧動作回路と供に各種の回路装置を作成しようとす
る要望がある。Therefore, such gate arrays are configured as various functional circuits in addition to logic circuits, and there is a desire to create various circuit devices together with high-voltage operation circuits as peripheral circuits of microcomputers.
しかしながら、上述の如く祈る半欅体回路は、トランジ
スタのゲート長を最小寸法として動作電源電圧も必要最
小限の電圧例えば５ｖに決められているので、これを例
えば１０ｖの電源電圧にて動作する高圧動作回路からの
１０Ｖの入出力を受けて動作させようとすると、トラン
ジスタのしきい値電圧やゲインファクタβの変化等の不
都合を招き、正常な動作を望む墨はでさない。However, in the above-mentioned semicircular circuit, the gate length of the transistor is the minimum dimension, and the operating power supply voltage is determined to be the minimum required voltage, for example, 5V, so this is set to a high voltage that operates at a power supply voltage of, for example, 10V. If an attempt is made to operate the device by receiving input/output of 10 V from the operating circuit, problems such as changes in the threshold voltage of the transistor and gain factor β will occur, and normal operation will not be possible.
この様に従来のゲートアレイの如きマスタースライス方
式の半導体回路装置に於いては、定格以上の高圧入力又
は高圧出力にロー能とする機能を備えておらず、設計・
倍電性の囲からも使い勝手の悪いものでめった。In this way, conventional master slice type semiconductor circuit devices such as gate arrays do not have a function to turn off high-voltage inputs or high-voltage outputs higher than the rated voltage, and the design and
It was difficult to use because of the double chargeability, so it was rare.
←う 発明が解決しようとする間粗点
不発明は上述の点に麻みてなされ、高圧入力又は高圧出
力を可能としてマスタースライス方式の半導体集積回路
装置の使い勝手の向上を目ざした八
本発明の半導体集積回路装置は、半導体チップ中に大量
の基本素子集合体と１２数の入出力回路とを備えた半導
体集積回路装置に於いて、各入出力回路単位毎に、Ｐチ
ャンネルＭＯＳ型トランジスタ群、ＮチャンネルＭ Ｏ
Ｓ ９ ）ランジスタ群、適数個のダイオード、並びに
適数個の抵抗を内設し、該入出力回路単位を１又はｙ！
、数単位使用して高１耐圧用入出力回路を構成するＫ
ｉｌして、上記ＮチャンネルＭＯＳ型トランジスタのゲ
ートを電源電圧に接続し、そのドレインを保護抵抗とし
ての上記抵抗に接続し、さらにそのソースを入力回路用
としての入力まだは出力回路用としての出力に接続する
と共に、このソースと電源電圧間及びこのソースとアー
ス間に保護用ダイオードとしての上記ダイオードを介在
したものである。←U While the invention is trying to solve the problem, the invention has been made in consideration of the above-mentioned points, and the semiconductor of the present invention is aimed at improving the usability of a master slice type semiconductor integrated circuit device by enabling high voltage input or high voltage output. An integrated circuit device is a semiconductor integrated circuit device that has a large number of basic element assemblies and 12 input/output circuits in a semiconductor chip. Channel MO
S9) A group of transistors, an appropriate number of diodes, and an appropriate number of resistors are provided internally, and the input/output circuit unit is 1 or y!
, several units are used to configure an input/output circuit for high voltage resistance.
il, the gate of the N-channel MOS type transistor is connected to the power supply voltage, its drain is connected to the above-mentioned resistor as a protection resistor, and its source is connected to the input for the input circuit and the output for the output circuit. The diode as a protection diode is interposed between this source and the power supply voltage and between this source and ground.
ホ）作 用
本発明の半導体集積回路装置に於いては、入出力回路内
に設けられたＮチャンネルＭＯＳ）ランジスタに依って
外部に加えられた高圧が該トランジスタと内部回路とで
分圧され、内部回路に直接高圧が印加される事はない。E) Function In the semiconductor integrated circuit device of the present invention, a high voltage applied externally by an N-channel MOS transistor provided in the input/output circuit is divided between the transistor and the internal circuit. High voltage is not applied directly to the internal circuits.
（へ）実施例
第６図はマスタースライス方式の本発明に係る半導体集
積回路チップ（財）の概略を示しており、該チップの中
央部には図示しないが基本素子集合体が大量Ｋ例えば２
０００程度行列配置され、瓶チップの周辺部には、発振
回路の他にもインターフェイス回路、ドライブ回路、あ
るいは各種の保護回路、又はアナログスイッチ回路等を
構成する為の入出力回路単位（Ｉ）・・・が複改個環状
に配列されている。尚、（Ｐ）・・・は各入出力回路単
位（Ｉ）に設けられた入出力端子であるう
所様な半導体集積回路装置の各入出力回路単位（１）・
・・には第４図に示す卯く、ＰチャンネルＭＯＳ型トラ
ンジスタ群（２）、 ＮチャンネルＭ ＯＳ Ｑ トラ
ンジスタｎ（３）、２個のダイオードｆ４１１４＋、２
個の抵抗！５）！５）、並びに入出力端子（Ｉ）を構１
戊する電極パッド（６）が予め配置ｄ形成されている。(F) Embodiment FIG. 6 shows an outline of a master slice type semiconductor integrated circuit chip (goods) according to the present invention, in which a large number of basic element assemblies (not shown) are located in the center of the chip, for example, 2
000 rows and columns, and around the bottle chip, in addition to the oscillation circuit, there are input/output circuit units (I) for configuring interface circuits, drive circuits, various protection circuits, analog switch circuits, etc. ... are arranged in a circular pattern. In addition, (P)... is an input/output terminal provided in each input/output circuit unit (I), and represents each input/output circuit unit (1) of a semiconductor integrated circuit device.
...shown in Fig. 4 include a P-channel MOS transistor group (2), an N-channel MOS Q transistor n (3), and two diodes f4114+, 2.
Individual resistance! 5)! 5), and the input/output terminal (I).
Hollow electrode pads (6) are pre-formed in a position d.
第１図、及び第２図に上述の如き構成の入出力回路単位
を用いて形成した出力回路及び入力回路を示す。FIG. 1 and FIG. 2 show an output circuit and an input circuit formed using input/output circuit units configured as described above.
第１図の５■電源を有する出力回路に於いて、（Ｑｌ）
（Ｑ２）は大々入出力回路単位（Ｉ）のＮチャンネルＭ
ＯＳ）ランジスタ群（２）の所望の２個のＮチャンネル
ＭＯＳトランジスタ、（ＤＩ）（Ｄ２）は夫々入出力回
路単位（１）のダイオード１．ｉｌ ｌ、ｉｌからなり
、（Ｄ５）は他の入出力回路単位（Ｉ’）のダイオード
（４）を使用している。（Ｒ）は同様に抵抗１５１ （
５）の単体もしくは並列接続体あるいは直列接続体が用
いられ、（Ｐ）は電極バンド（６）である。尚（ｒ）は
ＩＯＶ電源を有する外付回路に設けられており、内部の
出力回路の抵抗（９）より大巾に大きな値の抵抗値をも
っている。In the output circuit with 5■ power supply in Figure 1, (Ql)
(Q2) is roughly the N channel M of the input/output circuit unit (I)
(OS) Desired two N-channel MOS transistors of the transistor group (2), (DI) (D2) are the diodes 1. of the input/output circuit unit (1). It consists of il l and il, and (D5) uses the diode (4) of another input/output circuit unit (I'). (R) is the same resistance 151 (
5) may be used alone or in parallel or series connection, and (P) is an electrode band (6). Note that (r) is provided in an external circuit having an IOV power supply, and has a resistance value that is much larger than the resistance (9) of the internal output circuit.
ｉｑｒる出力回路は図示の如く、アースと電極バッドＩ
Ｐ＞間に抵抗値）と共に直列に接続されたＮチャンネル
ＭＯＳトランジスタ（Ｑｌ）、（Ｑ２）に放いてアース
側の該トランジスタ（Ｑ２）のフートは内部からの出力
■５が接続され、電極バッド（Ｐ）側の該トランジスタ
（Ｑｌ）のゲートは５ｖの内部電源電圧に接続されてい
る。尚、該トランジスタ（Ｑｌ）のソースと５Ｖの内部
電源電圧との間、並びにアースと祈るソースとの間、さ
らにはアースと該トランジスク（Ｑｌ）のドレインとの
間には夫々保護用のダイオード（Ｄｌ）、（Ｄ２〕、（
Ｄ３）が介在されている。The iqr output circuit is connected to the ground and electrode pad I as shown in the diagram.
An N-channel MOS transistor (Ql) is connected in series with (resistance value between The gate of the transistor (Ql) on the (P) side is connected to an internal power supply voltage of 5V. In addition, protective diodes ( Dl), (D2], (
D3) is interposed.
従って、内部からの出力ＶＳが高レベル“Ｈ＃の時は上
記トランジスタ（Ｑ２ ）（Ｑｌ ）ともにＯＮ状態で
あるので、電極パッド（Ｐ）の外部への出力Ｖ１は零Ｖ
に近い低レベル″Ｌ″となる。逆に内部からの出力■５
が低レベル＝Ｌ”の時はトランジスタ（Ｑ２）がＯＦＦ
状唇となり、両トランジスタ（Ｑｌ）、（Ｑ２−間の接
続電位Ｖ２は内部電源〔ＶＬとする〕からしきい値電圧
ＣＶｔｈとする〕を減じた値［Ｖｔ、−ＶｔｈＪ まで
充電され、その後トランジスタ（Ｑ５）もＯＦＦ状態と
なってしまい外部への出力■１は外付けのプルアップ抵
抗（ｒ）に依り１０Ｖの外部電圧〔ＶＨとする〕まで充
電され、１０■に近い高レベル″′Ｈ＃となる。この時
、一方のトランジスタ（Ｑｔ）のドレイン・ソース間電
圧は［ＶＬ−Ｖｔｈ） となり、他方のトランジスタ
（Ｑｌ）のドレイン・ソース間電圧は（ＶＨ−Ｖｔ＋Ｖ
ｔｈ）となり、１０ｖの外部電源電圧が内部の回路に印
加される事はない。Therefore, when the internal output VS is at a high level "H#", both the transistors (Q2) and (Ql) are in the ON state, so the output V1 to the outside of the electrode pad (P) is zero V.
It becomes a low level "L" close to . Conversely, output from inside ■5
When is low level=L”, transistor (Q2) is OFF
Both transistors (Ql) are charged to the value [Vt, -VthJ] obtained by subtracting the connection potential V2 between Q2 and the internal power supply [VL] to the threshold voltage CVth, and then the transistor (Q5) is also in the OFF state, and the output to the outside ■1 is charged to an external voltage of 10V [defined as VH] by the external pull-up resistor (r), and a high level ``'H'' close to 10■ At this time, the drain-source voltage of one transistor (Qt) becomes [VL-Vth), and the drain-source voltage of the other transistor (Ql) becomes (VH-Vt+V
th), and the external power supply voltage of 10V is not applied to the internal circuit.
、′ニー
次に第２図の５ｖ電源を有する入力回路につい ゛て
説明する。同図の入力回路は第１図の出力回路と同様に
ＮチャンネルＭＯＳ）ランジスタ（Ｑｌ）、ダイオード
（ＤＩ）（Ｄ２）（ＩＣ）、抵抗（Ｒ）、及び電極パッ
ド（Ｐ）を配ｗｓ、構成したものであり、出力回路と異
なっている所は上記トランジスタ（Ｑｌ）のソースをＮ
チャンネルＭＯＳトランジスタ群（２）のＮチャンネル
ＭＯＳトランジスタとＰチャンネル間Ｏ５）ランジスタ
群（３）のＰチャンネルＭＯＳトランジスタとからなる
アンプの入力に接続した点である。Next, the input circuit having a 5V power supply shown in FIG. 2 will be explained. Similar to the output circuit in FIG. 1, the input circuit in the figure includes an N-channel MOS transistor (Ql), a diode (DI) (D2) (IC), a resistor (R), and an electrode pad (P). The difference from the output circuit is that the source of the transistor (Ql) is connected to N
This point is connected to the input of an amplifier consisting of the N-channel MOS transistors of the channel MOS transistor group (2) and the P-channel MOS transistors of the P-channel transistor group (3).
従って、入力電圧Ｖ１が低レベル′Ｌ＃の時は、ゲート
に５ｖの内部電源電圧か印加されているトランジスタ（
Ｑｌ）はＯＮ状悪であるので、そのソース電位■２ も
低レベル“Ｌ″となり、アンプの出力Ｖｌは低レベル”
Ｌ＃である。逆に入力電圧Ｖ１が高レベル“Ｈ＃の時は
、トランジスタ（Ｑｌ） （７）７一ス電位ｖ２が［Ｖ
ｔ、−Ｖｔｈ３ まで充電されると、このトランジス
タ（Ｑｌ）はＯＦＦ状態となり、前述の出力回路の場合
と同様に５ｖ＃Ｊ作の内部回路に１０■の外部回路から
の印加電圧が直接加わる事なく出力■５は５ｖの高レベ
ル゛Ｈ”状庸となる。Therefore, when the input voltage V1 is at a low level 'L#, the transistor (
Ql) is in a bad ON state, so its source potential 2 also becomes low level "L", and the output Vl of the amplifier becomes low level.
It is L#. Conversely, when the input voltage V1 is at a high level "H#", the transistor (Ql) (7) 7 - potential v2 becomes [V
When charged to t, -Vth3, this transistor (Ql) becomes OFF state, and the applied voltage from the external circuit of 10■ is directly applied to the internal circuit of the 5v#J circuit, as in the case of the output circuit described above. Therefore, the output (5) becomes a high level "H" state of 5V.
（ト）発明の効果
本発明の半導体集積回路装Ｕは、以上の説明から明らか
な如く、入出力回路内に設けられたＮチャンネルＭＯＳ
）ランジスタに依って外部に加えられた高圧が該トラン
ジスタと内部回路とで分圧されるので、内部回路に直接
高圧が印加される事ばない。従って、本発明に依れば、
マ□スタスライス方式の＃ｒＳな装置に対して高圧入力
又は高圧出力を可能とする事ができ、この種半導体集積
回路の便いｌ≠手を大巾に向上できる。(G) Effects of the Invention As is clear from the above description, the semiconductor integrated circuit device U of the present invention has an N-channel MOS provided in the input/output circuit.
) Since the high voltage applied to the outside by the transistor is divided between the transistor and the internal circuit, the high voltage is not directly applied to the internal circuit. Therefore, according to the present invention,
High voltage input or high voltage output can be made possible for the #rS device of the master slice method, and the convenience of this type of semiconductor integrated circuit can be greatly improved.
第１図及び第２図は本発明の半導体集積回路装置の出力
回路、及び入力回路の回路図、第６図、及び第４図は本
発明係る装置の平面模式図及びそハ
の要部の平面模式図である。
（２）・・・ＭＯＳ型トランジスタ、（Ｄ）・・・ダイ
オード、（８）・・・抵抗、Φ）・・・電極パッド。1 and 2 are circuit diagrams of an output circuit and an input circuit of a semiconductor integrated circuit device according to the present invention, and FIGS. 6 and 4 are schematic plan views of the device according to the present invention and main parts thereof. FIG. (2)...MOS type transistor, (D)...diode, (8)...resistor, Φ)...electrode pad.
Claims (1)
出力回路とを備えた半導体集積回路装置に於いて、各入
出力回路単位毎に、ＰチャンネルＭＯＳ型トランジスタ
群、ＮチャンネルＭＯＳ型トランジスタ群、適数個のダ
イオード、並びに適数個の抵抗を内設し、該入出力回路
単位を１又は複数単位使用して高耐圧用入出力回路を構
成するに際して、上記ＮチャンネルＭＯＳ型トランジス
タのゲートを電源電圧に接続し、そのドレインを保護抵
抗としての上記抵抗に接続し、さらにそのソースを入力
回路用としての入力または出力回路用としての出力に接
続すると共にこのソースと電源電圧間及びこのソースと
アース間に保護用ダイオードとしての上記ダイオードを
介在した事を特徴とする半導体集積回路装置。1) In a semiconductor integrated circuit device that includes a large number of basic element assemblies and a plurality of input/output circuits in a semiconductor chip, each input/output circuit unit has a group of P-channel MOS type transistors and a group of N-channel MOS type transistors. When configuring a high voltage input/output circuit using one or more of the input/output circuit units, the N-channel MOS type transistor is The gate is connected to the power supply voltage, the drain is connected to the above-mentioned resistor as a protection resistor, and the source is connected to the input for the input circuit or the output for the output circuit, and the connection between this source and the power supply voltage and this A semiconductor integrated circuit device characterized in that the above-mentioned diode as a protection diode is interposed between a source and ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59195313A JPS6187357A (en) | 1984-09-18 | 1984-09-18 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59195313A JPS6187357A (en) | 1984-09-18 | 1984-09-18 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6187357A true JPS6187357A (en) | 1986-05-02 |
Family
ID=16339077
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59195313A Pending JPS6187357A (en) | 1984-09-18 | 1984-09-18 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6187357A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04116174U (en) * | 1991-03-25 | 1992-10-16 | 富士通電装株式会社 | Printed board |
| JPH05267658A (en) * | 1992-02-19 | 1993-10-15 | Nec Corp | Cmos semiconductor integrated circuit |
| JP2003504860A (en) * | 1999-06-29 | 2003-02-04 | コックレア リミティド | High voltage protection circuit of standard CMOS process |
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|---|---|---|---|---|
| JPS4830189A (en) * | 1971-08-19 | 1973-04-20 | ||
| JPS5130189A (en) * | 1974-09-06 | 1976-03-15 | Nippon Kotai Kogyo Kk | |
| JPS54140481A (en) * | 1978-04-21 | 1979-10-31 | Nec Corp | Semiconductor device |
| JPS5667962A (en) * | 1979-11-07 | 1981-06-08 | Mitsubishi Electric Corp | Gate protection circuit of mos field effect transistor |
-
1984
- 1984-09-18 JP JP59195313A patent/JPS6187357A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4830189A (en) * | 1971-08-19 | 1973-04-20 | ||
| JPS5130189A (en) * | 1974-09-06 | 1976-03-15 | Nippon Kotai Kogyo Kk | |
| JPS54140481A (en) * | 1978-04-21 | 1979-10-31 | Nec Corp | Semiconductor device |
| JPS5667962A (en) * | 1979-11-07 | 1981-06-08 | Mitsubishi Electric Corp | Gate protection circuit of mos field effect transistor |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04116174U (en) * | 1991-03-25 | 1992-10-16 | 富士通電装株式会社 | Printed board |
| JPH05267658A (en) * | 1992-02-19 | 1993-10-15 | Nec Corp | Cmos semiconductor integrated circuit |
| JP2003504860A (en) * | 1999-06-29 | 2003-02-04 | コックレア リミティド | High voltage protection circuit of standard CMOS process |
| JP4763192B2 (en) * | 1999-06-29 | 2011-08-31 | コクレア リミテッド | Standard CMOS process high voltage protection circuit |
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