JPS6257246A - Integrated circuit of field effect type semiconductor element - Google Patents
Integrated circuit of field effect type semiconductor elementInfo
- Publication number
- JPS6257246A JPS6257246A JP60197991A JP19799185A JPS6257246A JP S6257246 A JPS6257246 A JP S6257246A JP 60197991 A JP60197991 A JP 60197991A JP 19799185 A JP19799185 A JP 19799185A JP S6257246 A JPS6257246 A JP S6257246A
- Authority
- JP
- Japan
- Prior art keywords
- field
- elements
- effect semiconductor
- semiconductor element
- output signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
Landscapes
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、電界効果形半導体素子集積回路に関するも
のであって、特にカスケード接続によシROM を構
成する場合に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a field effect semiconductor element integrated circuit, and particularly to a case where a ROM is constructed by cascade connection.
第3図は従来のこの種の電界効果形半導体素子集積回路
の一例を示す説明図、第4図は第3図に示す集積回路の
等価回路図であり、図において(1)。FIG. 3 is an explanatory diagram showing an example of a conventional field-effect semiconductor element integrated circuit of this type, and FIG. 4 is an equivalent circuit diagram of the integrated circuit shown in FIG.
121 、 +3) 、 [41、+51 、 [6)
は並列に配設した入力信号線、+71 、 +81 、
+91 、 (10)、(11)、(12)、(13
)、(14) は各入力信号線111 、 +21
、 +31 、141 、 +51 、 +6)の方向
と直角な方向に並列に配設した出力信号線、(15)は
第1の電位をもつ電源に接続した第1’!位部、(16
)は電界効果形半導体素子である。121, +3), [41, +51, [6)
are input signal lines arranged in parallel, +71, +81,
+91, (10), (11), (12), (13
), (14) are each input signal line 111, +21
, +31 , 141 , +51 , +6), and output signal lines (15) are arranged in parallel in a direction perpendicular to the direction of the output signal lines 1'! position part, (16
) is a field effect semiconductor device.
入力信号線(1)、伐1.131 、[4) 、15)
、 (6)と出力信号線(7)。Input signal line (1), cutting 1.131, [4), 15)
, (6) and the output signal line (7).
(81、+’J 、 (10)、(11)、(12)、
(13)、(14) の延長線の交差する個所のうち
のいくつかの個所にそれぞれ電界効果形半導体素子(1
6)を配設し、各電界効果形半導体素子(16)のゲー
トをそれぞれ入力信号線111 、 +21 、 +3
+ 、 +41 、 +51 、 +61のいずれか1
つに接続し、各出力信号線+71 、 +81 、 +
91 、 (10)、(11)、(12)。(81, +'J, (10), (11), (12),
Field-effect semiconductor elements (1
6), and the gates of each field effect semiconductor element (16) are connected to input signal lines 111, +21, +3, respectively.
1 of +, +41, +51, +61
Connect to each output signal line +71, +81, +
91, (10), (11), (12).
(13)、(14)のそれぞれの延長線上の電界効果形
半導体素子(16)をカスケード接続し、これらの出力
信号線をそれぞれカスケード接続したそれぞれの延長線
上の電界効果形半導体素子(16)を介して第1電位部
(15)に接続して構成したものである。The field effect semiconductor elements (16) on each extension line of (13) and (14) are cascade-connected, and the field effect semiconductor elements (16) on each extension line are connected in cascade with these output signal lines. It is configured to be connected to the first potential section (15) via the first potential section (15).
複数本の入力信号線fil 、 +21 、 (31、
+41 、 +51 、 +61のうちの例えば3本の
入力信号線fil 、 +31 、 +51が電界効果
形半導体素子(16)をオンにする電位になったときに
は、ゲートが上記3本の入力信号線(1)。Multiple input signal lines fil, +21, (31,
For example, when three input signal lines fil, +31, and +51 among +41, +51, and +61 reach a potential that turns on the field-effect semiconductor element (16), the gate turns on the three input signal lines (16). ).
+31 、 +51に接続されている12個の電界効果
形半導体素子(16) (第4図で5OOI、 800
2 等の番号を付した素子のうち5011〜8014
、5ill〜2114 。12 field effect semiconductor elements (16) connected to +31 and +51 (5OOI, 800 in Figure 4)
2 Among the elements numbered 5011 to 8014
, 5ill~2114.
5211〜5214の12個)がオンとなシ、出力信号
線(14)が素子5O14、5114、5214を経て
第1%L位部(15)に電気的に接続される。When the 12 elements (5211 to 5214) are turned on, the output signal line (14) is electrically connected to the 1%L portion (15) via the elements 5O14, 5114, and 5214.
このように、複数本の入力信号線のそれぞれの電位の組
み合せによって、電界効果形半導体素子の配置状態で定
まる論理に従って、ある出力信号線のみが第1の電位を
もつ電源と接続されるという状態が得られROMが構成
される。In this way, a state in which only a certain output signal line is connected to a power supply having a first potential according to the logic determined by the layout of the field effect semiconductor element is created by combining the respective potentials of the plurality of input signal lines. is obtained and a ROM is constructed.
従来のROMの電界効果形半導体素子集積回路は以上の
ように構成されているので、出力信号線と第1の′電位
をもつ電源との間のカスケード接続の電界効果形半導体
素子の個数が多くなると、電界効果形半導体素子のオン
抵抗が合算されて、出力信号線と第1の電位をもつ電源
とが電気的に接続されてから該出力信号線が第1の電位
になるまでに、相当な時間を要するという問題があった
。Since the conventional ROM field-effect semiconductor element integrated circuit is configured as described above, a large number of field-effect semiconductor elements are connected in cascade between the output signal line and the power supply having the first potential. Then, the on-resistances of the field-effect semiconductor elements are added up, and from the time when the output signal line and the power supply having the first potential are electrically connected until the output signal line reaches the first potential, the on-resistance of the field-effect semiconductor element is added up. The problem was that it took a lot of time.
この時間を短くするために、個、々の電界効果形半導体
素子のゲート幅を広げてオン抵抗を下げる方法は、パタ
ーン面積が大きくなるという欠点がある。In order to shorten this time, the method of increasing the gate width of each field effect semiconductor element to lower the on-resistance has the disadvantage that the pattern area becomes large.
この発明は、上記の事情に鑑みてなされたもので、カス
ケード接続の電界効果形半導体素子の個数が増えても、
パターン面積が従来のものと同じ大きさで、出力信号線
が第1の電位をもつ電源に接続されてから第1の電位に
なるまでの時間が、余り長くならない電界効果形半導体
素子集積回路を提供することを目的とする。This invention was made in view of the above circumstances, and even if the number of cascade-connected field effect semiconductor elements increases,
A field-effect semiconductor element integrated circuit whose pattern area is the same as that of conventional circuits and whose output signal line does not take too long from being connected to a power source having a first potential to reaching the first potential. The purpose is to provide.
この発明に係る電界効果形半導体素子集積回路は、ゲー
トが同一の入力信号線に接続され、かつ第2の電極が同
一電位個所に接続される複数個の電界効果形半導体素子
を1つの電界効果形半導体素子にまとめたものである。The field-effect semiconductor element integrated circuit according to the present invention combines a plurality of field-effect semiconductor elements whose gates are connected to the same input signal line and whose second electrodes are connected to the same potential point into one field-effect semiconductor element. It is a type of semiconductor device.
複数個の電界効果形半導体素子を1つの電界効果形半導
体素子にまとめると、ゲートの幅を広くして、オン抵抗
を下げることができる。By combining a plurality of field effect semiconductor elements into one field effect semiconductor element, the gate width can be increased and the on-resistance can be lowered.
第1図はこの発明の一実施例を示す説明図、第2図は第
1図に示す実施例の回路図であり、図において第3図、
第4図の符号と同一の符号は相当する部分を示し、(1
6a)、(16b)、(15c)、(16d)、(16
e)。FIG. 1 is an explanatory diagram showing one embodiment of the present invention, and FIG. 2 is a circuit diagram of the embodiment shown in FIG.
The same reference numerals as those in FIG. 4 indicate corresponding parts, and (1
6a), (16b), (15c), (16d), (16
e).
(16f)は第3図、第4図に示す集積回路におけるそ
れぞれゲートが同一人力信号線に接続され、かつ第2の
電極が同一電位個所に接続される複数個の電界効果形半
導体素子を1つにまとめた電界効果形半導体素子である
。(16f) refers to a plurality of field-effect semiconductor elements in the integrated circuit shown in FIGS. 3 and 4 whose respective gates are connected to the same human input signal line and whose second electrodes are connected to the same potential point. These are field-effect semiconductor devices that are grouped together.
すなわち、第4図と第2図とを比較して素子5211〜
5214はゲートが同一人力信号線に接続され、かつ第
2の電極が同一電位個所に接続されているので、これを
1つの素子16eにまとめることができる。同様に素子
5201〜5204も1つの素子16f Kまとめるこ
とができる。このようにまとめると5113と5114
、8103と5104 、5illと8112゜51
01と5102の各1対の素子もゲートが同一人力信号
線に接続され、かつ第2の電極が同一電位個所に接続さ
れているので、それぞれ1つの素子16c。That is, by comparing FIG. 4 and FIG.
Since the gates of 5214 are connected to the same human input signal line and the second electrodes are connected to the same potential point, they can be combined into one element 16e. Similarly, the elements 5201 to 5204 can be combined into one element 16fK. To summarize like this, 5113 and 5114
, 8103 and 5104, 5ill and 8112°51
The gates of each pair of elements 01 and 5102 are connected to the same human input signal line, and the second electrodes are connected to the same potential point, so each element 16c is one element.
16d 、 16b 、 16aにまとめることができ
る。これらのまとめた素子はもとの素子の個数に応じて
ゲート幅が広められ、オン抵抗が下げられる。16d, 16b, and 16a. The gate width of these integrated devices is increased according to the number of original devices, and the on-resistance is lowered.
2n本の入力信号線の信号によって2n本の出力信号線
のうちの1本を選択するデコード回路の場合、nの値が
大きくなっても、出力信号線と第1の電位をもつ電源と
の間の電界効果形半導体素子のオン抵抗の和は、最小ゲ
ート幅の電界効果形半導体素子のオン抵抗の2倍を越え
ることはない。In the case of a decoding circuit that selects one of 2n output signal lines based on the signals of 2n input signal lines, even if the value of n becomes large, the connection between the output signal line and the power supply having the first potential is The sum of the on-resistances of the field-effect semiconductor elements between them does not exceed twice the on-resistance of the field-effect semiconductor element with the minimum gate width.
一方、第3図、第4図に示したような構成の集積回路に
おいては、出力信号線と第1の電位をもつ電源との間の
電界効果形半導体素子のオン抵抗の和は、1つの電界効
果形半導体素子(上記最小ゲート幅の電界効果形半導体
素子に相当する)のオン抵抗のn倍となる。On the other hand, in the integrated circuit having the configuration shown in FIGS. 3 and 4, the sum of the on-resistances of the field effect semiconductor elements between the output signal line and the power supply having the first potential is one It is n times the on-resistance of a field effect semiconductor element (corresponding to the field effect semiconductor element with the above-mentioned minimum gate width).
上記のように、第1図、第2図に示す構成の回路では、
カスケード接続の電界効果形半導体素子の個数が増えて
も、出力信号線と第1の電位をもつ電源との間の電界効
果形半導体素子のオン抵抗の和は、最小ゲート幅の電界
効果形半導体素子のオン抵抗の2倍を越えることがない
ので、出力信号線が第1の電位をもつ電源に接続されて
から第1の電位になるまでの時間は余り長くならない。As mentioned above, in the circuits with the configurations shown in FIGS. 1 and 2,
Even if the number of cascade-connected field-effect semiconductor devices increases, the sum of the on-resistances of the field-effect semiconductor devices between the output signal line and the power source with the first potential is the same as that of the field-effect semiconductor devices with the minimum gate width. Since it does not exceed twice the on-resistance of the element, the time from when the output signal line is connected to the power supply having the first potential until it reaches the first potential is not very long.
出力信号線に加えられる負荷容量の値が、集積回路中の
電界効果形半導体素子および配線の寄生容量に比して小
さい場合は、この効果は小さいが、出力信号線に加えら
れる負荷容量の方が大きい場合は、効果が大である。If the value of the load capacitance applied to the output signal line is smaller than the parasitic capacitance of the field effect semiconductor elements and wiring in the integrated circuit, this effect is small, but the load capacitance applied to the output signal line is When is large, the effect is large.
なお、電界効果形半導体素子はp型チャネルのものでも
、n型チャネルのものでもよい。Note that the field effect semiconductor element may be of a p-type channel or of an n-type channel.
また、出力信号線は抵抗体を介して第2の電位をもつ電
源へ接続されていてもよく、第2の電位へのプリチャー
ジを行なう回路に接続されていてもよく、他の型のチャ
ネルをもつ電界効果形半導体素子を介して第2の電位を
もつ電源に接続されていてもよい。Further, the output signal line may be connected to a power supply having a second potential via a resistor, or may be connected to a circuit that precharges to the second potential, or may be connected to a channel of another type. The power source may be connected to a power source having a second potential via a field effect semiconductor element having a second electric potential.
以上のとおシ、この発明によれば、出力信号線と第1の
電位をもつ電源との間のカスケード接続の電界効果形半
導体素子の個数が増えても、出力信号線が第1の電位を
もつ電源に接続されてから第1の電位になるまでの時間
が余り長くならないという効果がある。As described above, according to the present invention, even if the number of cascade-connected field-effect semiconductor elements between the output signal line and the power supply having the first potential increases, the output signal line remains at the first potential. This has the effect that the time from when it is connected to a power source until it reaches the first potential is not too long.
第1図はこの発明の一実施例を示す説明図、第2図は第
1図に示す実施例の回路図、第3図は従来のこの種の電
界効果形半導体素子集積回路の一例を示す説明図、第4
図は第3図に示す集積回路の回路図である。
図においてfl) 、 +21 、 +31 、 +4
1 、 +51 、 +61は入力信号線、+71 、
+81 、 [91、(10)、(11)、(12)
、(13)、(14) は出力信号線、(15)は第
1電位部、(16)、(16a)。
(16b)、(16c)、(16d)、(16e)、(
16f)は電界効果形半導体素子である。
なお各図中同一符号は同一または相当する部分を示す。FIG. 1 is an explanatory diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram of the embodiment shown in FIG. 1, and FIG. 3 is an example of a conventional field-effect semiconductor element integrated circuit of this type. Explanatory diagram, 4th
The figure is a circuit diagram of the integrated circuit shown in FIG. 3. In the figure fl), +21, +31, +4
1, +51, +61 are input signal lines, +71,
+81, [91, (10), (11), (12)
, (13), (14) are output signal lines, (15) is a first potential section, (16), (16a). (16b), (16c), (16d), (16e), (
16f) is a field effect semiconductor element. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
線を上記入力信号線の配設方向と直角な方向に互に並列
に配設し、上記入力信号線と上記出力信号線の延長線の
交差する個所のうちのいくつかの個所にそれぞれ電界効
果形半導体素子を配設し、上記電界効果形半導体素子の
ゲートをそれぞれ上記各入力信号線のいずれかに接続し
、上記各出力信号線をそれぞれ上記電界効果形半導体素
子のうちのいずれかの素子の第1の電極に接続し、上記
各電界効果形半導体素子の第2の電極は当該素子とカス
ケード接続される次段の電界効果形半導体素子の第1の
電極と接続するか又は上記カスケード接続の最終段とな
る各素子においては第1電位部に接続して構成される電
界効果形半導体素子集積回路において、 上記各電界効果形半導体素子のうちそのゲートが互に同
一の入力信号線に接続されかつその第2の電極が互に同
一電位の点に接続される複数の素子をまとめてそれぞれ
1個の素子を構成することを特徴とする電界効果形半導
体素子集積回路。[Claims] A plurality of input signal lines are arranged in parallel, a plurality of output signal lines are arranged in parallel with each other in a direction perpendicular to the arrangement direction of the input signal lines, and the input signal A field-effect semiconductor element is provided at some of the intersections of the extension line of the output signal line and the extension line of the output signal line, and the gate of the field-effect semiconductor element is connected to one of the input signal lines. and each of the output signal lines is connected to a first electrode of one of the field effect semiconductor devices, and the second electrode of each field effect semiconductor device is connected to the device in cascade. A field effect semiconductor element integrated circuit connected to the first electrode of the next stage field effect semiconductor element to be connected, or connected to the first potential section in each element at the final stage of the cascade connection. In a circuit, a plurality of field-effect semiconductor elements whose gates are mutually connected to the same input signal line and whose second electrodes are mutually connected to the same potential point are collectively combined into one. 1. A field-effect semiconductor element integrated circuit, characterized in that it comprises two elements.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60197991A JPS6257246A (en) | 1985-09-06 | 1985-09-06 | Integrated circuit of field effect type semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60197991A JPS6257246A (en) | 1985-09-06 | 1985-09-06 | Integrated circuit of field effect type semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6257246A true JPS6257246A (en) | 1987-03-12 |
Family
ID=16383691
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60197991A Pending JPS6257246A (en) | 1985-09-06 | 1985-09-06 | Integrated circuit of field effect type semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6257246A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6451531A (en) * | 1987-08-21 | 1989-02-27 | Fujitsu Ltd | Timing circuit for micro computer |
JPH0289341A (en) * | 1988-09-27 | 1990-03-29 | Matsushita Electron Corp | Semiconductor integrated circuit |
JPH02124231A (en) * | 1988-10-31 | 1990-05-11 | Hitachi Electron Eng Co Ltd | Parts assembling device |
JPH05175827A (en) * | 1991-06-05 | 1993-07-13 | Internatl Business Mach Corp <Ibm> | Integrated circuit array |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52116129A (en) * | 1976-03-26 | 1977-09-29 | Hitachi Ltd | Logical circuit |
JPS6089896A (en) * | 1984-08-06 | 1985-05-20 | Nec Corp | Memory device |
-
1985
- 1985-09-06 JP JP60197991A patent/JPS6257246A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52116129A (en) * | 1976-03-26 | 1977-09-29 | Hitachi Ltd | Logical circuit |
JPS6089896A (en) * | 1984-08-06 | 1985-05-20 | Nec Corp | Memory device |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6451531A (en) * | 1987-08-21 | 1989-02-27 | Fujitsu Ltd | Timing circuit for micro computer |
JPH0289341A (en) * | 1988-09-27 | 1990-03-29 | Matsushita Electron Corp | Semiconductor integrated circuit |
JPH02124231A (en) * | 1988-10-31 | 1990-05-11 | Hitachi Electron Eng Co Ltd | Parts assembling device |
JPH05175827A (en) * | 1991-06-05 | 1993-07-13 | Internatl Business Mach Corp <Ibm> | Integrated circuit array |
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