JPS55132065A - Cmos circuit - Google Patents

Cmos circuit

Info

Publication number
JPS55132065A
JPS55132065A JP4017879A JP4017879A JPS55132065A JP S55132065 A JPS55132065 A JP S55132065A JP 4017879 A JP4017879 A JP 4017879A JP 4017879 A JP4017879 A JP 4017879A JP S55132065 A JPS55132065 A JP S55132065A
Authority
JP
Japan
Prior art keywords
point
cmos circuit
channel
terminal
fett
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4017879A
Other languages
Japanese (ja)
Inventor
Kenji Sano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP4017879A priority Critical patent/JPS55132065A/en
Publication of JPS55132065A publication Critical patent/JPS55132065A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To improve performance of CMOS circuit sharply by inserting a diode between series-connected p-channel FET and n-channel FET in the forward direction against an impressed power.
CONSTITUTION: A diode D5 is formed between a p-channel FETTrB" and an n- channel FETTrA" simultaneously with the forming process thereof. In this constitution, when a high level signal is given to a terminal 1', TrA" is turned on and TrB" off, a point 2" is earthed and a point 3" becomes a forward drop level of D5. When a negative voltage is applied to a point 3", D5 and D7 are viased reversely, and a negative pole bootstrap can be applied to a positive side terminal 3" through capacity. When a low level signal is given to a terminal 1", TrB" is turned on and TrA" off, the point 3" becomes +V and the point 2" a forward drop level of D5. Then from applying +V or more to the point 2", D5 and D6 are biased reversely and a positive pole bootstrap can be applied. Thus the power voltage or those higher than that can be impressed, and performance of CMOS circuit can be improved accordingly.
COPYRIGHT: (C)1980,JPO&Japio
JP4017879A 1979-04-02 1979-04-02 Cmos circuit Pending JPS55132065A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4017879A JPS55132065A (en) 1979-04-02 1979-04-02 Cmos circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4017879A JPS55132065A (en) 1979-04-02 1979-04-02 Cmos circuit

Publications (1)

Publication Number Publication Date
JPS55132065A true JPS55132065A (en) 1980-10-14

Family

ID=12573515

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4017879A Pending JPS55132065A (en) 1979-04-02 1979-04-02 Cmos circuit

Country Status (1)

Country Link
JP (1) JPS55132065A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS574151A (en) * 1980-06-11 1982-01-09 Hitachi Ltd Mos integrated circuit device
JPH02256268A (en) * 1989-03-29 1990-10-17 Nec Corp Cmos output buffer for semiconductor integrated circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS574151A (en) * 1980-06-11 1982-01-09 Hitachi Ltd Mos integrated circuit device
JPS6360547B2 (en) * 1980-06-11 1988-11-24
JPH02256268A (en) * 1989-03-29 1990-10-17 Nec Corp Cmos output buffer for semiconductor integrated circuit

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