JPS58159363A - Input/output protecting device for semiconductor integrated circuit - Google Patents

Input/output protecting device for semiconductor integrated circuit

Info

Publication number
JPS58159363A
JPS58159363A JP57042177A JP4217782A JPS58159363A JP S58159363 A JPS58159363 A JP S58159363A JP 57042177 A JP57042177 A JP 57042177A JP 4217782 A JP4217782 A JP 4217782A JP S58159363 A JPS58159363 A JP S58159363A
Authority
JP
Japan
Prior art keywords
input
output
drain region
protecting device
prescribed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57042177A
Other languages
Japanese (ja)
Other versions
JPH0312472B2 (en
Inventor
Koji Eguchi
江口　宏次
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57042177A priority Critical patent/JPS58159363A/en
Publication of JPS58159363A publication Critical patent/JPS58159363A/en
Publication of JPH0312472B2 publication Critical patent/JPH0312472B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements

Abstract

PURPOSE:To reduce the area where a layout pattern occupies while maintaining input/output voltage withstanding features by a method wherein a part of an output protecting device is commonly used together with an input protecting device. CONSTITUTION:An input/output bonding pad 21 is connected to a drain region 22 provided with a prescribed diffused layer capacity of a Pch output transistor, and to the drain region 24 provided with a prescribed diffused layer capacity of an Nch output transistor, with the latter connection ohmically established with the intermediary of an N type diffused resistor 23. The drain region 24 of the Nch output transistor is further connected to an input gate 100 with the intermediary of another N type diffused resistor 25. The drain region 24 with a prescribed diffused capacity designed to protect the output end is partly used to protect the input end, which reduces the layout pattern by as much as 30%.

Description

【発明の詳細な説明】 本発＃４は牛導体集積回路の入出力保賎装盲に関する。[Detailed description of the invention] This issue #4 concerns the input/output protection of conductor integrated circuits.

従来、入出力保＠＊を扛、入力側と出力側にそれぞれ孤
別にその＋段を施している為にし１アウトパターンの占
有面積は入力保―襞電のみ、あるいは出力保線装置のみ
よりも当然のことながら大急〈なりていた０又、仁とに
相１ＩＩＩＡ溢Ｍ（Ｊｌ構造で入出力コモンタ１１の回
路執ＩＩにおいては、相補ｆｉＭＵ８＠造特Ｍのラッチ
了Ｖプ現象の発生防止に努めなけれはならない為にＮ型
Ｍ（ＪＩ９＠造又は１’ｆｉＭ０８構造による入出力保
線装置に比べｊ！に。Conventionally, input/output protection @* was used, and the + stage was separately applied to the input and output sides, so the area occupied by the 1-out pattern was naturally larger than that of input protection only or output protection device only. However, in order to prevent the occurrence of the phase 1 IIIA overflow M (in the circuit II of the input/output commoner 11 in the Jl structure, the latch of the complementary fiMU 8 @ Zoku M) was urgently required. Because of this, the N-type M (J!

し１アウトパターンの占有面積は大きくなっていたＯ しかるに、高集積密度化が進んでいる現在において、上
記し友人出力保ｇｉｉ装置を採用し続けることは、非常
に不合場的でかつ有効性に欠けている。However, in today's world where high integration densities are progressing, it is extremely inopportune to continue to use the above-mentioned output protection device, and it is not effective. Missing.

つまり、従来の入出力保線ｉｉｔｍが必費最小限のもの
であり九かどうかはかな９疑門のある所が多い為に１人
力保線及び出力保護に必ｌ！な最小限の機能を満足する
し１了クトバメーン倉見出し採用することによって、従
来の入出力保護パターンを採用してい次時よりも１更に
、高集積密度１ヒを図らなけれｔ’ｆならない。In other words, the conventional input/output track maintenance IITM is the minimum necessary cost, and since there are many places with 9 doubts, it is indispensable for one-man track maintenance and output protection! By adopting a main unit that satisfies the minimum functionality required, it is necessary to achieve an even higher integration density than the conventional input/output protection pattern.

本！ａ明は、従来の人出力保饅耐圧と同等、又はそれ以
上の耐圧管有し、＊（従来以上の高集積密度化を実現す
ることＹｔ目的としている。Book! The a-mei has pressure-resistant tubes that are equivalent to or higher than the conventional human power retention pressure, and aims to achieve higher integration density than the conventional one.

本％ＩＩＫよれは、入出力用ポンディングパッドからは
、出力保Ｉｉ装筺のみに接続され、入力ゲートは該出力
保ｗ！に装置の出力増と拡散抵抗會介して接続された構
造の入出力保５ｉｉｉ置が得られる。In this %IIK twist, the input/output bonding pad is connected only to the output protection Ii housing, and the input gate is connected to the output protection w! In this way, the output power of the device is increased and the input/output protection of the structure connected through the diffused resistor system is obtained.

本発＃４を相補ｔＩｉＭＵＳ構造における入出力保護装
置を例にとマて、従来の装置と比較しながら図Ｉｌ］を
用いてａ明してい〈０ １１１図は従来から！ｌ！施されてきた入出力保護装置
のレイアウトパターンを示し、！２図ＫＩＩＩＬ１図の
等価回路を示す。ｍｌｌｌ図、３１２図において、入出
力用ボンティングパッドｌｌ［、ｉ’ｃｈ出力トランジ
スタで所定の拡散層容量會もり友ドレイン領域１２と所
定のＮＪＩＩ拡散層抵抗１３ｔ−介したＮｃｈ出力トラ
ンジスタで所定の拡散増容ＪＩＩＶｒ４りたドレイン領
域１４へとオー建ｙ／ｉＩ！続される０次に人力ゲート
への接続は所定のＮｆＪ拡散層抵抗１５とＮ！１！第１
！【含む所定のポリシリコン抵抗１６とｔ介してボンデ
（ングバッド１１へと接続されている０尚ｍ１図、１Ｉ
ＬｌｔＩＡＫ＆ｖｈ−ｒ−矢ｆｌｌＯ（１人力ゲートへ
いたることｔ示している。このような従来の構造によれ
ばＰｃｈ、ｈｃｈ両出カドランジス７Ｉに対する出力保
Ｉ１１装置と、入力ブートに対する入力保躾ｆ！櫨とが
それぞれ孤別に形成し、配置をとる牛導体集積回路では
必然的にそのレイアウトパターンの占有伽横が大きくな
ってい危。Taking the present invention #4 as an example of an input/output protection device in a complementary tIiMUS structure, we will explain it using Figure Il while comparing it with a conventional device. l! The layout pattern of input/output protection devices that have been applied is shown! Figure 2 shows the equivalent circuit of Figure 1. In Fig. mlll and Fig. 312, the input/output bonding pad ll[, the i'ch output transistor has a predetermined diffusion layer capacitance, and the Nch output transistor has a predetermined value through the drain region 12 and a predetermined NJII diffusion layer resistor 13t. Diffusion volume increase JIIVr4 to the drain region 14 and O construction y/iI! The connection to the 0th order manual gate is a predetermined NfJ diffusion layer resistor 15 and N! 1! 1st
! [Contains a predetermined polysilicon resistor 16 and is connected to the bonding pad 11 via t.
LltIAK & vhr-arrow fllO (shows that it leads to a one-man power gate. According to such a conventional structure, there is an output protection device for both Pch and hch output quadrants 7I, and an input protection device for input boot). In conductor integrated circuits in which each conductor is formed and arranged separately, the layout pattern inevitably occupies a large amount of space, which is dangerous.

本発明では、入力保ｓｉ装置を出力保１ＩＩｆｔ置の一
部に共存させることによりて、従来の入出力保１耐圧を
推持した上でレイアウトパターンの占有面積を小さくし
たことｔ特徴としている。The present invention is characterized in that the area occupied by the layout pattern is reduced while maintaining the conventional input/output protection voltage by coexisting the input protection device in a part of the output protection area.

８３図は本楯＃４による入出力保護装置のレイアウトパ
ターンで、属４ｗＪはＩＮ３図の等価回路を示す。Figure 83 is the layout pattern of the input/output protection device according to this shield #4, and Gen 4wJ shows the equivalent circuit of the IN3 diagram.

尚、ｍ３図、５１４図で矢印１００は入力ゲートへいた
ることを示している。５１１３図、属４図において、入
出力用ボンティングパッド２１Ｆｉ、Ｐｃｈ出力トラン
ジスタで所定の拡散層容量を持りたドレイン領域２２と
所定のＮｊｌｌ拡散抵抗２３ｔ−介したＮｃｈ出力トラ
ンジスタで所定の拡散増容ｔｔ待ったドレイン領域２４
へとオーζｖｌ＠絖される。Note that the arrow 100 in Figures m3 and 514 indicates the direction to the input gate. In Fig. 5113 and Fig. 4, the input/output bonding pad 21Fi, the drain region 22 with a predetermined diffusion layer capacitance in the Pch output transistor, and the predetermined diffusion increase in the Nch output transistor via the predetermined Njll diffusion resistor 23t- are shown. drain area 24
It will be completed at ζvl@.

次に人力ゲートへの接続は前記Ｎｃｈ出力トランジスタ
のドレイン領域２４からｊＩ！＃Ｃｈ製拡散抵抗２５を
介して接続されている。このように出力保論用に設けら
れている所定の拡散ｍｓｔを持９たドレイン領域の−Ｓ
ｔ入力入力保検目も同時に担わせることによｐ、出力保
鏝装置と入力保麺装置とｔかなりの範囲で共有させたこ
とによりレイアウトパターンは従来のそれに比べて約３
０９６小さくすることが可能となりた０尚０本発＃！Ａ
に相補星ｈＬ）８構造以外の構造においても効果は得ら
れるものである◎Next, the connection to the human gate is from the drain region 24 of the Nch output transistor to jI! It is connected via a #Ch diffused resistor 25. -S of the drain region with a predetermined diffusion mst provided for output guarantee in this way.
The layout pattern has been reduced to approximately 3 times compared to the conventional one by having the output and input maintenance devices share a considerable range.
096 It is now possible to make the size smaller! A
The effect can also be obtained in structures other than the complementary star hL)8 structure.

【図面の簡単な説明】[Brief explanation of drawings]

謳１図は、従来の入出力保護装置を用いたし１アウトパ
タ一ン図で、謳２図は、１１１図の等価−略図である。 １８３図は、本発明の夾施例による入出力保ｓｉ！電を
用いたレイアウトパターン図で、５１１４図は％＠３図
の等価回略図である。 纂１＠１．畠２図、纂３図、畠４図において、１１゜・
２１・・・入出力用ボンティングパッド、１２．２２・
・・Ｐｃｈ出力トランジスタのドレイン領域、１３゜２
３・・ＮＪＩＩ拡歓抵抗、１４．２４・・・Ｎｃｈ出力
トランジスタのドレイン領域、１５．２５・・・Ｎ急拡
散抵抗、１６・・・Ｎａ１ｌ不純＠を含むボＩノシリコ
ン抵抗、１００・・１人力ゲートへ」に接続されること
ｔ示す矢印である。 拵１図 第３図Figure 1 is a one-out pattern diagram using a conventional input/output protection device, and Figure 2 is an equivalent schematic diagram of Figure 111. Figure 183 shows input/output protection si! according to another embodiment of the present invention. This is a layout pattern diagram using electricity, and Figure 5114 is an equivalent circuit diagram of Figure %@3.纂1@1. In Hatake 2, Hatake 3, and Hatake 4, 11°・
21... Input/output bonding pad, 12.22.
...Drain region of Pch output transistor, 13゜2
3...NJII expansion resistor, 14.24...Drain region of Nch output transistor, 15.25...N rapid diffusion resistor, 16...BoI silicon resistor containing Na1l impurity, 100... This is an arrow indicating that it is connected to the ``one-person powered gate''. Koshirae 1 diagram 3

Claims (1)

【特許請求の範囲】[Claims] 出力保Ｓ装置ｉｔｔ徊成する抵抗素子と容量素子の少な
くとも一部が入力保＠ａｔを兼ね備えたことを特徴とす
る牛導体集Ｓｔ回路の入出力保鰻懐筺０Output protection device (itt) Input/output protection device for a cow conductor collection St circuit characterized in that at least a part of the wandering resistance element and capacitance element also serves as input protection @at
JP57042177A 1982-03-17 1982-03-17 Input/output protecting device for semiconductor integrated circuit Granted JPS58159363A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57042177A JPS58159363A (en) 1982-03-17 1982-03-17 Input/output protecting device for semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57042177A JPS58159363A (en) 1982-03-17 1982-03-17 Input/output protecting device for semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPS58159363A true JPS58159363A (en) 1983-09-21
JPH0312472B2 JPH0312472B2 (en) 1991-02-20

Family

ID=12628698

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57042177A Granted JPS58159363A (en) 1982-03-17 1982-03-17 Input/output protecting device for semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS58159363A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61176146A (en) * 1985-01-31 1986-08-07 Toshiba Corp Semiconductor integrated circuit device
JPS61168650U (en) * 1985-04-10 1986-10-20
JPS63114409A (en) * 1986-10-31 1988-05-19 Hitachi Ltd Flip-flop circuit

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52132685A (en) * 1976-04-28 1977-11-07 Toshiba Corp Semiconductor integrated circuit device
JPS539484A (en) * 1976-07-14 1978-01-27 Nec Corp Integrated circuit device
JPS53116262A (en) * 1977-03-22 1978-10-11 Sumitomo Light Metal Ind Two stage disk for metal extrusion and metal extruding method
JPS5526683A (en) * 1978-08-16 1980-02-26 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit device
JPS574151A (en) * 1980-06-11 1982-01-09 Hitachi Ltd Mos integrated circuit device
JPS5763861A (en) * 1980-10-06 1982-04-17 Nec Corp Semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52132685A (en) * 1976-04-28 1977-11-07 Toshiba Corp Semiconductor integrated circuit device
JPS539484A (en) * 1976-07-14 1978-01-27 Nec Corp Integrated circuit device
JPS53116262A (en) * 1977-03-22 1978-10-11 Sumitomo Light Metal Ind Two stage disk for metal extrusion and metal extruding method
JPS5526683A (en) * 1978-08-16 1980-02-26 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit device
JPS574151A (en) * 1980-06-11 1982-01-09 Hitachi Ltd Mos integrated circuit device
JPS5763861A (en) * 1980-10-06 1982-04-17 Nec Corp Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61176146A (en) * 1985-01-31 1986-08-07 Toshiba Corp Semiconductor integrated circuit device
JPS61168650U (en) * 1985-04-10 1986-10-20
JPS63114409A (en) * 1986-10-31 1988-05-19 Hitachi Ltd Flip-flop circuit

Also Published As

Publication number Publication date
JPH0312472B2 (en) 1991-02-20

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