JPH0312472B2 - - Google Patents
Info
- Publication number
- JPH0312472B2 JPH0312472B2 JP57042177A JP4217782A JPH0312472B2 JP H0312472 B2 JPH0312472 B2 JP H0312472B2 JP 57042177 A JP57042177 A JP 57042177A JP 4217782 A JP4217782 A JP 4217782A JP H0312472 B2 JPH0312472 B2 JP H0312472B2
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- protection device
- bonding pad
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 description 7
- 230000000295 complement effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Description
【発明の詳細な説明】
本発明は半導体集積回路の入出力保護装置に関
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input/output protection device for a semiconductor integrated circuit.
従来、入出力保護装置は、入力側と出力側にそ
れぞれ孤別にその手段を施している為にレイアウ
トパターンの占有面積は入力保護装置のみ、ある
いは出力保護装置のみよりも当然のことながら大
きくなつていた。又、ことに相補型MOS構造で
入出力コモンタイプの回路装置においては、相補
型MOS構造特有のラツチアツプ現象の発生防止
に努めなければならない為にＮ型MOS構造又は
Ｐ型MOS構造による入出力保護装置に比べ更に、
レイアウトパターンの占有面積は大きくなつてい
た。 Conventionally, input/output protection devices have separate means on the input side and output side, so the area occupied by the layout pattern is naturally larger than that of only input protection devices or only output protection devices. Ta. In addition, especially in circuit devices with a complementary MOS structure and input/output common type, it is necessary to prevent the latch-up phenomenon peculiar to the complementary MOS structure, so input/output protection using an N-type MOS structure or a P-type MOS structure is required. Furthermore, compared to the equipment,
The area occupied by the layout pattern has been increasing.
しかるに、高集積密度化が進んでいる現在にお
いて、上記した入出力保護装置を採用し続けるこ
とは、非常に不合理的でかつ有効性に欠けてい
る。つまり、従来の入出力保護装置が必要最小限
のものであつたかどうかはかなり疑問のある所が
多い為に、入力保護及び出力保護に必要な最小限
の機能を満足するレイアウトパターンを見出し採
用することによつて、従来の入出力保護パターン
を採用していた時よりも、更に、高集積密度化を
図らなければならない。 However, in today's world where high integration densities are progressing, it is extremely unreasonable and lacking in effectiveness to continue to employ the above-mentioned input/output protection devices. In other words, there are many doubts as to whether conventional input/output protection devices were the minimum necessary, so we found and adopted a layout pattern that satisfies the minimum functions necessary for input and output protection. As a result, higher integration density must be achieved than when conventional input/output protection patterns are used.
本発明は、従来の入出力保護耐圧と同等、又は
それ以上の耐圧を有し、更に従来以上の高集積密
度化を実現することを目的としている。 The present invention aims to have a breakdown voltage equal to or higher than the conventional input/output protection breakdown voltage, and to realize higher integration density than the conventional one.
本発明によれば、入出力用ボンデイングパツド
からは、出力保護装置のみに接続され、入力ゲー
トは該出力保護装置の出力端と拡散抵抗を介して
接続された構造の入出力保護装置が得られる。 According to the present invention, an input/output protection device is obtained in which the input/output bonding pad is connected only to the output protection device, and the input gate is connected to the output end of the output protection device via a diffused resistor. It will be done.
本発明を相補型MOS構造における入出力保護
装置を例にとつて、従来の装置と比較しながら図
面を用いて説明していく。 The present invention will be explained using the drawings, taking an input/output protection device in a complementary MOS structure as an example and comparing it with a conventional device.
第１図は従来から実施されてきた入出力保護装
置のレイアウトパターンを示し、第２図に第１図
の等価回路を示す。第１図、第２図において、入
出力用ボンデイングパツド１１は、Pch出力トラ
ンジスタで所定の拡散層容量をもつたドレイン領
域１２と所定のＮ型拡散層抵抗１３を介したNch
出力トランジスタで所定の拡散層容量をもつたド
レイン領域１４へとオーミツク接続される。次に
入力ゲートへの接続は所定のＮ型拡散層抵抗１５
とＮ型不純物を含む所定のポリシリコン抵抗１６
とを介してボンデイングパツド１１へと接続され
ている。尚第１図、第２図において矢印１００は
入力ゲートへいたることを示している。このよう
な従来の構造によれはPch、Nch両出力トランジ
スタに対する出力保護装置と、入力ゲートに対す
る入力保護装置とをそれぞれ孤別に形成し、配置
しなければならない為に、入出力コモン回路形式
をとる半導体集積回路では必然的にそのレイアウ
トパターンの占有面積が大きくなつていた。 FIG. 1 shows a layout pattern of a conventional input/output protection device, and FIG. 2 shows an equivalent circuit of FIG. 1. 1 and 2, the input/output bonding pad 11 is a Pch output transistor with a drain region 12 having a predetermined diffusion layer capacitance and an Nch output transistor connected through a predetermined N-type diffusion layer resistor 13.
The output transistor is ohmicly connected to a drain region 14 having a predetermined diffusion layer capacitance. Next, the connection to the input gate is a predetermined N type diffusion layer resistor 15.
and a predetermined polysilicon resistor 16 containing N-type impurities.
It is connected to the bonding pad 11 via. In FIGS. 1 and 2, an arrow 100 indicates an input gate. The problem with this conventional structure is that the output protection device for both Pch and Nch output transistors and the input protection device for the input gate must be separately formed and placed, so an input/output common circuit format is used. In semiconductor integrated circuits, the layout pattern inevitably occupies a large area.
本発明では、入力保護装置を出力保護装置の一
部に共存させることによつて、従来の入出力保護
耐圧を維持した上でレイアウトパターンの占有面
積を小さくしたことを特徴としている。 The present invention is characterized in that by making the input protection device coexist with a part of the output protection device, the area occupied by the layout pattern is reduced while maintaining the conventional input/output protection breakdown voltage.
第３図は本発明による入出力保護装置のレイア
ウトパターンで、第４図は第３図の等価回路を示
す。 FIG. 3 shows a layout pattern of an input/output protection device according to the present invention, and FIG. 4 shows an equivalent circuit of FIG.
尚、第３図、第４図で矢印１００は入力ゲート
へいたることを示している。第３図、第４図にお
いて、入出力用ボンテイングパツド２１は、Pch
出力トランジスタで所定の拡散層容量を持つたド
レイン領域２２と所定のＮ型拡散抵抗２３を介し
たNch出力トランジスタ所定の拡散層容量を持つ
たドレイン領域２４へとオーミツク接続される。
次に入力ゲートへの接続は前記Nch出力トランジ
スタのドレイン領域２４から更にＮ型拡散抵抗２
５を介して接続されている。このように出力保護
用に設けられている所定の拡散層容量を持つたド
レイン領域の一部を入力保護の役目も同時に担わ
せることにより、出力保護装置と入力保護装置と
をかなりの範囲で共有させたことによりレイアウ
トパターンは従来のそれに比べて約30％小さくす
ることが可能となつた。尚、本発明は相補型
MOS構造以外の構造においても効果は得られる
ものである。 Incidentally, in FIGS. 3 and 4, the arrow 100 indicates the direction to the input gate. In FIGS. 3 and 4, the input/output bonding pad 21 is
The output transistor is ohmic-connected to a drain region 22 having a predetermined diffusion layer capacitance and a drain region 24 having a predetermined diffusion layer capacitance via a predetermined N-type diffused resistor 23 .
Next, the connection to the input gate is from the drain region 24 of the Nch output transistor to the N-type diffused resistor 2.
5. In this way, by making a part of the drain region that has a predetermined diffusion layer capacitance provided for output protection also play the role of input protection, the output protection device and the input protection device can be shared to a considerable extent. This made it possible to make the layout pattern approximately 30% smaller than the conventional one. Note that the present invention is a complementary type
Effects can also be obtained with structures other than MOS structures.
第１図は、従来の入出力保護装置を用いたレイ
アウトパターン図で、第２図は、第１図の等価回
路図である。第３図は、本発明の実施例による入
出力保護装置を用いたレイアウトパターン図で、
第４図は、第３図の等価回路図である。
第１図、第２図、第３図、第４図において、１
１，２１……入出力用ボンデイングパツド、１
２，２２……Pch出力トランジスタのドレイン領
域、１３，２３……Ｎ型拡散抵抗、１４，２４…
…Nch出力トランジスタのドレイン領域、１５，
２５……Ｎ型拡散抵抗、１６……Ｎ型不純物を含
むポリシリコン抵抗、１００……「入力ゲート」
に接続されることを示す矢印である。
FIG. 1 is a layout pattern diagram using a conventional input/output protection device, and FIG. 2 is an equivalent circuit diagram of FIG. 1. FIG. 3 is a layout pattern diagram using an input/output protection device according to an embodiment of the present invention.
FIG. 4 is an equivalent circuit diagram of FIG. 3. In Figures 1, 2, 3, and 4, 1
1, 21...Input/output bonding pad, 1
2, 22...Drain region of Pch output transistor, 13, 23...N type diffused resistor, 14, 24...
...Drain region of Nch output transistor, 15,
25...N-type diffused resistor, 16...Polysilicon resistor containing N-type impurity, 100..."input gate"
This is an arrow indicating that it is connected to.
Claims (1)
レイン電流路が接続された出力用トランジスタ
と、入出力兼用のボンデイングパツドと、前記ボ
ンデイングパツドと前記第１の節点との間に接続
された第１の拡散抵抗と、入力用トランジスタ
と、前記入力用トランジスタのゲートと前記第１
の節点との間に接続された第２の拡散抵抗を有
し、前記ボンデイングパツドと前記入力用トラン
ジスタのゲートとの間に前記第１及び第２の拡散
抵抗が直列に挿入接続されていることを特徴とす
る半導体集積回路の入出力保護装置。1. An output transistor with a source-drain current path connected between a power supply potential line and a first node, a bonding pad for both input and output, and an output transistor between the bonding pad and the first node. A connected first diffused resistor, an input transistor, a gate of the input transistor, and the first
a second diffused resistor connected between the bonding pad and the gate of the input transistor, and the first and second diffused resistors are inserted and connected in series between the bonding pad and the gate of the input transistor. An input/output protection device for a semiconductor integrated circuit, characterized by the following.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57042177A JPS58159363A (en) | 1982-03-17 | 1982-03-17 | Input/output protecting device for semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57042177A JPS58159363A (en) | 1982-03-17 | 1982-03-17 | Input/output protecting device for semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58159363A JPS58159363A (en) | 1983-09-21 |
| JPH0312472B2 true JPH0312472B2 (en) | 1991-02-20 |
Family
ID=12628698
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57042177A Granted JPS58159363A (en) | 1982-03-17 | 1982-03-17 | Input/output protecting device for semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58159363A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0669080B2 (en) * | 1985-01-31 | 1994-08-31 | 株式会社東芝 | Semiconductor integrated circuit device |
| JPS61168650U (en) * | 1985-04-10 | 1986-10-20 | ||
| JPS63114409A (en) * | 1986-10-31 | 1988-05-19 | Hitachi Ltd | Flip-flop circuit |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52132685A (en) * | 1976-04-28 | 1977-11-07 | Toshiba Corp | Semiconductor integrated circuit device |
| JPS539484A (en) * | 1976-07-14 | 1978-01-27 | Nec Corp | Integrated circuit device |
| JPS53116262A (en) * | 1977-03-22 | 1978-10-11 | Sumitomo Light Metal Ind | Two stage disk for metal extrusion and metal extruding method |
| JPS5526683A (en) * | 1978-08-16 | 1980-02-26 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit device |
| JPS574151A (en) * | 1980-06-11 | 1982-01-09 | Hitachi Ltd | Mos integrated circuit device |
| JPS5763861A (en) * | 1980-10-06 | 1982-04-17 | Nec Corp | Semiconductor device |
-
1982
- 1982-03-17 JP JP57042177A patent/JPS58159363A/en active Granted
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52132685A (en) * | 1976-04-28 | 1977-11-07 | Toshiba Corp | Semiconductor integrated circuit device |
| JPS539484A (en) * | 1976-07-14 | 1978-01-27 | Nec Corp | Integrated circuit device |
| JPS53116262A (en) * | 1977-03-22 | 1978-10-11 | Sumitomo Light Metal Ind | Two stage disk for metal extrusion and metal extruding method |
| JPS5526683A (en) * | 1978-08-16 | 1980-02-26 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit device |
| JPS574151A (en) * | 1980-06-11 | 1982-01-09 | Hitachi Ltd | Mos integrated circuit device |
| JPS5763861A (en) * | 1980-10-06 | 1982-04-17 | Nec Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58159363A (en) | 1983-09-21 |
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