JPH0244153B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a CMOS large-scale integrated circuit (hereinafter referred to as LSI).
This invention relates to a latch-up prevention circuit for preventing latch-up when a surge is applied between power supply terminals.

[Prior art]

Figure 1 shows a cross-sectional view of the semiconductor structure of the internal circuit of a CMOS LSI that takes conventional latch-up prevention measures. Note that this Figure 1 shows the N ^- substrate. In Figure 1, 1 is an N ^-substrate ,
2 is the drain P ⁺ diffusion region, 3 is the source P ⁺ diffusion region, 4 is the N ⁺ diffusion region, 5 is the P ^- well, 6 is the P ⁺ diffusion region, 7 is the drain N ⁺ diffusion region, 8 is the source
N ⁺ diffusion regions, 9 to 13 are oxide films, 14 and 15 are gate electrodes, 16 and 17 are wirings whose potential is _VDD , and 18 and 19 are wirings whose potential is _VSS .

An equivalent circuit when such a semiconductor structure causes latch-up is shown in FIG. 2a. In FIG. 2a, Tr ₁ is a lateral P ⁺ N - P - transistor with the drain P ⁺ diffusion region 2 of FIG. 1 as the emitter, the N ^- substrate 1 as the base, and the P ^{- well} 5 as the collector ^, Tr ₂
emitter source N ⁺ diffusion region 8, P ^- well 5
lateral with base and N ^- substrate 1 as collector
N ⁺ P ^- N ^- transistor, R ₁ is the resistance component of P ^- well 5 between N ^- substrate 1 and P ⁺ diffusion region 6, R ₂ is the resistance component of drain P ⁺ diffusion region 2, R ₃ is P ^- Well 5
and the resistance component of the N ^- substrate 1 between the N ⁺ diffusion region 4, R ₄
is the resistance component of the source N ⁺ diffusion region 8.

As shown in FIG. 1 above, an N ⁺ diffusion region 4 is provided on the N ^- substrate 1 and given a V _DD potential, and a P ⁺ diffusion region 6 is provided on the P ^- well 5 and given a V _SS potential. By giving the lateral transistor
For example, the collector resistances R ₁ and R ₃ of Tr ₁ and Tr ₂ are
In the figure above N ⁺ diffusion region 4 and P ⁺ diffusion region 6
can be made smaller than if they were placed at both the left and right ends of the figure. As a result, the base current flowing into the bases of the lateral transistors Tr ₁ and Tr ₂ can be reduced, and latch-up can be prevented to some extent.

Here, latch-up means that a surge current I from the outside flows into _the resistor _R1 from the emitter of the transistor _Tr3 as shown in FIG _. turns on, current flows through resistor _R3 , and transistor _Tr1
is turned on, current flows through the transistor Tr ₁ to the resistor R ₁ , and this keeps the transistor Tr ₂ on. Here, the emitter of transistor Tr ₃ is N ^-
This refers to the P ⁺ diffusion that connects to external terminals on the board.

Conventional latch-up countermeasures require the entire circuit to have the structure described above, which has the disadvantage of increasing the size of the pattern, lowering the degree of LSI integration, and complicating pattern design.

[Summary of the invention]

This invention was made to eliminate the drawbacks of the conventional ones as described above, and in an LSI configured on a substrate, a diode formed between both terminals of the V _DD and V _SS power supplies, a resistor, and a diode are used. A series body consisting of connected MOS transistors and connected in parallel with the above diode is provided, and the above MOS transistor is connected in parallel with the above diode.
By supplying the voltage across the transistor to the internal circuit, it is possible to significantly reduce surges from outside the LSI that trigger latch-up, and there is no need to take conventional latch-up measures for the internal circuit. The purpose is to provide a latch-up prevention circuit.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. Figure 3 shows the LSI configured on the N ^- board 1.
This figure shows an equivalent circuit when the latch-up prevention circuit of the present invention is provided between two power supply terminals V _SS and V _DD . In Figure 3, 20 is the V _SS terminal of the LSI,
21 is the V _DD terminal, 22 is both these terminals 20, 21
23 is the resistance component of the N ^- substrate 2 portion of this diode 22, 4 is the P ⁺ N ^- N ⁺ diode formed between the two.
0 is a series body connected in parallel with the diode 22, in the series body 40, 24 is a resistor, and 25 is an N whose gate, source, and P ^- well are short-circuited.
It is a channel MOS transistor. Also, 2
6 and 27 are terminals that supply power to the internal circuits of the LSI, respectively.

Also, Figure 4 shows P ⁺ N ^- N ⁺ diode 2 in Figure 3.
FIG. 2 is a structural cross-sectional view of No. 2. In Figure 4, 1 is
N ^- substrate, 28 is a P ⁺ diffusion region, 29 is an N ⁺ diffusion region, 30 is a wiring whose potential is V _SS , 31 is a wiring whose potential is V _DD
This is the wiring.

Next, the effects will be explained.

In FIG. 3, the resistance component 23 of the diode 22
are the P ⁺ diffusion region 28 and the N ⁺ diffusion region 29 in Fig. 4.
By making the distance between the two diffusion regions 28 and 29 as close as possible within the range allowed by the withstand voltage, and by making both the diffusion regions 28 and 29 extend parallel to each other and long on the pattern, the resistance between several Ω and several tens of Ω is achieved.
It can be done. In this way, when a surge is applied, the dynamic input resistance seen from the outside of the LSI is determined by the resistance component 23, so if the surge voltage is in the forward direction with respect to the diode 22, most of the surge current will flow through the diode 22 and the resistor 23. It flows out from the VDD terminal through the _VDD terminal.

Note that the dynamic resistance here is
When the surge voltage is a reverse voltage, it means the resistance (differential resistance) of the diode 22 at the time of breakdown, and when it is a forward voltage, it means the on-resistance of the diode 22.

Next, the surge voltage is applied to the diode 22,
In the case of the reverse direction, the breakdown voltage of the diode 22 is as high as about 50V, so the diode 22 alone is insufficient for protection from surge voltage, but the resistor 24 is connected in series with the internal circuit, N Since the channel MOS transistor 25 is connected in parallel to the internal circuit, the surge voltage is divided between the resistor 24 and the resistance component of the N-channel MOS transistor 25, and a small voltage is applied to the internal circuit. It provides protection from voltage. Here N channel MOS
Since the gate potential of the transistor 25 is the same as that of the P ^- well, the transistor 25 functions as a Zener diode between the drain and the P ^- well. The breakdown voltage varies depending on the gate oxide film thickness, but for example, if the gate oxide film thickness is 800 Å, it will be about 25V.
Also, the dynamic resistance value between the drain and source is about 20Ω when the channel width W is 1000 μm, so if the resistance value of the resistor 24 is now 30Ω, the voltage between terminals 26 and 27 is 25 + 25 × 20 / 30 + 20 =35(V).

Note that if the N-channel MOS transistor 25 is open source, the dynamic resistance value will be nearly twice as long as the channel width W is the same, and a MOS transistor is more suitable as a resistance divider circuit.

In this way, in the case of a forward voltage surge, the surge current flows out from the V _DD power supply through the diode 22 and hardly flows into the internal circuit, so the trigger current is not large enough to cause a latch-up. In addition, in the case of a reverse voltage surge, if the voltage value is greater than the breakdown voltage of the diode 22, the surge flows to the outside in the same way as in the forward direction. Even if the voltage is lower than the breakdown voltage, the current transiently flows to the outside through the junction capacitance of the diode 22. In addition, since the surge voltage is divided by the resistor 24 and the N-channel MOS transistor 25,
The voltage between terminals 26 and 27, that is, the voltage applied to the internal circuit, becomes small, and therefore, due to V/R=I, the surge current flowing into the internal circuit becomes small, and the trigger current does not become large enough to cause a latch-up. In this way latch-up can be prevented.

In addition, in the above embodiment, ^the
Although the case where the latch-up prevention circuit of the present invention is provided in a CMOS LSI has been described, the same effect can be achieved even when the substrate is P ^- . The equivalent circuit in this case is shown in Figure 4 as the power supply terminal V _SS
Only the resistor 25 on the side becomes the V _DD side.

〔Effect of the invention〕

As described above, if the latch-up prevention circuit of the present invention is placed around the chip, the power supply terminals V _SS ,
The influence of the surge applied between V _DD on the internal circuit can be significantly reduced, and there is no need to take conventional latch-up countermeasures for the internal circuit, and the pattern becomes smaller, allowing for higher LSI integration. In addition to the latch-up prevention circuit described above, if conventional countermeasures are applied to the internal circuit, the latch-up resistance can be significantly improved.

[Brief explanation of the drawing]

Figure 1 shows the conventional latch-up countermeasure.
A diagram showing an example of a CMOS circuit. FIGS. 2a and 2b are diagrams showing an equivalent circuit of the circuit in FIG. 1 and an equivalent circuit at the time of latch-up of the circuit, respectively. FIG. The equivalent circuit diagram of the circuit, FIG. 4, is a cross-sectional view of the semiconductor structure of the diode in the circuit of FIG. 20...V _SS power supply terminal, 21...V _DD power supply terminal,
22...P ⁺ N ^- N ⁺ diode, 24... Resistor, 2
5...N-channel MOS transistor whose gate, source, and P ^- well are short-circuited, 40...Series body. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] 1 A latch-up prevention circuit in a CMOS large-scale integrated circuit configured on a N ^- or P ^- substrate, which includes a gate, source, P ^- between a V _DD power supply terminal and a V _SS power supply terminal. A series body formed by connecting a resistor in series with either an N-channel MOS transistor whose well is short-circuited or an N-channel MOS transistor whose gate, source, and P ^- substrate are short-circuited, and a P ⁺
Latch-up prevention characterized by connecting an N ^- N ⁺ or N ⁺ P ^- P ⁺ diode in parallel, and supplying the voltage across the N-channel MOS transistor to the internal circuit of the CMOS large-scale integrated circuit. circuit.