JPH0553075B2 - - Google Patents
Info
- Publication number
- JPH0553075B2 JPH0553075B2 JP20300486A JP20300486A JPH0553075B2 JP H0553075 B2 JPH0553075 B2 JP H0553075B2 JP 20300486 A JP20300486 A JP 20300486A JP 20300486 A JP20300486 A JP 20300486A JP H0553075 B2 JPH0553075 B2 JP H0553075B2
- Authority
- JP
- Japan
- Prior art keywords
- input
- diffusion layer
- region
- protection
- protection diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000009792 diffusion process Methods 0.000 claims description 42
- 230000005669 field effect Effects 0.000 description 13
- 238000010586 diagram Methods 0.000 description 8
- 230000005611 electricity Effects 0.000 description 6
- 230000003068 static effect Effects 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 230000006378 damage Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 231100000989 no adverse effect Toxicity 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は集積回路（以下、ICという）の静電
気による破壊を防止するための入出力保護回路に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input/output protection circuit for preventing damage to an integrated circuit (hereinafter referred to as IC) due to static electricity.
ICの静電気による破壊を防止するための入出
力保護回路はIC設計のうえで重要であり、従来
種々の構造が考えられてきた。例えば、第５図は
従来の一般的な入力保護回路の等価回路図であ
り、入力端子３３より入力抵抗３４、入力配線３
７を介して論理回路３８内のMOS電界効果トラ
ンジスタのゲート電極等に接続され、入力配線３
７からは入力保護ダイオード３５，３６を介し
て、それぞれ電源ラインVDD、接地ラインGNDに
接続されている。静電気が入力端子３３に加わつ
た時には、この入力保護回路入力抵抗３４及び入
力保護ダイオード３５，３６を介して電荷が電源
ラインVDDもしくは接地ラインGNDに流れる。入
力保護が必要な時には通常電源ラインVDDや接地
ラインGNDには電位が与えられていないので、
入力配線３７と電源ラインVDDもしくは接地ライ
ンGNDとの間の電位差は入力保護ダイオード３
５，３６の降伏電圧におさえられて論理回路３８
内のMOS電界効果トランジスタを破壊から防ぐ。
Input/output protection circuits to prevent damage to ICs due to static electricity are important in IC design, and various structures have been considered in the past. For example, FIG. 5 is an equivalent circuit diagram of a conventional general input protection circuit.
7 to the gate electrode of the MOS field effect transistor in the logic circuit 38, and the input wiring 3
7 are connected to the power supply line V DD and the ground line GND via input protection diodes 35 and 36, respectively. When static electricity is applied to the input terminal 33, charges flow to the power supply line VDD or the ground line GND via the input protection circuit input resistor 34 and input protection diodes 35, 36. When input protection is required, no potential is normally applied to the power supply line V DD or ground line GND, so
The potential difference between the input wiring 37 and the power supply line V DD or ground line GND is determined by the input protection diode 3.
The logic circuit 38 is suppressed to the breakdown voltage of 5 and 36.
Prevents the internal MOS field effect transistor from being destroyed.
かかる第５図に示した従来の入力保護回路にお
いては、入力抵抗３４の抵抗が大きいほど、又、
ダイオード３５，３６の接合面積が大きければ大
きいほど、静電耐量は大きくなるが入力抵抗３４
の抵抗とダイオード３５，３６の寄生容量とによ
る時定数が大きくなり、動作スピードが低下する
などの特性面への悪影響のため、入力抵抗３４の
抵抗値、及びダイオード３５，３６の接合面積は
それほど大きくできない。
In the conventional input protection circuit shown in FIG. 5, the larger the resistance of the input resistor 34,
The larger the junction area of the diodes 35 and 36, the greater the electrostatic capacity, but the input resistance 34
The resistance value of the input resistor 34 and the junction area of the diodes 35, 36 are not so large because the time constant due to the resistance of the input resistor 34 and the parasitic capacitance of the diodes 35, 36 increases, which adversely affects characteristics such as a decrease in operating speed. I can't make it bigger.
また、ICの出力部が第６図に示すように、
MOS電界効果トランジスタ４０のドレインが電
源に接続されることなく出力端子４１に接続され
ている。この出力端子４１にも静電気が加わつて
MOS電界効果トランジスタ４０のドレイン接合
を破壊することがあり、この破壊を防止する保護
回路として出力端子４１とMOS電界効果トラン
ジスタ４０のドレインとの間に第５図の入力抵抗
３４と保護ダイオード３５，３６とからなる保護
回路を挿入することが考えられる。しかしなが
ら、第６図に示すような、オープンドレイン構造
の場合、MOS電界効果トランジスタ４０のドレ
インとICの動作電源電位よりも高い電源電位VDD
が与えられる配線との間にプルアツプ抵抗３９が
接続されるので、出力端子４１と電源ラインVDD
との間に保護ダイオードを接続するとこの保護ダ
イオードが順方向バイアスされることがあるの
で、このような保護ダイオードを接続することが
できない。 Also, as shown in Figure 6, the output section of the IC is
The drain of the MOS field effect transistor 40 is connected to an output terminal 41 without being connected to a power source. Static electricity is also added to this output terminal 41.
The drain junction of the MOS field effect transistor 40 may be destroyed, and as a protection circuit to prevent this destruction, an input resistor 34 and a protection diode 35 as shown in FIG. 5 are installed between the output terminal 41 and the drain of the MOS field effect transistor 40. It is conceivable to insert a protection circuit consisting of 36. However, in the case of an open drain structure as shown in FIG. 6, the power supply potential V DD is higher than the operating power supply potential of the drain of the MOS field effect transistor 40 and the IC.
Since the pull-up resistor 39 is connected between the output terminal 41 and the power supply line V DD
If a protection diode is connected between the terminal and the terminal, the protection diode may become forward biased, so such a protection diode cannot be connected.
本発明によれば、入力端子に抵抗器を介して接
続される入力保護ダイオード領域もしくは出力端
子に接続されるドレイン領域に隣接してこれら入
力保護ダイオード領域もしくはドレイン領域と同
導電型領域を形成し、入力端子もしくは出力端子
に高電圧が静電気等により加わつた時この同導電
型領域が入力保護ダイオード領域もしくはドレイ
ン領域に空乏層によつて接続せしめられる保護回
路を得る。
According to the present invention, a region of the same conductivity type as the input protection diode region or the drain region is formed adjacent to the input protection diode region connected to the input terminal via the resistor or the drain region connected to the output terminal. When a high voltage is applied to the input terminal or the output terminal due to static electricity or the like, a protection circuit is obtained in which the region of the same conductivity type is connected to the input protection diode region or the drain region through a depletion layer.
本発明によれば、通常動作時には同導電型領域
は入力保護ダイオード領域もしくはドレイン領域
と離れているので動作スピードを低下せしめた
り、プルアツプ抵抗を通して電流が流れたりする
ことはない。高電圧動作時には入力保護ダイオー
ドは電流容量が増し、保護効果がより高信頼度に
なり、またドレイン領域の電圧は保護ダイオード
で制限されることとなり十分な保護効果を得るこ
とができる。同導電型領域は十分大きくできるの
で保護動作時に保護回路が破壊されることもな
い。 According to the present invention, during normal operation, the same conductivity type region is separated from the input protection diode region or the drain region, so that the operation speed is not reduced and no current flows through the pull-up resistor. During high voltage operation, the current capacity of the input protection diode increases, making the protection effect more reliable, and since the voltage in the drain region is limited by the protection diode, a sufficient protection effect can be obtained. Since the same conductivity type region can be made sufficiently large, the protection circuit will not be destroyed during the protection operation.
次に、図面を参照して本発明をより詳細に説明
する。
Next, the present invention will be explained in more detail with reference to the drawings.
第１図は本発明の第１の実施例の等価回路図、
第２図はその構造断面図である。入力端子１は入
力抵抗２に接続され、入力抵抗２は保護ダイオー
ド３，４，５，６に接続されているが、通常入力
時にはダイオード５，６は接続されていない。か
かる構造は第２図のように得ることができる。す
なわち、N-基板１８にＰ型の抵抗領域１１とP-
型のウエル領域１７とP+型の拡散層７，８とが
形成されているP+型の拡散層７，８は空乏層１
５でつながる程度に隣接されている。P-型のウ
エル領域１７中にはN+型の拡散層９，１０とが
雲乏層１６でつながる程度に隣接して形成されて
いる。P+拡散層７とN-基板１８とで保護ダイオ
ード４を、P+拡散層８とN-基板１８とで保護ダ
イオード６をN+拡散層９とP-ウエル領域１７と
で保護ダイオード３を、N+拡散層１０とP-ウエ
ル領域１７とで保護ダイオード５をそれぞれ形成
している。入力端子１は抵抗領域１１に配線で接
続され、抵抗領域１１は配線でP+拡散層７とN+
拡散層９とのみに接続されている。 FIG. 1 is an equivalent circuit diagram of the first embodiment of the present invention,
FIG. 2 is a sectional view of its structure. The input terminal 1 is connected to an input resistor 2, and the input resistor 2 is connected to protection diodes 3, 4, 5, and 6, but the diodes 5 and 6 are not connected during normal input. Such a structure can be obtained as shown in FIG. That is, the P type resistance region 11 and the P -
The P + type well region 17 and the P + type diffusion layers 7 and 8 are formed as a depletion layer 1.
They are adjacent to each other to the extent that they are connected by 5. In the P − type well region 17 , N + type diffusion layers 9 and 10 are formed adjacent to each other to the extent that they are connected by the cloud depletion layer 16 . The P + diffusion layer 7 and the N - substrate 18 form a protection diode 4; the P + diffusion layer 8 and N - substrate 18 form a protection diode 6; the N + diffusion layer 9 and the P - well region 17 form a protection diode 3. , the N + diffusion layer 10 and the P - well region 17 form a protection diode 5, respectively. Input terminal 1 is connected to resistance region 11 by wiring, and resistance region 11 is connected to P + diffusion layer 7 and N + by wiring.
It is connected only to the diffusion layer 9.
入力端子１に通常の入力信号が加わつた場合
P+拡散層７からの空乏層およびN-拡散層からの
空乏層１６はそれぞれP+拡散層８やN+拡散層１
０に達しないようにしているので、入力保護ダイ
オード３，４のみが入力保護回路に加わつてお
り、入力保護回路の時定数は小さいので高い動作
スピードが得られる。 When a normal input signal is applied to input terminal 1
The depletion layer from the P + diffusion layer 7 and the depletion layer 16 from the N - diffusion layer are the P + diffusion layer 8 and the N + diffusion layer 1, respectively.
0, only the input protection diodes 3 and 4 are added to the input protection circuit, and since the time constant of the input protection circuit is small, high operating speed can be obtained.
一方、入力端１に正の高電圧が印加された場合
にはN+拡散層９と１０とはP-型ウエル領域１７
の接合に発生した空乏層１６により、同電位とな
り、等価的にダイオード３と５とが接続されたこ
とになる。また、入力端子１に負の高電圧が印加
された場合にはP+拡散層７と８とはN-基板１８
の接合に発生した空乏層１５により同電位とな
り、等価的にダイオード４と６とが接続されたこ
とになる。この結果高電圧印加時には保護ダイオ
ードの電流容量が大きくなり、保護回路の耐圧が
高くなる。このP+拡散層７と８及びN+拡散層９
と１０とが高電圧印加時にのみ、同電位となるよ
うに設計するのは空乏層巾の計算により、それぞ
れの領域７，８，９，１０の濃度間隔を決定する
ことにより容易に設計できる。 On the other hand, when a positive high voltage is applied to the input terminal 1, the N + diffusion layers 9 and 10 are
Due to the depletion layer 16 generated at the junction of the diodes 3 and 5, the potential becomes the same, and the diodes 3 and 5 are equivalently connected. Furthermore, when a negative high voltage is applied to the input terminal 1, the P + diffusion layers 7 and 8 are different from the N - substrate 18.
Due to the depletion layer 15 generated at the junction of the diodes 4 and 6, the potential becomes the same, and the diodes 4 and 6 are equivalently connected. As a result, when a high voltage is applied, the current capacity of the protection diode increases, and the withstand voltage of the protection circuit increases. This P + diffusion layer 7 and 8 and N + diffusion layer 9
It is easy to design so that and 10 have the same potential only when a high voltage is applied by calculating the depletion layer width and determining the concentration intervals of the respective regions 7, 8, 9, and 10.
第３図は本発明の出力保護回路に適用した第２
の実施例を示す等価回路図で、第４図はそれを実
現した構造断面図である。出力MOS電界効果ト
ランジスタ２０のドレインは直接出力端子２１と
プルアツプ抵抗２８を介してプルアツプ用の高電
圧が与えられる電源ラインVDD′とに接続されて
おり、通常動作時には保護ダイオード２２，２３
は出力端子２１に接続されていない。具体的には
N-基板３１にP+型拡散層２４とP-型ウエル領域
３０とを有している。P+型拡散層２４とN-基板
３１とで保護ダイオード２２を形成している。
P-型ウエル領域３０にはN+拡散層２５，２６，
２７，３２を有し、N+拡散層２５はMOS電界効
果トランジスタのソース、N+拡散層２６はMOS
電界効果トランジスタ２０のドレインを形成し、
N+拡散層２７とP-型ウエル領域３０とで保護ダ
イオード２３を形成し、N+拡散層３２はプルア
ツプ抵抗２８を形成しN+拡散層２６と２７とは
空乏層２９でつながる程度に隣接配置されてい
る。ドレイン領域であるN+拡散層２６は出力端
子２１に接続され、N+拡散層２７とP+拡散層２
４とが配線で接続されている。N+拡散層３２は
出力端子２１とプルアツプ用の高い電位の与えら
れる電源ラインVDDとに接続されている。 Figure 3 shows the second example applied to the output protection circuit of the present invention.
FIG. 4 is an equivalent circuit diagram showing an embodiment of the present invention, and FIG. 4 is a cross-sectional view of a structure that realizes it. The drain of the output MOS field effect transistor 20 is directly connected to the output terminal 21 and the power supply line V DD ' to which a high voltage for pull-up is applied via a pull-up resistor 28. During normal operation, the drain is connected to the power supply line V DD ' to which a high voltage for pull-up is applied.
is not connected to the output terminal 21. in particular
The N − substrate 31 has a P + type diffusion layer 24 and a P − type well region 30 . A protection diode 22 is formed by the P + type diffusion layer 24 and the N - substrate 31.
In the P - type well region 30, N + diffusion layers 25, 26,
27, 32, the N + diffusion layer 25 is the source of the MOS field effect transistor, and the N + diffusion layer 26 is the source of the MOS field effect transistor.
forming the drain of the field effect transistor 20;
The N + diffusion layer 27 and the P - type well region 30 form a protection diode 23, the N + diffusion layer 32 forms a pull-up resistor 28, and the N + diffusion layers 26 and 27 are adjacent to each other to the extent that they are connected by a depletion layer 29. It is located. The N + diffusion layer 26, which is a drain region, is connected to the output terminal 21, and the N + diffusion layer 27 and the P + diffusion layer 2
4 are connected by wiring. The N + diffusion layer 32 is connected to the output terminal 21 and the power supply line V DD to which a high potential for pull-up is applied.
出力端子２１が正常動作し、通常の出力を生じ
ている時にはN+拡散層２６はN+拡散層２７とは
離間しており、出力に大きた寄生容量が加わるこ
とはない。出力端子２１に正の大きな電圧が加わ
るとドレイン領域であるN+拡散層２６から空乏
層２９が伸張し、N+拡散層２７につながつてN+
拡散層２６と２７とを同電位にする。N+拡散層
２７はP+拡散層２４につながつているので、保
護ダイオード２２もしくは２３の降伏により、
N+拡散層２６とP-型のウエル領域３０との間の
電位差を制限してMOS電界効果トランジスタを
破壊から防ぐ。 When the output terminal 21 is operating normally and producing a normal output, the N + diffusion layer 26 is separated from the N + diffusion layer 27, and no large parasitic capacitance is added to the output. When a large positive voltage is applied to the output terminal 21, the depletion layer 29 extends from the N + diffusion layer 26 which is the drain region, connects to the N + diffusion layer 27, and becomes N +.
Diffusion layers 26 and 27 are made to have the same potential. Since the N + diffusion layer 27 is connected to the P + diffusion layer 24, breakdown of the protection diode 22 or 23 causes
The potential difference between the N + diffusion layer 26 and the P - type well region 30 is limited to prevent the MOS field effect transistor from being destroyed.
以上説明したように、入出力保護ダイオードが
高電圧印加時にのみ、入出力部に接続されるよう
に構成することにより、通常使用時は動作スピー
ドの低下等の特性に悪影響を及ぼすことはなく、
静電気などに対し耐量の高い入出力保護回路を構
成できる。
As explained above, by configuring the input/output protection diode to be connected to the input/output section only when high voltage is applied, there is no adverse effect on characteristics such as a decrease in operating speed during normal use.
It is possible to configure an input/output protection circuit with high resistance to static electricity.
第１図は本発明の第１の実施例を示す等価回路
図、第２図は本発明の第１の実施例を実現する構
造断面図、第３図は本発明の第２の実施例を示す
等価回路図、第４図は本発明の第２の実施例を実
現する構造断面図、第５図は従来の入力保護回路
の回路図、第６図は従来のオープンドレイン型出
力部の等価回路図である。
１……入力端子、２……入力抵抗、３，４，
５，６……ダイオード、７，８，１１……P+拡
散層、９，１０……N+拡散層、１５，１６……
空乏層、１７……P-型ウエル領域、１８……N-
基板、２０……MOS電界効果トランジスタ、２
１……出力端子、２２，２３……ダイオード、２
４……P+拡散層、２５，２６，２７，３２……
N+拡散層、２８……プルアツプ抵抗、２９……
空乏層、３０……P-型ウエル領域、３１……N-
基板、３３……入力端子、３４……入力抵抗、３
５，３６……ダイオード、３７……入力配線、３
８……論理回路、３９……プルアツプ抵抗、４０
……MOS電界効果トランジスタ、４１……出力
端子。
FIG. 1 is an equivalent circuit diagram showing a first embodiment of the present invention, FIG. 2 is a cross-sectional view of a structure realizing the first embodiment of the present invention, and FIG. 3 is a diagram showing a second embodiment of the present invention. 4 is a cross-sectional view of a structure realizing the second embodiment of the present invention, FIG. 5 is a circuit diagram of a conventional input protection circuit, and FIG. 6 is an equivalent circuit diagram of a conventional open-drain type output section. It is a circuit diagram. 1...Input terminal, 2...Input resistance, 3, 4,
5, 6...Diode, 7, 8, 11...P + diffusion layer, 9, 10...N + diffusion layer, 15, 16...
Depletion layer, 17...P - type well region, 18...N -
Substrate, 20...MOS field effect transistor, 2
1... Output terminal, 22, 23... Diode, 2
4...P + diffusion layer, 25, 26, 27, 32...
N + diffusion layer, 28...Pull-up resistor, 29...
Depletion layer, 30...P - type well region, 31... N-
Board, 33...Input terminal, 34...Input resistance, 3
5, 36...Diode, 37...Input wiring, 3
8...Logic circuit, 39...Pull-up resistor, 40
...MOS field effect transistor, 41...output terminal.
Claims (1)
域もしくは出力端子に接続される拡散領域に隣接
してこれら入力保護ダイオード領域もしくは前記
拡散領域と同導電型領域を形成し、前記入力端子
もしくは前記出力端子に高電圧が加わつた時、該
同導電型領域が前記入力保護ダイオード領域もし
くはドレイン領域に空乏層によつて接続せしめら
れることを特徴とする保護回路。1. A region of the same conductivity type as the input protection diode region or the diffusion region is formed adjacent to the input protection diode region connected to the input terminal or the diffusion region connected to the output terminal, and A protection circuit characterized in that when a high voltage is applied, the same conductivity type region is connected to the input protection diode region or the drain region by a depletion layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20300486A JPS6356957A (en) | 1986-08-28 | 1986-08-28 | Protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20300486A JPS6356957A (en) | 1986-08-28 | 1986-08-28 | Protection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6356957A JPS6356957A (en) | 1988-03-11 |
| JPH0553075B2 true JPH0553075B2 (en) | 1993-08-09 |
Family
ID=16466737
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20300486A Granted JPS6356957A (en) | 1986-08-28 | 1986-08-28 | Protection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6356957A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2780289B2 (en) * | 1988-11-17 | 1998-07-30 | セイコーエプソン株式会社 | Semiconductor device |
| JP2003072076A (en) | 2001-08-31 | 2003-03-12 | Canon Inc | Recording head and recorder using the same |
-
1986
- 1986-08-28 JP JP20300486A patent/JPS6356957A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6356957A (en) | 1988-03-11 |
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|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |