JPH0410225B2 - - Google Patents
Info
- Publication number
- JPH0410225B2 JPH0410225B2 JP58119079A JP11907983A JPH0410225B2 JP H0410225 B2 JPH0410225 B2 JP H0410225B2 JP 58119079 A JP58119079 A JP 58119079A JP 11907983 A JP11907983 A JP 11907983A JP H0410225 B2 JPH0410225 B2 JP H0410225B2
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- operating voltage
- vss
- power supply
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000003068 static effect Effects 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 11
- 230000005611 electricity Effects 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 239000000758 substrate Substances 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000006378 damage Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
(1) 発明の技術分野
本発明はＣ−MOS回路の如く電源ライン間イ
ンピーダンスが高い回路で構成した集積回路に対
して、外部から侵入する静電荷を効率良く排除し
うる静電保護回路を有する半導体装置に関する。[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention efficiently eliminates static charge that enters from the outside into an integrated circuit configured with a circuit with high impedance between power supply lines, such as a C-MOS circuit. The present invention relates to a semiconductor device having a static electricity protection circuit.
(2) 技術の背景及び従来技術の問題点
Ｃ−MOS回路は電源ライン間インピーダンス
が高く、定常状態では電源電流は流れず、従つて
消費電力が小である。このような電源間インピー
ダンスが高い回路に静電荷が入つてくると内部で
電源線間に高電位差が発生し、内部に形成された
素子が破壊されることになる。(2) Background of the Technology and Problems with the Prior Art A C-MOS circuit has high impedance between power supply lines, and no power supply current flows in a steady state, so power consumption is small. When static charge enters such a circuit with high impedance between power supplies, a high potential difference is generated between the power supply lines internally, and the elements formed inside are destroyed.
(3) 発明の目的
本発明は上記従来の問題点に鑑み、Ｃ−MOS
回路の如く電源ライン間インピーダンスが高い回
路に、外部から侵入する静電荷を効率良く排除す
ることができ、内部に形成された素子の破壊を防
止しうる静電保護回路を有する半導体装置を提供
することを目的とする。(3) Purpose of the Invention In view of the above-mentioned conventional problems, the present invention provides a C-MOS
To provide a semiconductor device having an electrostatic protection circuit capable of efficiently eliminating electrostatic charge entering from the outside into a circuit having high impedance between power supply lines such as a circuit, and capable of preventing destruction of elements formed inside. The purpose is to
(4) 発明の構成
そしてこの目的は本発明によれば、半導体チツ
プ内に第１動作電圧（Vcc）を供給する電源パツ
ドと、一端が該電源パツドに接続される抵抗Ｒ１
と、前記第１動作電圧（Vcc）とは異なる第２動
作電圧（Vss）と、該抵抗の他端との間に接続さ
れる内部回路素子と、外部から該電源パツドへの
静電気印加によつてオンし、通常の動作電圧では
オンせず、かつ該内部回路素子の耐圧よりも低い
しきい値電圧を有し、かつ前記第２動作電圧
（Vss）と該抵抗Ｒ１の他端との間を、ソース・
ドレインが接続し、ゲートが該抵抗Ｒ１の他端に
接続される第１トランジスタＱ１と、外部から該
電源パツドへの静電気印加によつてオンし、通常
の動作電圧ではオンせず、かつ該内部回路素子の
耐圧よりも低いしきい値電圧を有し、かつ前記第
２動作電圧（Vss）と該抵抗Ｒ１の他端との間
を、ソース・ドレインが接続し、ゲートが該第２
動作電圧に接続される第２トランジスタＱ２とを
有する半導体装置を提供することによつて達成さ
れる。(4) Structure of the Invention According to the present invention, a power supply pad for supplying a first operating voltage (Vcc) into a semiconductor chip, and a resistor R1 connected to the power supply pad at one end are provided.
and a second operating voltage (Vss) different from the first operating voltage (Vcc), an internal circuit element connected between the other end of the resistor, and an external static electricity applied to the power supply pad. the second operating voltage (Vss) and the other end of the resistor R1. The source
A first transistor Q1 whose drain is connected and whose gate is connected to the other end of the resistor R1 is turned on by applying static electricity from the outside to the power supply pad, is not turned on at normal operating voltage, and is connected to the inside of the transistor Q1. The source/drain has a threshold voltage lower than the breakdown voltage of the circuit element, and the second operating voltage (Vss) is connected to the other end of the resistor R1, and the gate is connected to the second operating voltage (Vss) and the other end of the resistor R1.
This is achieved by providing a semiconductor device having a second transistor Q2 connected to an operating voltage.
(5) 発明の実施例
第１図の回路は本発明の原理を示すもので、半
導体チツプ内への動作電圧を供給する電源バツド
Vcc、Vssの近くに、抵抗Ｒ１，Ｒ２および４個
のトランジスタＱ１……Ｑ４を配置する。Ｒ１，
Ｒ２は、静電荷の衝撃（インパクト）は緩和する
が、電源電流供給に支障のない程度に低い値のも
のとし、また多結晶シリコンの如く基板との間に
ｐ−ｎジヤンクシヨン（接合）を構成しない物質
で形成する。トランジスタＱ１……Ｑ４は外部か
ら侵入する静電荷を排除するために配置される。(5) Embodiments of the Invention The circuit shown in Figure 1 shows the principle of the present invention, and the circuit shown in Fig.
Resistors R1, R2 and four transistors Q1...Q4 are placed near Vcc and Vss. R1,
R2 should be set to a value low enough to alleviate the impact of static charges but not hinder the power supply current supply, and to form a p-n junction with the substrate, such as polycrystalline silicon. Formed from substances that do not. Transistors Q1...Q4 are arranged to eliminate static charges entering from the outside.
Ｑ１……Ｑ４はしきい値電圧の高い（例えば
10V〜20V）フイールドトランジスタとし、通常
の動作状態では導通しないが、静電荷の如く大な
る電位が侵入するとオンになり、静電荷を吸収し
バイパスさせるものとする。 Q1...Q4 has a high threshold voltage (for example
It is a field transistor (10V to 20V) that does not conduct under normal operating conditions, but turns on when a large potential such as static charge enters, absorbing the static charge and bypassing it.
更に、抵抗Ｒ１，Ｒ２は通常の動作状態におい
ては半導体チツプの特性に影響を与えないよう、
内部回路に求められる特性に応じて選定する。 Furthermore, resistors R1 and R2 are designed so as not to affect the characteristics of the semiconductor chip under normal operating conditions.
Select according to the characteristics required for the internal circuit.
例えばVccから侵入する正の静電気はその衝撃
が先ずＲ１で緩和され、Ｑ１，Ｑ３を通じてVss
側へ逃され、Vcc−Vss間の電位差が押えられ、
内部素子間電位差を押えることが可能となり、そ
の結果静電ストレスに対する耐性を得ることがで
きる。 For example, when positive static electricity enters from Vcc, the impact is first alleviated by R1, and then passed through Q1 and Q3 to Vss.
side, the potential difference between Vcc and Vss is suppressed,
It becomes possible to suppress the potential difference between internal elements, and as a result, resistance to electrostatic stress can be obtained.
上記した回路は第２図に、そのａには回路図
で、ｂには半導体装置の平面図で、またｃには同
図ｂにおける線ABCに沿う断面図で示され、線
AB、線BCに対応する部分は同図ｃには、Ａ，
Ｂ，Ｃの符号を付して示す。なお第２図以下にお
いて既に図示した部分と同じ部分は同じ符号を付
して表示するとして、第２図において、１は半導
体基板、２はVccパツドを形成するアルミニウム
配線、３は絶縁膜、４はフイールド絶縁膜、５は
多結晶シリコン（ポリシリコン）層、６はコンタ
クトホール、７はソース・ドレイン用拡散領域、
８は内部回路へ延びるVccライン、９は内部回路
末端となるVssラインを示す。ポリシリコン層５
はＲ１を構成し、Ｑ１，Ｑ２は第２図ｄに示され
る如くに構成される。 The above-mentioned circuit is shown in FIG. 2, in which a is a circuit diagram, b is a plan view of the semiconductor device, and c is a cross-sectional view taken along line ABC in b of the same figure.
The parts corresponding to AB and line BC are A,
They are indicated by the symbols B and C. Note that in FIG. 2 and subsequent figures, the same parts as those already illustrated are designated by the same reference numerals. In FIG. 2, 1 is a semiconductor substrate, 2 is an aluminum wiring forming a Vcc pad, 3 is an insulating film, and 4 is 5 is a field insulating film, 5 is a polycrystalline silicon (polysilicon) layer, 6 is a contact hole, 7 is a source/drain diffusion region,
Reference numeral 8 indicates a Vcc line extending to the internal circuit, and 9 indicates a Vss line at the end of the internal circuit. polysilicon layer 5
constitutes R1, and Q1 and Q2 are constituted as shown in FIG. 2d.
第２図に示される構成において、Vccパツド
（アルミニウム配線）２をVssパツドへ、Ｒ１を
Ｒ２へ、Ｑ１をＱ４へ、Ｑ２をＱ３へ変更する
と、Vssパツド側パターンが構成できる。 In the configuration shown in FIG. 2, by changing Vcc pad (aluminum wiring) 2 to Vss pad, R1 to R2, Q1 to Q4, and Q2 to Q3, a Vss pad side pattern can be constructed.
Ｒ１，Ｒ２の値としては、内部回路の消費電流
の変化量と内部回路の電源ノイズに対する耐性に
よつて異なるが、100ｍＡの消費電流の素子であ
れば、０〜1Ωが望ましく、一般的に、回路保護
のためには高い方が、また内部回路の安定動作の
ためには低い方が望ましい。 The values of R1 and R2 vary depending on the amount of change in the current consumption of the internal circuit and the resistance of the internal circuit to power supply noise, but for an element with a current consumption of 100 mA, a value of 0 to 1 Ω is desirable, and generally, A higher value is desirable for circuit protection, and a lower value is desirable for stable operation of the internal circuit.
第１図の回路と内部回路の関係を第３図に示
す。図示のインバータ１１は集積回路を構成する
ものの一つで、Ｐチヤネルトランジスタ１２とＮ
チヤネルトランジスタ１３とが直列に配置され、
入力１４は両トランジスタに共通につながり、ま
た両トランジスタの間から出力１５が取り出され
る。 FIG. 3 shows the relationship between the circuit of FIG. 1 and the internal circuit. The illustrated inverter 11 is one of the components constituting an integrated circuit, and includes a P channel transistor 12 and an N channel transistor 12.
A channel transistor 13 is arranged in series,
Input 14 is commonly connected to both transistors, and output 15 is taken out between both transistors.
かかるインバータにおいて、VccおよびVssの
電圧は通常の動作状態においてそれぞれ5V、0V
である。またVccとインバータ１１との間にはＲ
３を配置する。 In such an inverter, the Vcc and Vss voltages are 5V and 0V, respectively, under normal operating conditions.
It is. Also, there is R between Vcc and inverter 11.
Place 3.
本発明によると、静電荷の侵入に対し、Ｒ３が
静電荷による急激な衝撃を防止するだけでなく、
トランジスタ１６、トランジスタ１７を図示の如
くに配置し、これらトランジスタのしきい値電圧
を10V〜20Vに設定することによつてインバータ
が保護される。 According to the present invention, R3 not only prevents sudden impact caused by static charges, but also
The inverter is protected by arranging the transistors 16 and 17 as shown and setting the threshold voltages of these transistors to 10V to 20V.
Vccバツドに正の静電荷が入つた場合、第４図
を参照すると、トランジスタ１６に印加される電
圧＋VGが10V以上の時トランジスタがオンし、
電流は矢印の方向に流れてVssに吸収される。な
お、トランジスタ１６のしきい値VTHは約10Vと
する。 When a positive static charge is applied to the Vcc voltage, referring to FIG. 4, when the voltage +V G applied to the transistor 16 is 10V or more, the transistor turns on.
The current flows in the direction of the arrow and is absorbed by Vss. Note that the threshold value V TH of the transistor 16 is approximately 10V.
以上説明したように、抵抗Ｒ１およびしきい値
の高いFETであるトランジスタ１６，１７を配
置し、抵抗Ｒ１は基板との間にＰ−ｎ接合を構成
しない例えば０〜1Ωの値のものとし、トランジ
スタのしきい値電圧は内部回路素子の耐圧より低
く前記の如く約10Vとした。 As explained above, the resistor R1 and the transistors 16 and 17, which are FETs with high threshold values, are arranged, and the resistor R1 has a value of, for example, 0 to 1 Ω, which does not form a P-n junction with the substrate. The threshold voltage of the transistor was set to about 10 V, which is lower than the withstand voltage of the internal circuit elements, as described above.
Vss端子に正の静電荷が入つた場合、第５図を
参照すると、−Ｖが10V以上の時にしきい値電圧
が約10Vのトランジスタ１７がオンし、電流は矢
印の方向に流れてVccに吸収される。 When a positive static charge enters the Vss terminal, referring to Figure 5, when -V is 10V or more, the transistor 17 whose threshold voltage is approximately 10V is turned on, and the current flows in the direction of the arrow and reaches Vcc. Absorbed.
(6) 発明の効果
以上詳細に説明した如く、半導体素子に侵入し
た正、負の静電荷は、抵抗、トランジスタをそれ
ぞれ配置することによつて有効に選択的に対処さ
れ、内部素子の破壊が防止されるので、静電スト
レスに対する耐性を向上するに効果大である。(6) Effects of the Invention As explained in detail above, positive and negative static charges that have entered the semiconductor element can be effectively and selectively dealt with by arranging resistors and transistors, thereby preventing destruction of internal elements. This is highly effective in improving resistance to electrostatic stress.
第１図は本発明の実施例を示す回路図、第２図
ａ〜ｄは第１図の回路を具体的に示す図、第３図
は第１図と内部回路との関係を示す回路図、第４
図と第５図は第３図の回路の一部の動作を示す図
である。
図中、１は半導体基板、２はVccパツド（アル
ミニウム配線）、３は絶縁膜、４はフイールド絶
縁膜、５はポリシリコン層、６はコンタクトホー
ル、７はソース・ドレイン拡散領域、８はVccラ
イン、９はVssライン、１１はインバータ、１
２，１７はトランジスタ、１３，１６はトランジ
スタ、１４は入力、１５は出力、Ｑ１…Ｑ４はト
ランジスタ、Ｒ１…Ｒ３は抵抗。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIGS. 2 a to d are diagrams specifically showing the circuit in FIG. 1, and FIG. 3 is a circuit diagram showing the relationship between FIG. 1 and internal circuits. , 4th
5 and 5 are diagrams showing the operation of a portion of the circuit of FIG. 3. In the figure, 1 is a semiconductor substrate, 2 is a Vcc pad (aluminum wiring), 3 is an insulating film, 4 is a field insulating film, 5 is a polysilicon layer, 6 is a contact hole, 7 is a source/drain diffusion region, and 8 is a Vcc line, 9 is Vss line, 11 is inverter, 1
2 and 17 are transistors, 13 and 16 are transistors, 14 is an input, 15 is an output, Q1...Q4 are transistors, and R1...R3 are resistors.
Claims (1)
給する電源パツドと、 一端が該電源パツドに接続される抵抗Ｒ１と、 前記第１動作電圧（Vcc）とは異なる第２動作
電圧（Vss）と、該抵抗の他端との間に接続され
る内部回路素子と、 外部から該電源パツドへの静電気印加によつて
オンし、通常の動作電圧ではオンせず、かつ該内
部回路素子の耐圧よりも低いしきい値電圧を有
し、かつ前記第２動作電圧（Vss）と該抵抗Ｒ１
の他端との間を、ソース・ドレインが接続し、ゲ
ートが該抵抗Ｒ１の他端に接続される第１トラン
ジスタＱ１と、 外部から該電源パツドへの静電気印加によつて
オンし、通常の動作電圧ではオンせず、かつ該内
部回路素子の耐圧よりも低いしきい値電圧を有
し、かつ前記第２動作電圧（Vss）と該抵抗Ｒ１
の他端との間を、ソース・ドレインが接続し、ゲ
ートが該第２動作電圧に接続される第２トランジ
スタＱ２と を有する半導体装置。[Claims] 1. A power supply pad that supplies a first operating voltage (Vcc) into a semiconductor chip, a resistor R1 having one end connected to the power supply pad, and a resistor R1 that supplies a first operating voltage (Vcc) into the semiconductor chip; 2 The internal circuit element connected between the operating voltage (Vss) and the other end of the resistor turns on when static electricity is applied from the outside to the power supply pad, does not turn on at normal operating voltage, and has a threshold voltage lower than the withstand voltage of the internal circuit element, and has the second operating voltage (Vss) and the resistor R1.
A first transistor Q1 whose source and drain are connected to the other end of the resistor R1 and whose gate is connected to the other end of the resistor R1 is turned on by applying static electricity from the outside to the power supply pad, and is turned on as usual. does not turn on at the operating voltage, has a threshold voltage lower than the withstand voltage of the internal circuit element, and is connected to the second operating voltage (Vss) and the resistor R1.
and a second transistor Q2 whose source and drain are connected to the other end thereof and whose gate is connected to the second operating voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58119079A JPS6010767A (en) | 1983-06-30 | 1983-06-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58119079A JPS6010767A (en) | 1983-06-30 | 1983-06-30 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6010767A JPS6010767A (en) | 1985-01-19 |
| JPH0410225B2 true JPH0410225B2 (en) | 1992-02-24 |
Family
ID=14752353
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58119079A Granted JPS6010767A (en) | 1983-06-30 | 1983-06-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6010767A (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60257558A (en) * | 1984-06-04 | 1985-12-19 | Nec Corp | Semiconductor integrated circuit device |
| JPH0724310B2 (en) * | 1987-01-23 | 1995-03-15 | 松下電子工業株式会社 | Semiconductor device |
| EP0276850A3 (en) * | 1987-01-28 | 1990-06-27 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device with latch up preventing structure |
| JP2806532B2 (en) * | 1988-09-28 | 1998-09-30 | 日本電気アイシーマイコンシステム株式会社 | Semiconductor integrated circuit device |
| JP2953192B2 (en) * | 1991-05-29 | 1999-09-27 | 日本電気株式会社 | Semiconductor integrated circuit |
| KR930005184A (en) * | 1991-08-21 | 1993-03-23 | 김광호 | Semiconductor device for preventing electrostatic voltage |
| JP3184148B2 (en) | 1998-04-15 | 2001-07-09 | 日本電気アイシーマイコンシステム株式会社 | Semiconductor integrated circuit device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51104278A (en) * | 1975-03-12 | 1976-09-14 | Suwa Seikosha Kk | |
| JPS574151A (en) * | 1980-06-11 | 1982-01-09 | Hitachi Ltd | Mos integrated circuit device |
-
1983
- 1983-06-30 JP JP58119079A patent/JPS6010767A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51104278A (en) * | 1975-03-12 | 1976-09-14 | Suwa Seikosha Kk | |
| JPS574151A (en) * | 1980-06-11 | 1982-01-09 | Hitachi Ltd | Mos integrated circuit device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6010767A (en) | 1985-01-19 |
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