JPS63200560A - Cmos semiconductor device - Google Patents
Cmos semiconductor deviceInfo
- Publication number
- JPS63200560A JPS63200560A JP62033857A JP3385787A JPS63200560A JP S63200560 A JPS63200560 A JP S63200560A JP 62033857 A JP62033857 A JP 62033857A JP 3385787 A JP3385787 A JP 3385787A JP S63200560 A JPS63200560 A JP S63200560A
- Authority
- JP
- Japan
- Prior art keywords
- well
- region
- guard band
- gate electrode
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000000926 separation method Methods 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 description 14
- 238000000034 method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はＣＭＯＳ型半導体装置、詳しくは、そのガード
バンド構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a CMOS type semiconductor device, and more particularly to its guard band structure.
従来の技術
近年、半導体集積回路装置の高密度化が進み、特にＣＭ
ＯＳ型半導体集積回路装置は低消費電力という特性を備
えているため、広（用いられている。Background of the Invention In recent years, semiconductor integrated circuit devices have become more densely packed, especially in CM
OS type semiconductor integrated circuit devices are widely used because they have the characteristic of low power consumption.
以下に従来のＣＭＯＳ型半導体集積回路装置について説
明する。A conventional CMOS type semiconductor integrated circuit device will be explained below.
第、３図は、従来のＣＭＯＳ型半導体集積回路装置のイ
ンバータの一部を示すものである。このインバータはＰ
チャネルＭＯ８）ランジスタ（以下Ｐ−ＭＯ３Ｔと略す
）とＮチャネルＭＯ８）ランジスタ（以下Ｎ−ＭＯ８Ｔ
と略す）のそれぞれのゲート電極を共通にして入力信号
を印加し、Ｐ−ＭＯ３Ｔのソース電極に電源電圧を印加
し、Ｎ−ＭＯ８Ｔのソースを接地電位になして、Ｎ−Ｍ
Ｏ３ＴおよびＰ−ＭＯ８Ｔの各ドレイン電極を共通にし
て出力信号を取り出す。第３図はＣＭＯＳ型Ｏ８バータ
の要所平面図、第４図は第３図のｂ−ｂ ゛断面図であ
る。第３図および第４図中、ｌはＰ−ウェル、２はＮ−
ウェル、３はガードバンドと呼ばれるＮ型拡散層、４は
ゲート電極配線層、５゜６はＰ−ＭＯ８Ｔのドレイン、
ソース電極領域、７．８はＮ−ＭＯ８Ｔのドレインソー
ス電極領域、９は絶縁膜である。FIG. 3 shows a part of an inverter of a conventional CMOS type semiconductor integrated circuit device. This inverter is P
Channel MO8) transistor (hereinafter abbreviated as P-MO3T) and N channel MO8) transistor (hereinafter N-MO8T)
), the input signal is applied to the gate electrode of each of the N-M
The drain electrodes of O3T and P-MO8T are made common and output signals are taken out. FIG. 3 is a plan view of important parts of the CMOS type O8 converter, and FIG. 4 is a sectional view taken along line bb in FIG. 3. In FIGS. 3 and 4, l is P-well, 2 is N-well
well, 3 is an N-type diffusion layer called a guard band, 4 is a gate electrode wiring layer, 5°6 is the drain of P-MO8T,
A source electrode region, 7.8 is a drain source electrode region of N-MO8T, and 9 is an insulating film.
ガードバンドのＮ型拡散層３、Ｎ−ＭＯ８Ｔのソースお
よびドレイン電極領域７．８は、それぞれの領域におい
て、同時にＮ型不純物を注入することにより形成する。The N-type diffusion layer 3 of the guard band and the source and drain electrode regions 7.8 of the N-MO8T are formed by simultaneously implanting N-type impurities in each region.
すなわち、ソースおよびドレイン電極領域７，８はゲー
ト電極配線層４をマスクとしてＮ型不純物を注入する、
いわゆる、自己整合技術によって形成する。しかし、ガ
ードバンド用のＮ型拡散層３もこの工程で同時に形成し
ようとすると、ゲート電極配線層４が横切るため、ゲー
ト電極配線層４との重なり部分でＮ型拡散層が分断され
る。That is, N-type impurities are implanted into the source and drain electrode regions 7 and 8 using the gate electrode wiring layer 4 as a mask.
It is formed by a so-called self-alignment technique. However, if the N-type diffusion layer 3 for the guard band is also formed at the same time in this step, the gate electrode wiring layer 4 crosses the N-type diffusion layer 3, so that the N-type diffusion layer is divided at the overlapped portion with the gate electrode wiring layer 4.
発明が解決しようとする問題点
上述の従来の構成では、ガードパント用のＮ型拡散層３
が分断されるため、ＣＭＯＳ型半導体装置特有のいわゆ
るラッチアップ現象が生じやすくなり、本来のガードパ
ントの機能が損なわれる。Problems to be Solved by the Invention In the conventional configuration described above, the N-type diffusion layer 3 for guard punt
As a result, the so-called latch-up phenomenon peculiar to CMOS type semiconductor devices tends to occur, and the original function of the guard punt is impaired.
すなわち、Ｐ−ＭＯ８Ｔのドレイン、ソース電極領域５
，６、Ｎ−ウェル２、Ｐ−ウェル１、Ｎ−ＭＯ８Ｔのド
レイン、ソース電極領域７，８により、４層のＰＮＰＮ
構造となり、サイリスタと同様の構造となる。That is, the drain and source electrode regions 5 of P-MO8T
, 6, N-well 2, P-well 1, N-MO8T drain and source electrode regions 7 and 8, resulting in four layers of PNPN.
The structure is similar to that of a thyristor.
上記の構造において接地電位に接続したＰ−ウェルより
約０．７Ｖ低いノイズなどの電圧が出力端子に加わると
、出力端子に接続したＮ−ＭＯ８Ｔのドレイン電極領域
８からＰ−ウェル１に電子が注入され、その注入された
電子の一部がＰ−ウェル１を拡散した後、Ｎ−ウェル２
に到達し、Ｎ−ウェル２中を電源電圧に接続されたガー
ドバンドの拡散層３ヘトリフトする。このドリフト電流
が引き起こす電圧降下により、電源に接続されたＰ−Ｍ
Ｏ８Ｔのソース電極領域６の近傍でＮ−ウェル中２に同
ソース電極領域６から正孔の注入がおこる。注入された
正孔は上に述べた注入電子と同様の過程をたどって、Ｎ
−ＭＯ８Ｔのソース電極領域８からＰ−ウェル１への電
子の注入を引きおこす。ラッチアップ現象は、これらの
過程の繰返しから引き起こされるものである。Ｎ−ウェ
ル２に電源電圧を供給するガードバンドのＮ型拡散層３
が分断されていると、ラッチアップが生じやすくなる。In the above structure, when a voltage such as noise that is approximately 0.7 V lower than the P-well connected to the ground potential is applied to the output terminal, electrons are transferred from the drain electrode region 8 of the N-MO8T connected to the output terminal to the P-well 1. After some of the injected electrons diffuse through P-well 1, N-well 2
, and is lifted into the N-well 2 to the guard band diffusion layer 3 connected to the power supply voltage. The voltage drop caused by this drift current causes the P-M connected to the power supply to
Holes are injected from the source electrode region 6 of O8T into the N-well medium 2 in the vicinity of the source electrode region 6 of the O8T. The injected holes follow the same process as the injected electrons mentioned above, and become N
- Causes injection of electrons from the source electrode region 8 of MO8T into the P-well 1. The latch-up phenomenon is caused by repetition of these processes. Guard band N-type diffusion layer 3 that supplies power supply voltage to the N-well 2
If they are separated, latch-up is more likely to occur.
そのためＣＭＯＳ型半導体装置の動作信頼性低下を引き
起こすという欠点を有していた。This has the disadvantage of causing a reduction in the operational reliability of the CMOS type semiconductor device.
本発明は上記従来の問題点を解決するもので、ラッチア
ップ現象を抑制するＣＭＯ３型半導体装置を提供するこ
とを目的とする。The present invention solves the above-mentioned conventional problems, and aims to provide a CMO3 type semiconductor device that suppresses the latch-up phenomenon.
問題点を解決するための手段
この目的を達成するために１本発明は、ゲート電極配線
層直下の所定ウェル内に、同ウェルと同一導電型の高濃
度領域をそなえ、前記高濃度領域を前記ウェル領域中に
配設された同導電型のガードバンド領域と重なり合わせ
た構成のＣＭＯＳ型半導体装置である。Means for Solving the Problems In order to achieve this object, the present invention provides a high concentration region of the same conductivity type as the well in a predetermined well directly below the gate electrode wiring layer, and This is a CMOS type semiconductor device having a configuration in which a guard band region of the same conductivity type provided in a well region overlaps with the guard band region.
作用
この構成によって、ガードバンド領域が、ゲート電極配
線層にあらかじめ設けられたＮ型拡散層により分断され
ずに一体化され、Ｎ−ウェルの電位の降下を防ぎ、ラッ
チアップ現象を抑制することができる。Effect: With this configuration, the guard band region is integrated without being separated by the N-type diffusion layer provided in advance in the gate electrode wiring layer, thereby preventing a drop in the potential of the N-well and suppressing the latch-up phenomenon. can.
実施例
以下本発明の一実施例について、図面を参照しながら説
明する。EXAMPLE An example of the present invention will be described below with reference to the drawings.
第１図は本発明の実施例におけるＣＭＯＳ型Ｏ８バータ
の要所平面図、第２図は第１図のａ−ａ’断面図である
。同図中の符号１〜９は従来の実施例の場合と同様であ
り、１０はＮ型拡散層である。FIG. 1 is a plan view of important parts of a CMOS type O8 converter according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along the line aa' in FIG. Reference numerals 1 to 9 in the figure are the same as in the conventional embodiment, and 10 is an N-type diffusion layer.
Ｎ型拡散層１０はゲート電極配線層形成の前工程で、他
の回路要素、たとえば、Ｐ型基板にＮ型拡散層を作り、
この領域にＭＯＳ構造容量を形成するとき、あるいは、
デプレッション型トランジスタのゲート電極下のチャネ
ルに拡散層を形成する工程と同時にすることができ、工
程数はＮ型拡散層１０を入れることによっても変化しな
い。The N-type diffusion layer 10 is formed on other circuit elements, for example, on a P-type substrate, in the process before forming the gate electrode wiring layer.
When forming a MOS structure capacitor in this region, or
This step can be performed simultaneously with the step of forming a diffusion layer in the channel under the gate electrode of the depletion type transistor, and the number of steps does not change even if the N-type diffusion layer 10 is included.
発明の効果
以上のように本発明によれば、ゲート電極配線層直下の
所定ウェル中に同一導電型の高濃度領域を設け、これに
自己整合で形成されるガードバンド領域を重なり合わせ
ることにより、ガードバンドの分断がなくなり、ラッチ
アップを抑制することができる優れたＣＭＯＳ型半導体
装置を実現できるものである。Effects of the Invention As described above, according to the present invention, by providing a high concentration region of the same conductivity type in a predetermined well directly below the gate electrode wiring layer and overlapping the guard band region formed by self-alignment, It is possible to realize an excellent CMOS type semiconductor device in which separation of the guard band is eliminated and latch-up can be suppressed.
第１図、第２図はそれぞれ本発明ＣＭＯＳ型インバータ
の要所平面図、同断面図、第３図、第４− 〇 −
図はそれぞれ従来のＣＭＯＳ型Ｏ８バータの要所平面図
、同断面図である。
■・・・・・・Ｐ−ウェル、２・・・・・・Ｎ−ウェル
、３・・・・・・ガードバンド、４・・・・・・ゲート
電極配線層、５，６・・・・・・Ｐ型ドレイン、ソース
電極領域、７，８・・・・・・Ｎ型ドレイン、ソース電
極領域、９・・・・・・絶縁膜、１０・・・・・・Ｎ型
拡散層。
代理人の氏名 弁理士 中尾敏男 はか１名７−−−
Ｐ−ウェル
２−Ｎ−フエルFigures 1 and 2 are a plan view and cross-sectional view of key points of the CMOS type inverter of the present invention, respectively, and Figures 3 and 4 are a plan view and cross-sectional view of key points of a conventional CMOS type O8 inverter, respectively. It is a diagram. ■... P-well, 2... N-well, 3... Guard band, 4... Gate electrode wiring layer, 5, 6... ... P type drain, source electrode region, 7, 8 ... N type drain, source electrode region, 9 ... insulating film, 10 ... N type diffusion layer. Name of agent: Patent attorney Toshio Nakao Haka1 person 7---
P-well 2-N-well
Claims (1)
一導電型の高濃度領域をそなえ、前記高濃度領域を前記
ウェル領域中に配設された同導電型のガードバンド領域
と重なり合わせたことを特徴とするＣＭＯＳ型半導体装
置。A high concentration region of the same conductivity type as the well is provided in a predetermined well directly below the gate electrode wiring layer, and the high concentration region is overlapped with a guard band region of the same conductivity type disposed in the well region. A CMOS type semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62033857A JPS63200560A (en) | 1987-02-17 | 1987-02-17 | Cmos semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62033857A JPS63200560A (en) | 1987-02-17 | 1987-02-17 | Cmos semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63200560A true JPS63200560A (en) | 1988-08-18 |
Family
ID=12398173
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62033857A Pending JPS63200560A (en) | 1987-02-17 | 1987-02-17 | Cmos semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63200560A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008198777A (en) * | 2007-02-13 | 2008-08-28 | Seiko Instruments Inc | Semiconductor device |
| CN109148448A (en) * | 2017-06-19 | 2019-01-04 | 中芯国际集成电路制造(上海)有限公司 | A kind of CMOS inverter and electronic device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6235557A (en) * | 1985-08-09 | 1987-02-16 | Agency Of Ind Science & Technol | Semiconductor device |
-
1987
- 1987-02-17 JP JP62033857A patent/JPS63200560A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6235557A (en) * | 1985-08-09 | 1987-02-16 | Agency Of Ind Science & Technol | Semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008198777A (en) * | 2007-02-13 | 2008-08-28 | Seiko Instruments Inc | Semiconductor device |
| CN109148448A (en) * | 2017-06-19 | 2019-01-04 | 中芯国际集成电路制造(上海)有限公司 | A kind of CMOS inverter and electronic device |
| CN109148448B (en) * | 2017-06-19 | 2020-09-01 | 中芯国际集成电路制造(上海)有限公司 | CMOS phase inverter and electronic device |
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