JPS61276252A - Cmos semiconductor device - Google Patents
Cmos semiconductor deviceInfo
- Publication number
- JPS61276252A JPS61276252A JP60117112A JP11711285A JPS61276252A JP S61276252 A JPS61276252 A JP S61276252A JP 60117112 A JP60117112 A JP 60117112A JP 11711285 A JP11711285 A JP 11711285A JP S61276252 A JPS61276252 A JP S61276252A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- type
- well
- drain
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 238000009792 diffusion process Methods 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 abstract description 4
- 230000015556 catabolic process Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0927—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising a P-well only in the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
- H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は相補型MO8半導体装置(以下CMOSトラン
ジスタという)に関し、特に高耐圧を有するNチャネル
MO8)ランジスタの構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a complementary MO8 semiconductor device (hereinafter referred to as a CMOS transistor), and particularly to the structure of an N-channel MO8 transistor having a high breakdown voltage.
従来、0MO8)ランジスタを構成するNチャネルMO
Sトランジスタは第2図に示すように、N型基板10に
Pウェル9が形成され、Pウェル9内に深さ約0.5〜
1.0μのソース拡散層1.ドレイン拡散層2.チャネ
ルストッパー7が配置され、そして厚さ約300〜80
0人のゲート酸化膜12上に厚さ4000〜7000人
のポリシリコンのゲート電極3が形成され、絶縁層とし
て厚さ約1μのフィールド酸化膜8及びゲート電極を覆
う厚さ約200〜1000人の酸化膜11が形成された
構造となっている。Conventionally, 0MO8) N-channel MO constituting a transistor
As shown in FIG. 2, in the S transistor, a P well 9 is formed in an N type substrate 10, and a depth of approximately 0.5 to
1.0μ source diffusion layer1. Drain diffusion layer 2. A channel stopper 7 is arranged and has a thickness of approximately 300-80 mm.
A polysilicon gate electrode 3 with a thickness of 4,000 to 7,000 µm is formed on a gate oxide film 12 of 0 µm, and a field oxide film 8 of about 1 µm in thickness as an insulating layer and a field oxide film 8 with a thickness of about 200 to 1,000 µm covering the gate electrode. The structure has an oxide film 11 formed therein.
NチャネルMO8)ランジスタは、0MO8トランジス
タ回路内において、Pウェル9及びソース拡散層1に対
しドレイン拡散層2に十の電圧が印加され、ゲート電極
3の電位を変化させることによシ、動作させることがで
きる。The N-channel MO8) transistor is operated by applying a voltage of 10 to the drain diffusion layer 2 with respect to the P well 9 and the source diffusion layer 1 and changing the potential of the gate electrode 3 in the 0MO8 transistor circuit. be able to.
上記従来構造のNチャネルMOSトランジスタを有する
0MO8ICは、5v以下の電源ラインで使用されるの
が一般的であるが、最近20V程度の耐圧を有する0M
O8ICが要求されてきている。しかしながらこの様な
高耐圧の0MO8ICは下記の理由によシ従来構造での
実現は難かしい。The 0MO8IC having the N-channel MOS transistor of the conventional structure is generally used in a power supply line of 5V or less, but recently the 0MO8IC has a withstand voltage of about 20V.
O8IC is required. However, it is difficult to realize such a high voltage 0MO8 IC with a conventional structure for the following reasons.
α) ドレイン耐圧を上げるためドレイ/接合を深くす
ると、ドレイン逆バイアスのとき空乏層がソース側にま
で伸び、耐圧が低下する。そのためチャネル長を大きく
とる必要があシ、微細化ができない欠点がある。α) If the drain/junction is deepened to increase the drain breakdown voltage, the depletion layer will extend to the source side when the drain is reverse biased, reducing the breakdown voltage. Therefore, it is necessary to have a large channel length, and there is a drawback that miniaturization is not possible.
(2) ドレイン逆バイアスの場合、ドレインのゲート
酸化膜直下で電界が集中し、ホールがPウェル内に注入
される。この注入電流が多くなるとソース、Pウェルビ
レ4フ間でnpnバイポーラトランジスタの動作が生じ
、大電流によシ素子の破壊が起る欠点がある。(2) In the case of drain reverse bias, the electric field concentrates directly under the gate oxide film of the drain, and holes are injected into the P-well. If this injection current increases, the operation of the npn bipolar transistor occurs between the source and the P-well bottom 4, which has the drawback of causing destruction of the silicon element due to the large current.
本発明の目的は上記欠点を除去し、高耐圧のCMOS半
導体装置を提供することにある。An object of the present invention is to eliminate the above-mentioned drawbacks and provide a CMOS semiconductor device with high breakdown voltage.
本発明のCMOS半導体装置はPウェル領域に形成され
たN型のソース拡散層及びドレイン拡散層と、このソー
ス拡散層を囲んでPウェル領域内に形成されたP+型拡
散層と、ドレイン拡散層の少くともチャネル領域側に形
成されたN−型拡散層とを含んでなるNチャンネルMO
Sトランジスタを有するものである。A CMOS semiconductor device of the present invention includes an N type source diffusion layer and a drain diffusion layer formed in a P well region, a P+ type diffusion layer surrounding the source diffusion layer and formed in the P well region, and a drain diffusion layer. an N-type diffusion layer formed at least on the channel region side of the
It has an S transistor.
次に、本発明の実施例について図面を診照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第1図は本発明の一実施例の断面図である。FIG. 1 is a sectional view of an embodiment of the present invention.
第1図において、Ni基板10上には表面濃度が5X1
0”個/ cm3程度のPウェル6が形成されておシ、
このPウェル6内にはN型のソース拡散層1及びドレイ
ン拡散層2が形成されている。そしてこのソース拡散層
1はPウェル6よシ高濃度のP+型拡散層4(表面濃度
〜1×1016個/am3)で囲まれており、一方ドレ
イン拡散層2は低濃度のN−型拡散層5(表面濃度〜1
×10個/cm)とケート側で接続されている。In FIG. 1, the surface concentration on the Ni substrate 10 is 5X1.
P-wells 6 of about 0"/cm3 are formed,
In this P well 6, an N type source diffusion layer 1 and a drain diffusion layer 2 are formed. The source diffusion layer 1 is surrounded by a P+ type diffusion layer 4 with a higher concentration than the P well 6 (surface concentration ~1 x 1016 atoms/am3), while the drain diffusion layer 2 is surrounded by a low concentration N- type diffusion layer 4. Layer 5 (surface concentration ~1
×10 pieces/cm) and connected on the gate side.
尚、ソース拡散層1及びドレイン拡散層2の深さは0.
3〜1.0μ、P+型拡散層4の深さは1.0〜3.0
μ、N−型拡散層5の深さは1.0−2.0μである。Note that the depth of the source diffusion layer 1 and the drain diffusion layer 2 is 0.
3 to 1.0μ, the depth of the P+ type diffusion layer 4 is 1.0 to 3.0μ
The depth of the .mu., N- type diffusion layer 5 is 1.0-2.0 .mu..
また、ソース拡散層1とドレイン拡散層20間のチャネ
ル長は3〜5μでアシ、チャネル部において、ソース拡
散層1のゲート側l端部からP+型拡散層4のゲート下
I縁端までの距離は1.0〜3.0μ、ドレイン拡散層
2のゲート側l端部からN−型拡散層5のゲート下I緑
端までの距離は1.0〜3.0μに構成されている。In addition, the channel length between the source diffusion layer 1 and the drain diffusion layer 20 is 3 to 5 μm. The distance is 1.0 to 3.0 .mu., and the distance from the gate side l end of the drain diffusion layer 2 to the gate lower I green end of the N- type diffusion layer 5 is 1.0 to 3.0 .mu..
このように構成された本発明の実施例によれば次のよう
な改良点がある。According to the embodiment of the present invention configured as described above, there are the following improvements.
α) N−型拡散層5によシトレイン耐圧を上げること
ができる。α) The N-type diffusion layer 5 can increase the cytrain breakdown voltage.
■ 従来構造ではドレイン拡散層2とPウェル9による
接合が逆バイアスされると空乏層は殆んどPウェル9側
に伸るが、本発明による構造においては、N−型拡散層
5側にも空乏層が伸びるためチャネル長を長くせず高耐
圧化が可能となる。■ In the conventional structure, when the junction between the drain diffusion layer 2 and the P-well 9 is reverse biased, the depletion layer mostly extends toward the P-well 9 side, but in the structure according to the present invention, the depletion layer extends toward the N-type diffusion layer 5 side. Also, since the depletion layer is extended, high breakdown voltage can be achieved without increasing the channel length.
(3) 更にソース側のP+型拡散層4が、上記空乏
層のストッパーとして働く。(3) Furthermore, the P+ type diffusion layer 4 on the source side acts as a stopper for the depletion layer.
(4) ドレイン側からホールがPウェル内に注入さ
れた場合、P+型拡散層4によりホールを吸収すること
ができる。(4) When holes are injected into the P well from the drain side, the holes can be absorbed by the P+ type diffusion layer 4.
以上説明した様に1本発明によればNチャネルMOSト
ランジスタの高耐圧化が可能とな夛、20V程度の耐圧
を有するCMOS半導体装置が得られるのでその効果は
大きい。As explained above, according to the present invention, it is possible to increase the withstand voltage of an N-channel MOS transistor, and a CMOS semiconductor device having a withstand voltage of about 20V can be obtained, which is highly effective.
第1図は本発明の一実施例の断面図、第2図は従来のC
MOS半導体装置の断面図でおる。
1・・・・・・ソース拡散層、2・・・・・・ドレイン
拡散層、3・・・・・・ゲート電極、4・・・・・・P
+型拡散層、5・旧・・N 型拡散層、6・・・・・・
Pウェル、7・・・・・・チャネルストッパー、8・・
・・・・フィールド酸化L 9・・・・・・Pウェル、
10・・・・・・N型基板、11・・・・・・ゲート絶
縁膜、12・・・・・・ゲート酸化膜。FIG. 1 is a sectional view of one embodiment of the present invention, and FIG. 2 is a conventional C
It is a sectional view of a MOS semiconductor device. 1... Source diffusion layer, 2... Drain diffusion layer, 3... Gate electrode, 4... P
+ type diffusion layer, 5, old...N type diffusion layer, 6...
P well, 7...Channel stopper, 8...
...Field oxidation L 9...P well,
10...N-type substrate, 11...Gate insulating film, 12...Gate oxide film.
Claims (1)
イン拡散層と、該ソース拡散層を囲んでPウェル領域内
に形成されたP^+型拡散層と、前記ドレイン拡散層の
少くともチャネル領域側に形成されたN^−型拡散層と
を含んでなるNチャンネルMOSトランジスタを有する
ことを特徴とするCMOS半導体装置。An N-type source diffusion layer and a drain diffusion layer formed in the P-well region, a P^+-type diffusion layer surrounding the source diffusion layer and formed in the P-well region, and at least a channel of the drain diffusion layer. A CMOS semiconductor device comprising an N-channel MOS transistor including an N^-type diffusion layer formed on a region side.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60117112A JPS61276252A (en) | 1985-05-30 | 1985-05-30 | Cmos semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60117112A JPS61276252A (en) | 1985-05-30 | 1985-05-30 | Cmos semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61276252A true JPS61276252A (en) | 1986-12-06 |
JPH0344425B2 JPH0344425B2 (en) | 1991-07-05 |
Family
ID=14703712
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60117112A Granted JPS61276252A (en) | 1985-05-30 | 1985-05-30 | Cmos semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61276252A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02307272A (en) * | 1989-05-22 | 1990-12-20 | Matsushita Electron Corp | Semiconductor device |
WO1996032747A1 (en) * | 1995-04-12 | 1996-10-17 | National Semiconductor Corporation | Structure and fabrication of mosfet having multi-part channel |
US6020227A (en) * | 1995-09-12 | 2000-02-01 | National Semiconductor Corporation | Fabrication of multiple field-effect transistor structure having local threshold-adjust doping |
-
1985
- 1985-05-30 JP JP60117112A patent/JPS61276252A/en active Granted
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02307272A (en) * | 1989-05-22 | 1990-12-20 | Matsushita Electron Corp | Semiconductor device |
WO1996032747A1 (en) * | 1995-04-12 | 1996-10-17 | National Semiconductor Corporation | Structure and fabrication of mosfet having multi-part channel |
US5744372A (en) * | 1995-04-12 | 1998-04-28 | National Semiconductor Corporation | Fabrication of complementary field-effect transistors each having multi-part channel |
US6078082A (en) * | 1995-04-12 | 2000-06-20 | National Semiconductor Corporation | Field-effect transistor having multi-part channel |
US6576966B1 (en) | 1995-04-12 | 2003-06-10 | National Semiconductor Corporation | Field-effect transistor having multi-part channel |
US6020227A (en) * | 1995-09-12 | 2000-02-01 | National Semiconductor Corporation | Fabrication of multiple field-effect transistor structure having local threshold-adjust doping |
US6127700A (en) * | 1995-09-12 | 2000-10-03 | National Semiconductor Corporation | Field-effect transistor having local threshold-adjust doping |
Also Published As
Publication number | Publication date |
---|---|
JPH0344425B2 (en) | 1991-07-05 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |